A 1.8-V 2.4-GHz Monolithic CMOS Inductor-less Frequency … · 2003-08-14 · A 1.8-V 2.4-GHz Monolithic CMOS Inductor-less Frequency Synthesizer for Bluetooth Application By Wong

A 1.8-V 2.4-GHz Monolithic CMOS

Inductor-less Frequency Synthesizer

for Bluetooth Application

By

Wong Man Chun

A Thesis Submitted to

The Hong Kong University of Science and Technology

in partial fulfillment of the requirements for

the Degree of Master of Philosophy

in Electrical and Electronic Engineering

August, 2002, Hong Kong

Authorization

I hereby declare that I am the sole author of the thesis.

I authorize the Hong Kong University of Science and

Technology to lend this thesis to other institutions or individuals for

the purpose of scholarly research.

I further authorize the Hong Kong University of Science and

Technology to reproduce the thesis by photocopying or by other

means, in total or in part, at the request of other institutions or

individuals for the purpose of scholarly research.

___________________________________________

Wong Man Chun


Inductor-less Frequency Synthesizer

for Bluetooth Application

By

Wong Man Chun

This is to certify that I have examined the above Master thesis

and have found that it is complete and satisfactory in all respects,

and that any and all revisions required by

the thesis examination committee have been made.

Dr. Howard Cam LUONG

Thesis Supervisor

Prof. Johnny K. O. SIN

Thesis Examination Committee Member (Chairman)

Dr. Philip K. T. Mok

Thesis Examination Committee Member

Prof. Philip C. H. CHAN

Head of Department

Department of Electrical and Electronic Engineering


August 2002

i


Inductor-less Frequency Synthesizer for

Bluetooth Application

By

Wong Man Chun

Electrical and Electronic Engineering


Abstract

Bluetooth is a new wireless standard that uses short-range radio links

to replace the cables connecting portable and/or fixed electronic devices.

The standard defines a uniform structure for a wide range of devices to

communicate with each other. The goal of Bluetooth transceivers is to

achieve robustness, low complexity, low power and low cost.

Conventional monolithic frequency synthesizer is difficult to fulfil the

Bluetooth specifications . Traditional designs usually generate a 2.4-GHz

signal using LC-oscillators with on-chip spiral inductors. These inductors

have low quality factors, occupy a large chip area, and are quite sensitive to

process variation, which degrade the performance in terms of cost, power

and production yield.

ii

This thesis presents a 1.8-V 2.4-GHz monolithic CMOS inductor-less

frequency synthesizer that meets all the Bluetooth specifications. The design

employs a fractional-N architecture with a novel frequency doubler to

achieve a 2.4GHz operating frequency. Because the oscillating frequency is

half, a ring oscillator can be used to replace the LC-oscillator to achieve wide

tuning range with a minimum chip area. In addition, the complexity and the

requirement of other building blocks, likes frequency divider and multi-

modulus divider can be relaxed.

Implemented in a 0.35µm CMOS process and measured at a 1.8V

voltage supply, the results can meet all the requirements of Bluetooth

specification. Operating at 2.448GHz, the design consumes 55.9mW and

achieves a phase noise of –92.5dBc/Hz@500kHz with a tuning range of

12%. The settling time is 55µs and the core chip area is 0.69mm2.

iii

Acknowledgments

I would like to express my gratitude to many people who have given

me a lot advice, supports and happiness throughout the two years master

program in the HKUST.

First, I would like to thank Dr. Howard Cam Luong for his guidance,

supports and care. He has been my research supervisor since I was working

on the final year project in my undergraduate study. He has encouraged and

supported me throughout the entire research. I am very grateful to him for

his invaluable guidance.

I would like to thank Fred Kwok and S. F. Luk for their technical

supports in measurement and equipment setups. I would also very grateful

to my friends in analog research laboratory, Alan Chan, Chan Chit Sang,

Gary Wong, Gerry Leung, Guo Chun bing, Ho Ka Wai, Kenneth Ng, Lincoln

Leung, Martin Chui, Tam Yiu Ming, Vincent Cheung, They share fun,

experience, knowledge, happiness with me.

I would like to thank Dr. Jonny Sin and Dr. Philip Mok for being my

thesis examination committee.

Last but not least, I would like to thank my family for their support and

care during my entire school-life.

iv

Table of Contents

Abstract i

Acknowledgment iii

Table of Contents iv

List of Figures vi

List of Tables ix

Chapter 1 Introduction1.1 Motivation1.2 Thesis organization

13

Chapter 2 Synthesizer Background2.1 Introduction2.2 General Considerations

2.2.1 Phase Noise2.2.2 Settling Time2.2.3 Chip Area

2.3 Fractional-N ArchitectureReference

4

5779

12

Chapter 3 Synthesizer Design3.1 Introduction3.2 Bluetooth System Specifications3.3 Design Specifications

3.3.1 Phase Noise Requirement3.3.2 Spurious Tone Specification3.3.3 Settling Time

3.4 Proposed Architecture3.4.1 Architecture Description3.4.2 Advantages of Proposed Architecture

3.4.2.1 Relax the Requirement of Ring Oscillator3.4.2.2 Smaller Chip Area and Faster Settling3.4.2.3 Larger Frequency Tuning Range

3.4.3 Disadvantages of Proposed Architecture3.5 Synthesizer Behavior Model

3.5.1 Behavior Model Description3.5.2 Loop Filter Implementation3.5.3 Open Loop Gain Analysis and Noise3.5.4 Noise3.5.5 Loop optimization and Stability

3.6 Summary of Proposed Specification

1314

161718

21

24252626

272830323340

v

Reference 41

Chapter 4 Circuit Implementation4.1 Introduction4.2 Frequency Doubler

4.2.1 Introduction & Design Specification4.2.2 Circuit Implementation

4.3 Voltage-Controlled Oscillator4.3.1 Introduction & Design Specification4.3.2 Circuit Implementation

4.4 High Speed Frequency Divider4.4.1 Introduction & Design Specification4.4.2 Circuit Implementation

4.5 Half Speed Frequency Divider & Multi-Modulus Divider4.5.1 Introduction & Design Specification4.5.2 Circuit Implementation

4.5.2.1 Half Speed Frequency Divider4.5.2.2 Multi-modulus Frequency Divider

4.6 Phase Frequency Detector & Charge Pump4.6.1 Introduction & Design Specification4.6.2 Circuit Implementation

4.6.2.1 Phase Frequency Detector4.6.2.2 Charge Pump4.6.2.3 Loop Filter

Reference

42

4345

5355

6061

67

6970

79

81828385

Chapter 5 Experimental Results5.1 Chip Fabrication5.2 Ring Oscillator5.3 Frequency Doubler5.4 Frequency Divider & Multi-Modulus Divider5.5 Proposed Frequency Synthesizer

5.5.1 Spurious Tone Performance5.5.2 Phase Noise5.5.3 Settling Time5.5.4 I-Q Mismatch

5.6 Summary of Measurement Results5.7 Comparison

Reference

87909599102103103105106108110112

Chapter 6 Conclusion 113

vi

List of FiguresFigure 1.1 Block diagram of Bluetooth receiver front-end 2

Figure 2.1 Phase noise in an oscillator output spectrum 5

Figure 2.2 Effect of synthesizer phase noise in a receiver 6

Figure 2.3 Block diagram of fractional-N synthesizer 10

Figure 3.1 Frequency allocation in Bluetooth specification 15

Figure 3.2 Output spectrum of synthesizer 17

Figure 3.3 Bluetooth time slots assignment 19

Figure 3.4 Conventional frequency synthesizers 22

Figure 3.5 Proposed frequency synthesizer architecture 23

Figure 3.6 Block diagram of the proposed architecture 27

Figure 3.7 Dual-path loop filter with dual charge pump 29

Figure 3.8 A Blot plot of open loop gain 30

Figure 3.9 Minimum loop bandwidth 34

Figure 3.10 Optimum loop bandwidth 35

Figure 3.11 Phase noise contribution at different offset frequencies 37

Figure 3.12 Simulated open loop transfer function 39

Figure 3.13 Simulated settling time 39

Figure 4.1 Location of frequency doubler 43

Figure 4.2 Analog mixer as a frequency doubler 44

Figure 4.3 Schematic of LC Oscillator 46

Figure 4.4 Block diagram of the proposed frequency doubler 46

Figure 4.5 Schematic diagram of the proposed frequency doubler 47

Figure 4.6 Idea of injection-mode technique 49

Figure 4.7 The idea of negative skew 51

Figure 4.8 Simulation results (a) presudo-NMOS (b) Dynamic loading 52

Figure 4.9 Location of voltage-controlled oscillator 53

Figure 4.10 Block diagram of ring oscillator 56

Figure 4.11 Schematic of delay cell 56

Figure 4.12 Location of the frequency divider 60

vii

Figure 4.13 Building block diagram of a frequency divider 62

Figure 4.14 Schematic of frequency divider 63

Figure 4.15 Transconductance of the NMOS transistor Mn4 65

Figure 4.16 Location of second divider & multi-modulus divider 67

Figure 4.17 Schematic of frequency divider 69

Figure 4.18 System block diagram of multi-modulus divider 70

Figure 4.19 Phase-selection principle in the multi-modulus divider 71

Figure 4.20 Block diagram of four-to-one multiplexer 73

Figure 4.21 Schematic of the two-to-one multiplexer 74

Figure 4.22 Schematic of true single phase circuit frequency divider 75

Figure 4.23 Block diagram of digital control circuit 76

Figure 4.24 Digital control block 77

Figure 4.25 Block diagram of sequential counter 78

Figure 4.26 Location of PFD, charge pump and LPF 79

Figure 4.27 Transient response of a charge pump phase locked lock 80

Figure 4.28 Schematic of phase frequency detector 82

Figure 4.29 Schematic of TSPC D-flip-flop 82

Figure 4.30 Schematic of charge pump 83

Figure 4.31 Schematic of charge pump 84

Figure 5.1 (a) Floor plan (b) die photo of the proposed synthesizer 89

Figure 5.2 Testing setup of ring oscillator 90

Figure 5.3 Frequency vs. tuning voltage 91

Figure 5.4 Buffered output power spectrum of the ring oscillator 92

Figure 5.5 Phase noise of the ring oscillator 93

Figure 5.6 Phase noise at different operating frequencies 93

Figure 5.7 Testing setup of frequency doubler 95

Figure 5.8 Output power spectrum of the frequency doubler 96

Figure 5.9 Phase noise of the frequency doubler 97

Figure 5.10 Phase noise of different input frequencies 98

Figure 5.11 Testing setup of frequency dividers & multi divider 99

Figure 5.12 Output waveform of full-speed frequency divider 100

viii

Figure 5.13 Output waveform of half-speed frequency divider 101

Figure 5.14 Output waveform of multi-modulus frequency divider 101

Figure 5.15 Testing setup of proposed frequency synthesizer 102

Figure 5.16 Measurement results of the spurs at 2.448GHz 103

Figure 5.17Phase noise of the closed-loop ring oscillator 104

Figure 5.18 Phase noise of the closed-loop frequency doubler 105

Figure 5.19 Measured settling time with frequency step 72MHz 106

Figure 5.20 Measurement result of IQ-mismatch 107

ix

List of TablesTable 3.1 Required specification of the synthesizer for Bluetooth 20

Table 3.2 Optimized loop filter parameters 37

Table 3.3 Noise contributions 38

Table 3.4 Design specification of the synthesizer for Bluetooth 40

Table 4.1 Design specifications of the frequency doubler 45

Table 4.2 Design specifications of the voltage-controlled oscillator 55

Table 4.3 Design specifications of the frequency divider 61

Table 4.4 Summary of different operation mode 63

Table 4.5 Design specifications of the half-speed frequency divider 68

Table 4.6 Design specifications of the multi-modulus frequency divider 68

Table 4.7 Design specifications of the multi-modulus frequency divider 80

Table 4.8 Design specifications and simulation results of the amplifier 84

Table 5.1 Measurements results of the ring oscillator 94

Table 5.2 Measurements results of the frequency doubler 98

Table 5.3 Measurements results of the frequency dividers 101

Table 5.4 Summary performance of frequency synthesizer 109

Table 5.5 Comparison of recent reported designs 111

A 1.8-V 2.4-GHz Monolithic CMOS Inductor-less Frequency Synthesizer for Bluetooth Application

Chapter1 - 1 -

Chapter 1

Introduction

1.1 Motivation

In recent years, the rapid development of wireless communication has

lead to an increasing demand of low-cost, low-power and high-performance

Integrated Circuits (ICs). Short Communication Network, Bluetooth or

Wireless Local Area Network (WLAN) have replaced the old cable

communication.

Bluetooth is an open-source standard for connecting devices without

wires via short-wave radio frequencies. As a short-wave standard, most

Bluetooth development is now concentrated on connecting devices within a

short distance. Bluetooth is aimed at allowing wireless connections between

all devices – in essence, mobile phone, printer, PC, PDA could all

communicate with each other. They are synchronized by way of the

Bluetooth chip that each would contain. This implies that anything with a

Bluetooth chip can join in, which also implies the potential for Bluetooth

technology is practically endless.


Chapter1 - 2 -

Unlike many other wireless standards, the Bluetooth wireless

specification includes both link layer and application layer definitions for

product developers which supports data, voice and content-centric

applications. Radios that comply with the Bluetooth wireless specification

operate in the unlicensed, 2.4-GHz radio spectrum ensuring communication

compatibility worldwide.

A simple Bluetooth receiver front-end is shown in Figure 1.1 including

a low-noise amplifier, mixer, frequency synthesizer and quadrature IF circuit.

One of the major building blocks is the frequency synthesizer. The purpose

of the synthesizer is to generate a reference frequency (LO) for the mixer to

down-convert the RF (radio frequency) signal to the IF (intermediate

frequency) of 1MHz for IF circuitry signal processing.

Figure 1.1 Block diagram of Bluetooth receiver front-end

In this research project, we are trying to demonstrate the possibility of

implementing a fully integrated monolithic frequency synthesizer in standard

CMOS process for Bluetooth applications. Standard CMOS technology is

FrequencySynthesizer

IFCircuit

LNA

RFsignal

I channel

Q channel

ILO

QLO


Chapter1 - 3 -

more attractive over other technologies because of the possibility to offer the

lowest cost solution. Unlike other building blocks in the receiver, the

frequency synthesizer itself is already a system including many building

blocks. It involves system design, low noise analog circuit design and high-

speed digital circuit design. They have been designed to solve the existing-

designs problems. Thus, the project is a very challenging.

1.2 Thesis Organization

An overview of the basic requirements of the frequency synthesizer in

a wireless communication system will be presented in chapter 2. Some

common topology of a frequency synthesizer will be reviewed such as the

phase-locked synthesizer. The system specifications of Bluetooth are

described at the beginning of chapter 3. Then the proposed architecture of

the frequency synthesizer will be presented. Whole-loop system issues, for

example loop bandwidth and phase noise consideration and trade-offs will

be discussed in chapter 3. After discussing the system requirements of the

synthesizer, a detailed description of different building blocks including the

frequency doubler, voltage controlled oscillator, frequency divider, multi-

modulus divider, phase frequency detector, charge pump, and loop filter on

circuit level will be discussed in chapter 4. The layout floor planning will be

presented in chapter 5. The measurement results of individual building

blocks and the whole synthesizer will be given in chapter 6. Chapter 7 will

conclude the thesis.


Chapter2 - 4 -

Chapter 2

Synthesizer Background

2.1 Introduction

In this chapter, some general considerations and technical challenges

of frequency synthesizer are discussed. Critical parameters of synthesizer

such as phase noise, switching time, chip area and voltage supply will be

presented. Also common synthesizer architectures, fractional-N design will

be discussed.


Chapter2 - 5 -

2.2 General Considerations

2.2.1 Phase Noise

Ideally, the synthesizer output spectrum should be a pure and stable

impulse. However, due to several noise influences in real circuit

implementation, the output spectrum is like skirt-shaped tone rather than a

sharp impulse [1]. It indicates that there is some signal power at frequencies

slightly offset from the desired oscillating frequency. The random fluctuation

of the output spectrum is defined as phase noise. In a practical oscillator, the

output is generally given by:

( ) ( ) tttAVout θω +⋅= 0sin (eq. 2.1)

where A(t) and θ(t) are the amplitude and phase with a random fluctuations.

As a result of the random fluctuations represented by A(t) and θ(t), the

output spectrum is shown in figure 2.1. Phase noise is quantified by

considering a unit bandwidth at an offset frequency ω from the carrier ω0,

then calculate the noise power in the band, and divide this result by the

carrier power. The quantity is expressed in the unit of dBc/Hz.

Figure 2.1 Phase noise in an oscillator output spectrum

ω

ω0f


Chapter2 - 6 -

To illustrate the importance of phase noise in a receiver [1], consider

the situation shown in figure 2.2. The noisy signal of the oscillator, shown in

figure 2.1, is used to down-convert a weak Radio Frequency (RF) signal with

a very strong unwanted signal. Both down-converted signals will consist of

two overlapping spectra. The wanted RF signal suffers from significant noise

due to the skirt of the unwanted signal. Therefore a low phase noise

oscillator or frequency synthesizer is significant in a wireless receiver to

maintain a high signal-to-noise ratio.

Figure 2.2 Effect of synthesizer phase noise in a receiver

ω0f

fRF signal

unwanted signal

fdown converted RF signal

unwanted convertedsignal


Chapter2 - 7 -

2.2.2 Settling Time

Switching time is defined as switching the output frequency of the

synthesizer from the first channel to the last channel. It is a very important

issue in the frequency hopping scheme and spread spectrum systems. The

Frequency hopping scheme defines how many hops per second is required

in the system. The frequency synthesizer is required to vary over the total

bandwidth of the system. A finite time is needed to establish a new stable

reference frequency. Basically, the settling time is usually one tenth of the

hopping time to ensure proper operation. Therefore, a fast switching

frequency synthesizer is desired to fulfill the system requirement. However,

in a conventional phase lock loop synthesizer, a large loop bandwidth is

desired in order to increase the switching time. On the other hand, a large

loop bandwidth will result in stability problem of synthesizer. It will cause

more noise from the other switching circuitry coupling to the output of

synthesizer and degrades the phase noise performance. Settling time,

stability and phase noise have to be optimized in order to fulfill the fast

frequency hopping specification.

2.2.3 Chip Area

Chip area is directly related to the cost of implementation. A smaller

chip area is desired. However, to fulfil the requirement of phase noise, a

small loop-bandwidth is needed to reduce the noise in the charge pump and

loop filter. A large capacitor is usually used to implement a small loop-


Chapter2 - 8 -

bandwidth. However, it occupies a large chip area. Also on-chip spiral

inductors are usually used to implement a LC resonance tank. The spiral

inductor is another device that occupies most of the chip area. To minimize

the chip area, smaller capacitance and minimization of number of on-chip

inductors are desired.


Chapter2 - 9 -

2.3 Fractional-N Architecture

Almost all synthesizers used in wireless communication systems are

the phase-locked loop (PLL) or indirect synthesizer [2]. A basic description of

factional-N architectures will be briefly described in this section.

A factional-N phase-locked loop (PLL) building blocks diagram is

shown in figure 2.3. A dual-modulus divider with a division ration M/M+1

(integer) divides the output frequency of voltage-controlled oscillator (VCO).

The divided frequency is compared with the reference frequency (fref) by the

Phase Frequency Detector (PFD). The loop filter low-pass filtered the output

signal, and this signal is the control input to the VCO. If the output frequency

decreases, the frequency and phase difference between fdiv and fref will be

larger and the phase frequency detector output will increase. This results

that the output frequency of the VCO will tune until the correct output

frequency is reached. This negative feedback mechanism ensures that the

output frequency of synthesizer is locked.

The fractional division is achieved by periodically changing the

division value of the dual-modulus divider. For example, the divider divides A

input pulses by M and B input pulses by M+1. The total division can be

written as eq. 2.2. Choosing the value A and B can change the resulting

fraction division value within M and M+1.


Chapter2 - 10 -

1+++=

MBMABA

DivisionTotal (eq. 2.2)

Since the output frequency of fractional-N synthesizers is a multiple of

a fraction of the reference frequency. The reference frequency is not

necessary to same as the channel spacing and these enables that the

reference frequency can be choose larger. Fractional-N synthesizer allows a

larger reference frequency, it results that the loop bandwidth of this

synthesizer can be larger compared to the case of the integer-N synthesizer.

The settling time is improved significantly and it makes the fractional-N

synthesizer suitable for a fast-frequency hopping system, like bluetooth

application.

Figure 2.3 Block diagram of fractional-N synthesizer

Although the design of this topology is very simple, the factional-N

synthesizer suffers from a lot of drawbacks. The main disadvantage of the

architecture is that the fractional-N synthesizer suffers a large fractional spur.

PhaseDetector

LoopFilter

FrequencyDivider

/M or /M+1

Fref Fout

Moduluscontrol


Chapter2 - 11 -

It is because the voltage-controlled oscillator output equals to the reference

frequency multiplied by fractional division ratio M+a (where a is the fractional

number). The output of the loop filter will ramp up or down with a period of

1/(afref). This unwanted signal will modulate the output of voltage-controlled

oscillator, creating spurs at afref, 2afref, etc. One of the approaches to

suppressing the fractional spurs is to randomize the choice of the modulus

(M) such that the average division factor is still given the desired value. A

sigma-delta modulator can be used for this purpose [4]. The fractional spurs

can be shaped such that most of the noise appearing at higher frequency

offsets. The low-pass filter suppresses the noise at higher offsets, so that the

noise is not appeared at the output of synthesizer.

The second disadvantage of the architecture is that the low frequency

noise generated by the loop components can modulate the VCO control

voltage and resulting in the noise appearing at the output spectrum of

synthesizer. If the loop bandwidth is too large, the noise from the loop

components suffers a smaller attenuation. It results that the total phase

noise will be degraded. Therefore, a tradeoff between the phase noise and

the loop bandwidth has to be considered.


Chapter2 - 12 -

References

[1] Behzad Razazvi, RF microelectronics, Prentice Hall, New Jersey, 1998

[2] J. Craninckx and M. Steyaert, Kluwer Academic Publishers,

Boston/Dordercht/London, 1998

[3] J. Craninckx and Michel S. J. Steyaert, “A Fully Integrated CMOS DCS-1800

Frequency Synthesizer,” IEEE JSSC, vol.33 no.12, pp.2054-2065, Dec. 1998

[4] T. A. D. Riley, M.A. Copeland and T. A. Kwasniewsky, “Sigma –Delta Modulation in

Fractional-N Frequency Synthesis,” IEEE JSSC, vol.28, pp.553-559, May. 1993


Chapter 3 - 13 -

Chapter 3

Synthesizer Design

3.1 Introduction

In this chapter, Bluetooth specifications related to the synthesizer

design are presented. Based on the requirements of the standard, a design

specification of some important parameters, such as phase noise, spurs and

settling time requirements are derived. A proposed architecture, based on a

fractional-N synthesizer, is proposed to meet the specifications. To analyze

the behavior of the synthesizer, a simple behavior model is considered. The

model is useful for the loop gain analysis. Some important parameters, for

example loop bandwidth, phase noise and settling time, of the design can be

extracted and optimized from the analysis to fulfil all the requirements of

Bluetooth. At the end of this chapter, the specifications of the frequency

synthesizer are summarized.


Chapter 3 - 14 -

3.2 Bluetooth System Specifications

Bluetooth wireless technology has revolutionized the personal

connectivity market by providing freedom from wired connections - enabling

links between mobile computers, mobile phones, portable handheld devices,

and connectivity to the Internet. Bluetooth technology redefines a new way

for connectivity. It is a short-range radio link intended to replace the cables

connecting portable and/or fixed electronic devices. Key features are

robustness, low complexity, low power, and low cost.

The Bluetooth system operates in the 2.4GHz ISM (Industrial

Scientific Medicine) band [1]. It employs GFSK (Gaussian Frequency Shift

Keying) Modulation. In a vast majority of countries around the world, the

range of this frequency band is 2400-2483.5 MHz. Bluetooth uses a spread

spectrum, frequency hopping, and full-duplex signal at up to 1600 hops/sec.

The signal hops among 79 frequencies at 1 MHz intervals to give a high

degree of interference immunity. The center frequencies of the channels

(fchannel) are

( ) MHzkf channel 12402 −+= (eq. 3.1)

where k = 1,2, … ,79


Chapter 3 - 15 -

The frequencies for lower guard band and upper guard band are

2MHz and 3.5MHz respectively. Some countries however have national

limitations in the frequency range. In order to comply with these national

limitations, special frequency hopping algorithms have been specified for

these countries. The frequency allocation is shown in figure 3.1.

Figure 3.1 Frequency allocation in Bluetooth specification

1MHz

79 channels

2400MHz 2402MHz 2480MHz 2483.5MHz

Lowerguardband

Upperguardband


Chapter 3 - 16 -

3.3 Design Specifications

For a Bluetooth receiver application, a frequency synthesizer can be

characterized by the phase noise, spurious tones and switching time. The

derivations of specifications are described in the following section.

3.3.1 Phase Noise Requirement

The minimum power of the desired RF signals can be as low as –

70dBm [1]. The adjacent-channel power at 500-kHz frequency offset is –

20dBc. Outside the receiver band, the power of out of band signal can be up

to 0dBm. If the LNA and RF filters provide enough attenuation of out of band

signals, the effect can be ignored.

To derive the phase noise specification, Signal-to-Noise Ratio (SNR)

is considered with the effect of phase noise. The SNR is found as follows:

( )( )

( )

( )

kHzHzdBcdL

xdBdL

fSNRSSdL

SNRfdLSS

SNRSS

chblockdesired

chblockdesired

noisephasedesired

500@/89

101log10920

log10

log10

6

−≤

−−−≤

−−−≤

≥++−

≥−

ω

ω

ω

ω

(eq. 3.2)


Chapter 3 - 17 -

where Sdesired is the power of desired signal, Sphase noise is the noise power,

Sblock is the power of blocking signal, fch is the channel bandwidth. Assuming

a required SNR after downconversion of 9dB, the calculated phase noise

requirement of frequency synthesizer is –89dBc/Hz@500kHz.

3.3.2 Spurious Tone Specification

The phase frequency detector and the charge pump in the

synthesizer operate at reference frequency (fref). Since the attenuation of the

loop filter is finite, a signal or noise from these building blocks at reference

frequency modulates the control voltage of the voltage-controlled oscillator,

and it appears at the upper side-band and lower side-band output spectrum

of the synthesizer as shown in figure 3.2. These two tones are defined as

spurs. Usually the magnitude of the spurs is inversely proportional to

reference frequency and measures the difference between the power of the

carrier and the spur.

Figure 3.2 Output spectrum of synthesizer

f0 f0 + freff0 - fref


Chapter 3 - 18 -

Blocking signals, which are located at fref away from the desired

signal, are down converted to the IF frequency. Usually the power of the

blocking signal can be very large and this down converted signal degrades

the SNR of desired signal significantly. The spurious tones have to be

minimized to preserve the SNR of the signal. The derivation of spurious tone

specification is similar in the case of the phase noise specification except the

channel bandwidth is not included.

( )

dBcS

dBcS

SNRSSS

SNRSSS

SNRSS

spur

spur

blockdesiredspur

spurblockdesired

noisephasedesired

49

93070

−≤

−+−≤

−−≤

≥+−

≥−

(eq. 3.3)

where Sspur is the power due to spurious tone. The blocking signal at fref is

as large as –30dBm. If a 9dB SNR is required, the maximum spurious tone

requirement of frequency synthesizer is –49dBc.

3.3.3 Settling Time

Bluetooth adopts a frequency hop scheme. A frequency hop

transceiver is applied to combat interference and fading. A shaped, binary


Chapter 3 - 19 -

FM modulation is applied to minimize transceiver complexity. The symbol

rate is 1 Ms/s. The nominal hop rate is 1600 hops/s.

A slotted channel as shown in figure 3.3 is applied with a nominal slot

length of 625 ìs. The slot numbering ranges from 0 to 227-1 and is cyclic with

a cycle length of 227. For full duplex transmission, a Time-Division Duplex

(TDD) scheme is used. On the channel, information is exchanged through

packets. Each packet is transmitted on a different hop frequency. The packet

nominally covers a single slot, but can be extended to cover up to five slots.

Figure 3.3 Bluetooth time slots assignment

The minimum settling time or switching time is limited by the time to

switch from the first channel to the last channel in frequency domain. In this

case, the settling time requirement of the frequency synthesizer is one-tenth

of the frequency hop time. The nominal hop rate is 1600 hops/s. This implies

that the settling time has to be smaller than 62.5µs (1600-1 x 10-1).

625µs

S1 S2 S3 S4 S5 S6

up to cyclic 227 slots


Chapter 3 - 20 -

All of the specifications are based on the design specification of the

frequency synthesizer for the Bluetooth application. Table 3.1 summaries the

requirements.

Table 3.1 Required specification of the frequency synthesizer for Bluetooth

Parameters Specification

Frequency Range 2400MHz- 2483.5MHzFrequency Resolution 1MHz

Phase Noise <-89dBc/Hz@500kHzSpurious Tone <-49dBcSettling Time <62.5µs


Chapter 3 - 21 -

3.4 Proposed Architecture

3.4.1 Architecture Description

A frequency synthesizer is one of the important building blocks to

generate a reference frequency for the wireless communication system.

Because of the greater demand for high-speed connectivity, the operating

frequency shifts to higher frequency band. This means that a higher

operating frequency of frequency synthesizer is desired, eg. 2.4GHz in the

Bluetooth system.

A conventional fractional-N synthesizer is usually adopted as shown

in figure 3.4. It includes a voltage-controlled oscillator, high-speed frequency

divider, phase frequency detector, charge pump and loop filter. The voltage-

controlled oscillator usually has to operate at few giga-hertz range

depending on the application and system of receiver. One way to implement

the oscillator at high operating frequency is to use an LC-oscillator. The

oscillating frequency is controlled by the value of inductor and capacitor in

resonance tank. In a monolithic design, the on-chip spiral inductor is

required to implement the resonance tank. However, it is very difficult to

design and fabricate the on-chip spiral inductor with a precise inductance

and high quality factor in standard CMOS process [2]. Even with a fair tuning

ability, any changing of the inductance and quality factor by process

variation will shift the operating frequency of the oscillator.


Chapter 3 - 22 -

Figure 3.4 Conventional frequency synthesizers

The ring oscillator is another type of voltage-controlled oscillator.

Because of its simplicity and ease of use in the CMOS integration (without

any on-chip spiral inductor), it is suitable for use in frequency synthesizers.

Although it is simpler to design, the oscillating frequency is usually very small

(GHz-range) depending on the process and supply voltage. One of the

topologies is to use a frequency doubler to double the output frequency of

the ring oscillator, so that the frequency synthesizer generates a higher

output frequency.

In this project, a 4th order type II, fractional-N inductor-less frequency

synthesizer with a frequency doubler shown in figure 3.5 is proposed. The

proposed synthesizer consists of a ring oscillator, frequency doubler, full

speed frequency divider, half speed frequency divider, multi-modulus divider,

phase frequency detector, charge pump and loop filter. The operating

principle is almost the same as the fractional-N synthesizer described in the

previous chapter.

PhaseDetector

Charge Pump& LPF

FrefFout

Frequency Divider

LC-oscillator

Fdiv


Chapter 3 - 23 -

Figure 3.5 Proposed frequency synthesizer architecture

The reference frequency (fref) is chosen to be 18MHz, this value is

large enough that is more than 10 times of the loop bandwidth (100kHz) for

stability consideration. Another reason is that the reference spurs from the

charge pump are not fall in the interested band, this value can relax the

spurious tone requirement of the synthesizer. When the frequency

synthesizer is locked, the output frequency of synthesizer (fsynthesizer) equals

to the reference frequency (fref) multiplied by the total division ratio (M can

choose to be 64-71), the resulting frequency is doubled after the frequency

doubler. The output frequency of synthesizer expressed as follows:

( )

MHz

toMHz

Mfff refoutrsynthesize

2556~2304

2716418

22

=

××=

××=×=

(eq. 3.4)

PhaseDetector

Charge Pump& LPF

fref (18MHz)fout

Full SpeedFrequencyDivider /2

Half SpeedFrequencyDivider /2

Multi-modulusFrequency Divider/16, 16.25 …17.75

FrequencyDoubler X2

Ring Oscillator

fdiv


Chapter 3 - 24 -

A significant advantage of this approach is to relax the operating

frequency of the voltage-controlled oscillator and frequency dividers by half.

Furthermore, the chip area and frequency-division ration is reduced and the

frequency tuning is doubled. Detailed advantages descriptions and designs

of the proposed architecture will be described in the next section.

3.4.2 Advantages of Proposed Architecture

3.4.2.1 Relax the Requirement of Ring Oscillator and Frequency Divider

Since a frequency doubler is used at the output of the ring oscillator,

the output frequency of the ring oscillator is just half of the desired operating

frequency of synthesizer. The output frequency of the ring oscillator is equal

to fsynthesizer/2 and ranges from 1200 to 1240MHz. In conventional design, the

full speed frequency divider has to operate as fast as the voltage-controlled

oscillator. Because of the lower speed requirement of the oscillator, the

operating frequency of this divider is also half. In addition, the speed

requirement of the half speed frequency divider and multi-modulus divider is

also relaxed.

The operating frequency of oscillator and dividers are proportional to

the voltage supply and power consumption. Since the operating frequency of

these building blocks is halved, the voltage supply and the power

consumption of these building blocks are reduced significantly. The total

power consumption of the whole synthesizer can be minimized. In the

research project, the voltage supply is targeted at 1.8V and the technology


Chapter 3 - 25 -

process will be the standard 0.35µm CMOS process for better digital and

analog circuit compatibility. The power consumption is less than 60mW and

is kept as low as possible.

3.4.2.2 Smaller Chip Area and Faster Settling Time

In a monolithic design, the on-chip spiral inductor is required to

implement the resonance tank. If a quadrature LC-oscillator is used, a total

of 4 on-chip spirals inductors are required. The four on-chip inductors usually

occupy most of the chip area. However, in the proposed design, a ring

oscillator is used instead of an LC-oscillator. Thus, there is no longer a need

for any on-chip spiral inductor. This saves a lot of chip area.

Also the phase noise requirement of the Bluetooth application is relax,

it is just –89dBc/Hz@500kHz. The loop bandwidth can be increased to allow

a smaller roll-off of phase noise from the charge pump and loop filter. Also

these can minimize the value of the on-chip capacitor used when

implementing the loop filter. As in the proposed architecture, there is no on-

chip spiral inductor. Thus, the chip area is limited to less than 1mm2. Another

advantage to increase the loop bandwidth is that the settling time is faster to

fulfil the fast switching time specification of the fast frequency hopping

system in the Bluetooth application.


Chapter 3 - 26 -

3.4.2.3 Larger Frequency Tuning Range

A large parasitic capacitance associated with transistors limits the

frequency tuning, making the voltage-controlled oscillator or synthesizer

unsuitable for manufacturing due to the process variation. Fortunately, a ring

oscillator can achieve a wide tuning ability to guard against the process

tolerance. In the proposed specification, the ring oscillator is able to operate

within a range of 400MHz. If it co-operates with frequency doubler, the

tuning range can be more than 800MHz. The tuning should be large enough

to compensate the process variation.

3.4.3 Disadvantages of Proposed Architecture

Although the proposed architecture has a lot of advantages, there is

some drawbacks that degrades the performance of the synthesizer. Adding

a frequency doubler after the output of the loop will degrade the phase noise

performance of the synthesizer. Theoretically, the phase noise of the

frequency doubler degrades 6dB comparing to that of the ring oscillator.

However, in practical situation, the measured phase noise is even worse. It

is because the frequency doubler itself contributes some noise to the output

of the synthesizer. Therefore, a larger phase noise margin is required at the

design stage to ensure that the phase noise of the synthesizer can meet

specifications.


Chapter 3 - 27 -

3.5 Synthesizer Behavior Model

3.5.1 Behavior Model Description

A behavior linear model for the proposed frequency synthesizer is

shown in figure 3.6. These models are useful for analysis and study of the

open loop of the synthesizer. The behavior model usually uses the phase of

the signals to represent the state variables. The phases of each nodes are

represented by voltage. Since the frequency doubler is not inside the loop of

the synthesizer, the doubler is not included in this model.

Figure 3.6 Block diagram of the proposed architecture

The phase frequency detector is a block with a gain of 1/2π. The

resulting phase error controls the current Icp of the charge pump. A loop filter

with a low-pass transfer function H(s) sends out a DC control-value to the

voltage-controlled oscillator. The oscillator is represented by a gain of KVCO

with a pole at zero frequency. The output of the oscillator then is divided by

divider N times and fed back to the phase frequency detector. If the loop

breaks at the point after the divider, the open-loop transfer function A(s) is

expressed as follows:

1/2π

PFD

Icp H(s) KVCO/s

1/N

Vref

Vdiv


Chapter 3 - 28 -

( ) )(2

121

)( sHsN

KI

NSK

sHIsA vcocpvcocp ⋅

⋅⋅⋅

=⋅⋅⋅⋅=ππ

(eq. 3.5)

3.5.2 Loop Filter Implementation

The choice of transfer function H(s) in eq. 3.5 is very important. It

determines the loop bandwidth of the frequency synthesizer and this is

directly related to the performance of the whole synthesizer, for example

phase noise, spurious tone performance and settling time. In the proposed

architecture, a 4th order type II PLL synthesizer is implemented. The 4th

order should be large enough to reduce the output phase noise of the

charge pump and filter.

In order to minimize the chip area and enhance the synthesizer

performance, a dual-path filter with dual charge pump is used to implement

the loop filter [3][4]. A schematic of the dual-path filter with dual charge pump

is shown in figure 3.7. Since the output voltage swing of the amplifier is rail-

to-rail, it provides a large enough tuning voltage to control the frequency of

the ring oscillator.


Chapter 3 - 29 -

Figure 3.7 Dual-path loop filter with dual charge pump

The aim of the amplifier is to combine two signal paths (Vz and Vb), so

that a low-pass transfer function can be obtained at the output node of the

filter (Vout). The corresponding equation is expressed as eq. 3.6. The

expression gives a 3rd order low pass function H(s). The multiplication factor

B can be controlled to be large enough, so that a low frequency of zero can

be realized without a large value of resistor (Rp) or capacitor (Cz). This

method can reduce the phase noise coming from the resistor. At the same

time, it can minimize the chip area by using a smaller value of capacitor.

4

4

4

4

1)1()1(1

)(

1)1()1(

τττ

τττ

sR

ss

sCsH

sR

ss

sC

I

VVV

p

z

z

p

z

z

cp

pzout

+⋅

++⋅=

+⋅

++

⋅=

+=

(eq. 3.6)

where τz = BRpCz, τp = RpCp, τ4 = R4C4

C4

+

_ Vopamp

Cz

C2

Rp Cp

Vref

R4

Icp

BxIcp

Vout

Vz

-Vp


Chapter 3 - 30 -

3.5.3 Open Loop Gain Analysis and Noise

Combining the results of section 3.4.1 and 3.4.2, an open loop

transfer function for the frequency synthesizer can be obtained in eq. 3.7.

The cross-over frequency or loop bandwidth (ωc) can be calculated by

setting the loop transfer function to unity. The expression is shown in eq. 3.8.

A Bode plot of the open loop transfer function is illustrated in figure 3.8.

4

42 1)1(

)1(2

)(ττ

τπ s

Rss

CsN

KIsA

p

z

z

vcocp

+⋅

++⋅

⋅⋅⋅

= (eq. 3.7)

N

RBKI pvcocpc ⋅

⋅⋅⋅=

πω

2(eq. 3.8)

Figure 3.8 A Blot plot of open loop gain

ωp

ωz ωc

-40dB/decade

-20dB/decade

-60dB/decade

A(s)

ω


Chapter 3 - 31 -

As expressed in eq. 3.8, the loop bandwidth is controlled by many

parameters and all of these parameters can be designed. The first

parameter resistor Rp can be found by eq. 3.9 by setting the loop bandwidth

(ωc), the gain of voltage-controlled oscillator (Kvco), charge pump current (Icp),

division ration (N) and multiplication factor (B) as desired.

BKIN

Rvcocp

cp ⋅⋅

⋅⋅=

ωπ2(eq. 3.9)

The zero ωz is designed at a factor α below the loop bandwidth. As a

result, the capacitor Cz can be solved.

cpz

c

zpzz

RBC

CRB

ωα

αω

τω

⋅⋅=

=⋅⋅

== 11

(eq. 3.10)

The two high frequency poles τp and τ4 are set to coincide, so this

achieves the best noise suppression outside the loop bandwidth. The poles

ωp and ω4 are designed at a factor β beyond the loop bandwidth. As a result,

the capacitor Cp can be solved. The resistor R4 is expressed as a factor γ

smaller than resistor Rp, and C4 is equal to γ times Cp. The corresponding

equations are listed below:


Chapter 3 - 32 -

p

p

cpp

cp

p

CC

RR

RC

⋅=

=

⋅⋅=

⋅==

γ

γ

ωβ

ωβτ

ω

4

4

1

1

(eq. 3.11)

3.5.4 Noise

The phase noise of voltage-controlled oscillator is not the only noise

source in a PLL frequency synthesizer. The phase noises coming from the

charge pump and loop filter also degrade the phase noise performance of

the whole synthesizer. This phase noise contribution of the charge pump,

resistors Rp, R4 and amplifier are summarized as follow [5]:

HzvI

KL

IBKNkT

L

IBKNkT

L

BVVI

NkTL

OPAMPnoisec

ccp

vcoA

c

ccp

vcoR

c

ccp

vcoRp

c

tgscp

cpcp

2

4

2

2

42

4

64

62

2

2

)()(

4)(

4)(

1)(

2)4()(

⋅

∆⋅

⋅⋅=∆

∆⋅

⋅⋅⋅⋅⋅⋅⋅=∆

∆⋅

⋅⋅⋅⋅⋅⋅

=∆

∆⋅

+⋅

−⋅⋅⋅⋅⋅

=∆

ωω

ωβω

ωω

ωγβπω

ωω

ωβπ

ω

ωωβ

ααβπ

ω

(eq. 3.12)


Chapter 3 - 33 -

3.5.5 Loop optimization and Stability

The loop bandwidth can be chosen to determine the phase noise,

settling time, spurious tone performance and stability. The goal of the

optimization is to minimize the chip area and fulfil all mentioned

specifications. The minimum value of the loop bandwidth is usually bounded

by the settling time requirement. The first order of equation to describe the

settling time (Tsettling) is defined in eq. 3.13. Figure 3.9 shows the settling

time with a different loop bandwidth. If the specified accuracy (a) is 10-6 and

the settling time is 60µs, the desired loop bandwidth is at least 40kHz. As the

synthesizer is a 4th order system, generally exhibiting slower settling to

higher precision. For this reason, the required loop bandwidth has to be

larger than 40kHz. Thus an accurate simulation is required to verify the

settling time.

csettling

aT

ωln−= (eq. 3.13)

where a is the specified accuracy.


Chapter 3 - 34 -

Figure 3.9 Minimum loop bandwidth

The chip area and the total phase noise of the synthesizer also relate

to the loop bandwidth. If the loop bandwidth increases, the required on-chip

capacitor decreases and thus the chip area is reduced. However, the noise

coming from the charge pump and loop filter will be increased significantly.

Therefore, an optimization of the loop bandwidth is performed using Matlab

tool. Setting the current pass through the charge pump (Icp) to 1µA, will lead

to the smallest capacitor value according to eq. 3.11. At the same time, in

order to maintain the phase margin of the open loop analysis high enough,

so that the system is stable, factors α and β are designed to be 4 and 6

respectively. The gain of the voltage-controlled oscillator (Kvco) equals at

most 450MHz/V from the simulation of the ring oscillator and the division

ratio is 67. The other parameters, the charge pump ratio (B) and the fourth

Minimumpoint


Chapter 3 - 35 -

pole ratio (γ), are designed to be 36 and 3 to ensure that phase noise and

chip area are minimized.

The loop bandwidth is first found by minimizing the total capacitor

used. From the figure 3.10, a plot of total capacitors used to implement the

loop filter against the loop bandwidth is shown. In order to minimize the chip

area, the optimum loop bandwidths should be within 100kHz to 140kHz.

Figure 3.10 Optimum loop bandwidth

After the range of bandwidth is found, the exact bandwidth has to be

determined. Using eq. 3.12, the phase noise with different loop bandwidths

can be calculated. The designed loop bandwidth is 100kHz. The unit gain

bandwidth requirement of the Opamp is at least larger than the designed


Chapter 3 - 36 -

loop bandwidth (100kHz) with a voltage gain of 60dB. An ideal amplifier with

a gain of 60dB and unit gain bandwidth of 10MHz is used in the behaviour

model.

Table 3.2 summarizes the optimized loop parameters. Figure 3.11

shows the phase noise contributions of all building blocks at different offset

frequency, the corresponding phase noise contributions at 500kHz offset

frequency are listed in table 3.3. Assume the phase noise of ring oscillator is

–108dBc/Hz at 500kHz offset. The total phase noise of the frequency

synthesizer without the frequency doubler will be –101.6dBc/Hz at 500kHz

offset. This phase noise will degrade by around 7dB after the frequency

doubler [6]. Thus, the total phase noise will be –94.6dBc/Hz at 500kHz offset

which is 5.6dB better than the requirement of the Bluetooth standard. This

value will further degrade by using the full-speed frequency divider, however,

a 5.6dB margin should be large enough to meet the specifications. The total

capacitance used to implement the loop filter is around 250pF, which is very

small but fulfils all requirements.


Chapter 3 - 37 -

Table 3.2 Optimized loop filter parameters


Reference Frequency (fref) 18MHzLoop Bandwidth (ωc) 100kHz

Charge Pump Current (Icp) 1µAZero Frequency (α) 4Pole Frequency (β) 6

Filter Current Ratio (B) 36Fourth Pole Ratio (γ) 3

Capacitor (Cz) 38.8pFCapacitor (Cp) 58.2pFCapacitor (C4) 174.8pFTotal Capacitor 271.8pF

Resistor (Rp) 3.8kΩResistor (R4) 1.2kΩ

Figure 3.11 Phase noise contribution at different offset frequencies

Overall

R1

Opamp

ChargePump

VCO

R4


Chapter 3 - 38 -

Table 3.3 Noise contributions

Noise Source Phase Noise at 500kHz Offset

Charge Pump Current (Icp) -135.4 dBc/HzResistor (Rp) -105.3 dBc/HzResistor (R4) -111.6 dBc/Hz

Opamp -107.9 dBc/HzRing Oscillator -108.0 dBc/Hz

Total without doubler -101.6 dBc/HzTotal with doubler -94.6 dBc/Hz

Figure 3.12 shows the simulated open loop gain. The loop bandwidth

of the synthesizer is located at 100kHz. It is high enough to avoid slow

settling. The phase margin of the open loop is 57o. This margin should be

large enough to ensure the loop stability. The behaviour model is also

simulated by HP’s ADS to estimate the settling time of the synthesizer. The

simulated settling time shown in figure 3.13 is around 45µs.


Chapter 3 - 39 -

Figure 3.12 Simulated open loop transfer function

Figure 3.13 Simulated settling time

LoopBW=100kHz

Phasemargin=57o


Chapter 3 - 40 -

3.6 Summary of Proposed Specification

The specifications in table 3.4 of the proposed architecture have been

designed for the Bluetooth application. The voltage supply and power

consumption have been designed to operate at 1.8V and less than 70mW

for low power operation. Also the settling time is fast enough to fulfil the

requirements of frequency hopping rates. Chip area is minimized to reduce

the cost of implementation.

Table 3.4 Design specification of the frequency synthesizer for Bluetooth


Voltage Supply 1.8VFrequency Range 2400MHz- 2483.5MHz

Frequency Resolution 1MHzLoop Bandwidth 100kHz

Phase Noise <-89dBc/Hz@500kHzSpurious Tone <-49dBcSettling Time <62.5µs

Power Consumption <70mWChip Area <1mm2

Process TSMC 0.35µm CMOS


Chapter 3 - 41 -

References

[1] Bluetooth specification v1.1

[2] N.T. Tchamov and P. Jarske, “1.2V Gigahertz-Resonance-Ring ICO/VCO,” IEEE

Electronics Letters, vol.33, pp. 541-542, Mar. 1997.

[3] D. Mijuskovic and M. J. Bayer, T. F. Chomics, N. K. Garg, F. James, P. W.

McEntarfer, and J. A. Porter, “Cell Based Fully Integrated CMOS Frequency

Synthesizer,” IEEE JSSC, vol.29, no. 3, pp. 271-279, Mar. 1994.

[4] J. Craninckx and M. Steyaert, “A fully Inegrated CMOS DCS-1800 Frequency

Synthesizer,” IEEE JSSC, vol.33, no. 12, Dec. 1998.

[5] J. Craninckx and M. Steyaert, “Wireless CMOS Frequency Synthesizer,” Kluwer

Academic Publishers, Boston/Dordrecht/London, 1998

[6] Joseph M. C. Wong and H. C. Luong, "A 1.5-V 4-GHz Dynamic-Loading

Regenerative Frequency Doubler in a 0.35-µm CMOS Process," RFIC Symposium,

June 2002.


Chapter 4 - 42 -

Chapter 4

Circuit Implementation

4.1 Introduction

The specification of whole synthesizer has been designed and

extracted to meet the requirements of the Bluetooth standard in last chapter.

In this chapter, design specifications and circuit-level implementations of the

monolithic inductor-less frequency synthesizer is discussed. It includes the

analysis and design of the frequency doubler, voltage-controlled oscillator,

high-speed frequency divider, multi-modulus divider, phase frequency

divider, charge pump and loop filter.


Chapter 4 - 43 -

4.2 Frequency Doubler

4.2.1 Introduction & Design Specifications

Frequency doublers are connected with the output of the voltage-

controlled oscillator as shown in figure 4.1. This is used to double the

frequency of voltage-controlled oscillator to achieve the desired output

frequency while effectively reducing the operating frequency of the voltage-

controlled oscillator and the high-speed frequency divider by half.

Figure 4.1 Location of frequency doubler

Two existing approaches are used to implement a frequency

doubling circuit. The first approach uses an analog multiplier or up-

conversion mixer with the two input terminals connected together as shown

in figure 4.2 [1]. The main problem of the topologies is that the output swing

is typically limited to only around several tens of milli-volts which is not large

enough to drive the next stages, eg. mixer. In addition, such a design

PhaseDetector

Charge Pump& LPF

Fref Fout




FrequencyDoubler X2

VCO

Fdiv


Chapter 4 - 44 -

requires a passive component such as inductor or resistor and thus occupies

a large chip area.

Figure 4.2 Analog mixer as a frequency doubler

The second approach uses the regenerative frequency doubling

technique with essentially a two-stage ring oscillator [2]. Each of the

amplifier stages is a simple emitter coupled differential pair with resistive

loads. Although such a frequency doubler can operate at a high frequency,

the resistive loading inevitably limits the operating bandwidth, which is

defined as the difference between the maximum and the minimum operating

frequencies. To achieve a desired frequency of few GHz, such a frequency

doubler has so far only been implemented in advanced BJT processes or

other special process [3].

This section presents a new dynamic-loading technique to implement

a CMOS frequency doubler [4] with a high operating frequency, a large

bandwidth, a high output swing and a low phase noise. Table 4.1 concludes

the design specifications of the frequency doubler.

Input Signal with

frequency f

Output Signal with

frequency 2f


Chapter 4 - 45 -

Table 4.1 Design specifications of the frequency doubler


Voltage Supply 1.8VMaximum Output Operating Frequency >2.4GHz

Output Bandwidth as large as possibleOutput Signal Strength >200mVpp

Power Consumption <5mW

4.2.2 Circuit Implementation

The original idea of frequency doubler is derived from a LC oscillator,

the schematic is shown in figure 4.3. It includes an LC tank, a pair of

negative transconductance with a biasing transistor. The node X is the

injection-mode node which means that the oscillating frequency at this node

is twice the oscillating frequency of the LC Oscillator. By using this principle,

the frequency doubling circuit can be implemented.

In order to implement a frequency doubler, one simple way is to

replace the LC tank of the LC-oscillator by a pair of PMOS dynamic loadings.

However, the output of the doubler is just single-ended which is a problem.

Considering the single-ended output of the synthesizer connects to a single-

ended nonlinear-mixer, the even-order harmonics of the down-converted

signal can not be cancelled. Therefore, a fully differential frequency doubler

is proposed.


Chapter 4 - 46 -

Figure 4.3 Schematic of LC Oscillator

A block diagram of the proposed dynamic-loading regenerative

frequency doubler is shown in figure 4.4. It is essentially a cross-coupled

two-stage amplifier. The architecture is configured as a 2-stages ring-

oscillator. The corresponding detailed schematic diagram is shown in figure

4.5.

Figure 4.4 Block diagram of the proposed frequency doubler

clk0 clk90

clk180 clk270+_ fout = 2fin

Mn1 Mn2

Mn3

Out0 Out180

bias

Node X(fout)

Inductor


Chapter 4 - 47 -

Figure 4.5 Schematic diagram of the proposed frequency doubler

Each of the amplifier stages is a simple differential pair with PMOS

dynamic loading (Mp1, Mp2). The dynamic-loading technique enables a

larger bandwidth compared to the resistive loading. Since the RC time

constant at the output nodes of the differential amplifiers is changing

dynamically, it offers a large bandwidth at that output node. Furthermore, the

absolute value of the resistive load cannot be controlled very well in CMOS

technology, which would affect the operating frequency of the doubler. This

problem does not exist or at least is minimized when PMOS dynamic loading

is being used.

Mp1 Mp2

Mn1 Mn2

Mn3

Mn4 Mn5

Mn6 Mn11

clk0 clk90clk180 clk270

bias

fout + fout -

Mp3 Mp4

Mn7 Mn8

Mn9 Mn10

0o 180o 270o 90o


Chapter 4 - 48 -

In our proposed design shown in figure 4.5, the cross-coupled pairs

(Mn1, Mn2), (Mn7, Mn8) provide a positive feedback to achieve large voltage

swings at the output nodes of the differential amplifier. When one of the

differential outputs goes high, the positive feedback mechanism helps to

push the other differential output low. Both differential amplifiers are sharing

the same biasing transistor (Mn3). This technique can help to improve the

amplitude and phase matching at the output nodes of the amplifiers [5]. As

discussed later, a smaller phase error results in a purer output tone.

Two differential pairs (Mn4, Mn5), (Mn9, Mn10) are used to maintain

quadrature phase of the output nodes of the amplifiers. A biasing transistor

(Mn6), which is operated at saturation region, is connected to one differential

pair. The function of this transistor is to form an injection-mode node at its

drain with an output frequency doubling the input frequency.

The frequency doubling mechanism relies on the injection-mode

technique. In order to learn more about the injection-mode technique, a

simple circuit shown in figure 4.6a, is used to analysis the mechanism of the

injection-mode technique. The outputs (fout and fout’) are taken from the

drain of the biasing NMOS transistors (Mn1, Mn1’) respectively, and the

frequency of the outputs is exactly the same as the input clk signal in this

case. Because of the nonlinearity of the (Mn2, Mn2’), the output signals (fout

and fout’) are distorted and out-of phase. If the biasing NMOS transistor is


Chapter 4 - 49 -

shared as shown in figure 4.6b, the both output signals (fout and fout’) are

mixed together, so that the frequency of resulting signal is doubled.

Figure 4.6 Idea of injection-mode technique (a) no sharing (b) with sharing biasing transistor

In the proposed design, a large swing occurs at the output nodes of

the differential amplifiers. Because the biasing transistor is biased at the

saturation region, the double-frequency signal is maximized. The outputs of

the frequency doubler are exactly out of phase since the (Mn4, Mn5) and

(Mn9, Mn10) are cross-coupled to each other. The drain of Mn6 is the

clk180

Mn2

Mn1

clk0

bias

(fout)

Mn2’

Mn1’ bias

(fout’)

clk180

Mn1bias

(fout)

clk0

Mn2 Mn2’

clk0

fout

clk0

fout

fout’


Chapter 4 - 50 -

injection-mode node which the frequency of the signal at that node doubles

the input frequency.

Effectively, the idea of the frequency doubling can be thought of as

two signals being mixed together by Mn6 as shown in eq. 4.1.

22sin2

90sinsintaotata

ωωω

−=

+⋅ (eq. 4.1)

where a is the amplitude of the amplifier’s output. From eq. 4.1, the double-

frequency output signal amplitude is equal to a2/2. Consequently, in order to

maximize the output swing of the doubler, the output swing of the differential

amplifiers needs to be maximized.

In the conventional dynamic-loading technique, the input clocks of the

gate (Mp1, Mn4) are complementary (phase difference is ð). However, the

phase difference is ð/2 for the proposed frequency doubler. The idea is

known as negative skewing [6]. The simplified conceptual diagram is shown

in figure 4.7. The clock input turns on Mp1 before low-to-high output

transitions and turns off the PMOS before high-to-low output transitions. It

speeds up the transitions and offers a larger swing at the output nodes of the

differential amplifiers, which in turn results in a larger output signal of the

frequency doubler.


Chapter 4 - 51 -

Figure 4.7 The idea of negative skew

In order to prove that dynamic loading leads to larger amplitude at the

outputs of the amplifiers and at the output of the doubler, a simulation is

carried out. Two different configurations of inverters, one of which is a

presudo-NMOS inverter and the second dynamic loading inverter, as shown

in figure 4.8 are considered. A 2-GHz signal clock is applied as the inputs to

both inverters. These two inverters are designed to consume the same

power for a fair comparison. The corresponding outputs are simulated by

Hspice and plotted in the same figure. A larger output swing is achieved for

the inverter using the dynamic loading technique as shown in curve (b). This

simple simulation implies that the dynamic loading technique can speed up

the transitions and results in larger amplitude of the amplifier’s output. By

in90

in

out

ô

in out

in90

Mp1

Mn4


Chapter 4 - 52 -

using this technique, the output swing of the doubler can increase

significantly.

Figure 4.8 Simulation results (a) presudo-NMOS (b) Dynamic loading techniques

(a)

(b)

bias

clk90

clk0

(b)

bias

clk

(a)


Chapter 4 - 53 -

4.3 Voltage-Controlled Oscillator


As wireless communication systems move towards high-data-rate

applications, high frequency and low-phase-noise oscillator are important

building blocks in the frequency synthesizer design. Figure 4.9 shows the

location of the voltage-controlled oscillator in the synthesizer. The important

parameters of the oscillator are the phase noise, voltage supply, power

consumption and tuning range.

Figure 4.9 Location of voltage-controlled oscillator

In recent years, LC-tank oscillators [7] have demonstrated a good

phase-noise performance with low power consumption. However, the tuning

range of LC-oscillator (around 5% ~ 10%) is relative low when compared to

ring oscillators (>40%). The output frequency may be shifted out of the

desired range in the presence of process variation. Moreover, the phase

noise and power consumption of the LC-tank oscillators highly depends on

PhaseDetector

Charge Pump& LPF

Fref Fout




FrequencyDoubler X2

VCO

Fdiv


Chapter 4 - 54 -

the quality factor of on-chip spiral inductors. In most digital standard CMOS

processes, it is difficult to obtain a high quality factor for the inductor. Some

reported inductor designs [8] can achieve a high quality factor in standard

CMOS processes, however it requires post-processing steps which

inevitably increase the cost. Also, the on-chip spiral inductor usually

occupies a large chip area, which is undesirable for cost and yield

considerations.

The ring oscillator is another type of voltage-controlled oscillator. Due

to its simplicity and its ease in CMOS integration, it is usually used in a lot of

phase-locked loop frequency synthesizers and clock recovery designs

[9][10]. Ring oscillators normally occupy less chip area, which improves both

the cost and the yield. It generates quadrature-phase outputs if even

numbers of delay cells are used. However, the phase noise performance is

poorer when compared with LC-oscillators. In this section, the design of a

monolithic voltage-controlled ring oscillator will be presented. The oscillator

using a negative delay path with normal delay path achieves a high

operating frequency, wide tuning range, low power consumption and

improved phase-noise performance. Table 4.2 summaries the design

specifications of the voltage-controlled oscillator.


Chapter 4 - 55 -

Table 4.2 Design specifications of the voltage-controlled oscillator


Voltage Supply 1.8VCenter Frequency 1.2GHz

Maximum Output Operating Frequency >1.3GHzTuning Range >30%

Gain 450MHz/VPhase Noise <-105dBc/Hz@500kHz



The voltage-controlled oscillator is a four-stage ring oscillator. A block

diagram of the ring oscillator and schematic of the delay cell are shown in

figure 4.10 and 4.11 respectively. From the block diagram, four delay cells

are cascaded together with a normal delay path (solid line) and negative

skew path (dotted line). All delay cells are configured as a differential

structure to minimize the effect of power supply injected phase noise. Each

delay cell consists of a pair of NMOS input transistors (Mn1, Mn4), a pair of

PMOS positive feedback transistors (Mp2, Mp3) to maintain oscillation, a pair

of dynamic PMOS loading transistors (Mp1, Mp4) to speed up the transition

from high-to-low or low-to-high and a pair of tuning NMOS transistors (Mn2,

Mn3) in series with a capacitor to tune the RC time constant of the delay cell.


Chapter 4 - 56 -

Figure 4.10 Block diagram of ring oscillator

Figure 4.11 Schematic of delay cell

In order to achieve a high operating frequency, the ring oscillator

employed a dynamic loading technique with negative skew [11]. The clock

input turns on Mp1 before low-to-high output (out) transitions and turns off

the PMOS before high-to-low output (out) transitions. It speeds up the

Mp1 Mp2 Mp3 Mp4

Mn1 Mn2 Mn3 Mn4

Vin2- Vin2+

Vin1- Vin1+

C1 C1

(1pF) (1pF)

Vcont

out+ out-

out+

out-

Vin2+

Vin1+

Vin1-

Vin2-

out+

out-

Vin2+

Vin1+

Vin1-

Vin2-

out+

out-

Vin2+

Vin1+

Vin1-

Vin2-

out+

out-

Vin2+

Vin1+

Vin1-

Vin2-


Chapter 4 - 57 -

transitions and offers a higher maximum achievable oscillating frequency

since the dynamic loading with negative skew technique compensates for

the poor speed performance of PMOS transistor in standard CMOS

technology. By using the technique, the oscillating frequency of ring

oscillator can almost double compared with the conventional design (without

dynamic loading with negative skew) [11]. Another way to maximize the

oscillating frequency is that the transconductance to drain capacitance ratio

(gm/CT) of the NMOS input pair (Mn1, Mn4) is maximized to achieve a high

operating frequency with low power dissipation. One method is to increase

the transconductance of the (Mn1, Mn4) to speed up the oscillating frequency,

but the drawback is that it consumes a lot of power. The other method is to

use donut transistors to minimize the capacitance of output node, so that the

operating frequency will be higher.

The wide frequency tuning range of an oscillator is important to

compensate the frequency-shift problem because of the process variation.

The wide frequency tuning range depends on the delay of each delay cell.

Basically, the oscillating frequency can be tuned by changing the load

impedance or output RC time constant. In this design, pair of tuning NMOS

transistors (Mn2, Mn3) in series with a capacitor (C1~1pF) is used to tune

the RC time constant of the delay cells. When the control voltage (Vcont) is

smaller, the tune-on resistance of the transistor (Mn2, Mn3) is larger. It turns

out that the delay is shorter and the oscillating frequency is faster. On the

other hand, if the control voltage is large, the tune-on resistance of the


Chapter 4 - 58 -

transistor (Mn2, Mn3) is small. The delay will be larger and it results in the

operating frequency being smaller. Because of the large variation of

resistance under a wide range biasing voltage (0.6V-1.8V), the ring oscillator

can achieve a large tuning capability. In addition, the tuning transistors do

not consume any DC power. Thus, this tuning mechanism can maintain

constant power consumption and constant output signal magnitude.

Phase noise of an oscillator is a very important issue. It affects the

whole receiver performance. As discussed before, the phase noise can be

improved by increasing the carrier power [12]. Since the output of the

oscillator is full swing, the carrier power is already maximized. In this case,

the full swing output signal switches the transistors on or off periodically. The

current noises from transistors become zero when the transistors turn off

periodically. The phase noise performance is improved.

The phase noise analysis of ring oscillator is simplified and a single-

side band phase noise of a differential four-stage ring oscillator is equated

as follow [12].

( )

3

2rms

2

pL

noise22

2rms

N9

VC

i

f16N2fL

≈Γ

⋅⋅

πΓ

⋅=

(eq. 4.2a)


Chapter 4 - 59 -

pLr

0

dd

VCN2I

Nt21

f

VINP

⋅⋅≈≈

⋅⋅= (eq. 4.2b)

noise

2

dd

2

0

2i

PVN

ff

29

fL ⋅

⋅

⋅

⋅

π= (eq. 4.2c)

where N is the number of identical stages, Γrms is root-mean square (RMS)

of impulse-stimulus function (ISF), f is frequency offset from the carrier, inoise

is the total current noise on each node and is given by the power sum of

individual sources, CL and Vp is the total output capacitance and peak output

amplitude, f0 is the oscillating frequency of the ring oscillator, P is the total

power consumption and I is the current pass through each delay cell. If eq.

4.2b substitutes into eq. 4.2a, the phase noise of the ring oscillator can be

modelled by eq. 4.2c. If the number of stages (N) increases, the phase noise

is worse for the same power dissipation and frequency oscillation. Using the

eq. 4.2a, the phase noise is about –107dBc/Hz at 500kHz offset from the

carrier.


Chapter 4 - 60 -

4.4 High Speed Frequency Divider


The first full-speed frequency divider (also called prescaler) connects

to the output of the voltage-controlled oscillator as shown in figure 4.12. It

divides the frequency of the ring oscillator by half. The first frequency divider

drives the second half-speed frequency divider. It divides by a fixed ratio

(/2), and can therefore operate at a higher frequency because it does not

have to allow for the delays involved in counting or resetting. The main

purpose of the divider is to lower the frequency to a range that can be

applied to a multi-modulus divider with small steps.

Figure 4.12 Location of the frequency divider

Conventional high-speed frequency dividers are mainly based on

injection-locked topology [13] or source-coupled logic design (SCL) [14][15].

Injection locked dividers can operate up to more than 10GHz at low supply

voltages. However, this kind of topology usually employs an on-chip spiral

PhaseDetector

Charge Pump& LPF

Fref Fout




FrequencyDoubler X2

VCO

Fdiv


Chapter 4 - 61 -

inductor which occupies a large chip area. Also the operating frequency

range is usually very small (~5%-10%).

Source-coupled logic design is another way to implement a fully

differential frequency divider. This section presents a dynamic-loading

technique to implement a source-coupled logic and a fully differential

frequency divider [16] with a high operating frequency, a large frequency

range and a high output swing. Also a solid theoretical analysis is developed

to predict the operating frequency of the frequency divider. Table 4.3

summaries the design specifications of the frequency divider.

Table 4.3 Design specifications of the frequency divider


Voltage Supply 1.8VTopology SCL

Maximum Input Operating Frequency >1.3GHzOperating Frequency Range 1GHz-1.3GHz

Output Signal Strength >1.5Vpp



Two D-flip-flops connecting in a Master/Slave configuration can

function as a fully differential frequency divider as shown in figure 4.13. Each

D-flip-flop is triggered by a CLK and CLKBAR signal from the voltage-

controlled oscillator. The D-flip-flop always operates at two modes


Chapter 4 - 62 -

periodically. When the input CLK signal is low, one of the D-flip-flops is

under sensing mode. The D-flip-flop senses the D input and flips it to the Q

output. On the other hand, when the input CLK signal is high, the D-flip-flop

is under latching mode. It latches and holds the output’s state. This

mechanism enables the output frequency to be half of the input.

Figure 4.13 Building block diagram of a frequency divider

Figure 4.14 shows a fully differential frequency divider with dynamic

loading in schematic level [16][17]. It consists of two identical D-flip-flops

cross-coupled with each other. A NMOS pair (Mn4, Mn5) is used to sense the

input in the sensing mode. A NMOS cross-coupled pair (Mn1, Mn2)

configures as a positive feedback to latch the output in the latching mode. A

pair of PMOS transistors (Mp1, Mp2) is used to realize the dynamic loading

[17]. In the sensing mode, the PMOS loading transistors are operated in the

linear region, the turn-on resistance is very small, thus it provides a small RC

time constant to the output node. It helps the NMOS pair (Mn4, Mn5) sense

the D inputs in a higher speed, so that it can speed up the transition from

D Q

DFF

Db Qb

D Q

DFF

Db Qb

CLKCLKBAR


Chapter 4 - 63 -

low-to-high or from high-to-low. While in the latching mode, however, the

PMOS loading transistors are turned off and this contributes to a large RC

output time constant. The NMOS cross-coupled pair (Mn1, Mn2) holds the

output’s state of D-flip-flop. Such a mechanism ensures that the output

frequency is half of the input frequency and it greatly increases the

maximum operating frequency and the frequency range of the divider.

Figure 4.14 Schematic of frequency divider

Table 4.4 Summary of different operation mode

CLK signal Operation mode PMOS loading RC time constant

High Latching OFF LargeLow Sensing ON Small

Mp1 Mp2 Mp3 Mp4

Mn1 Mn2 Mn7 Mn8

Mn3 Mn9clkbar clk

clkbar clk

Mn4 Mn5 Mn10 Mn11


Chapter 4 - 64 -

To derive the operating frequency of the frequency divider with

dynamic loading, a theoretical analysis is performed [17]. Basically, the

speed of this type frequency divider heavily depends on how fast the

sensing operation is. Thus, it assumes that the D-flip-flop is under sensing

mode and the analysis is based on the half circuit of this D-flip-flop. The

transfer function of the model is equated and setting the voltage gain to

unity, the resulting equation is shown as follows:

( )

411

2

1124

max,2

dndndpL

L

Lout

gggG

C

Ggmpgmngmnf

++=

++−−=

π(eq. 4.3)

where gm is transconductance, gd is channel conductance and CL is total

parasitic capacitance at the output node. At the maximum output operating

frequency fout,max, negative transconductance gmn1 is chosen to compensate

the load GL. Then the maximum achievable output operating frequency of

the divider can be simplified and given in eq. 4.4.

Kgmn

gmn

Cgmn

fL

out

max44

4max,

2

=

=π

(eq. 4.4)


Chapter 4 - 65 -

In practical situations, the input clock signals (CLK and CLKBAR) are

most likely a distorted sinusoidal waveform. The transconductance of Mn4

(gmn4) is not constant in the sensing mode as illustrated in figure 4.15.

Therefore, we can assume the average transconductance equals the

maximum gmn4max divided by a correction factor K. Since the

transconductance gmn4 is like a triangular waveform, the correction factor

can be approximated to be 2. The average value gmn4 is equal to gmn4max/2.

The resulting maximum input operating frequency (twice the maximum

output operating frequency) equals to eq. 4.5. As the PMOS loading is

operated in linear region when in sensing mode, the transconductance

gmn4max can be found as eq. 4.6.

L

in

C

gmnf

π2max4

max, = (eq. 4.5)

gsddb

tclkdda

tgs

bbaox

tgs

ds

VVV

PMOSVVVV

NMOSVV

VVVLWC

NMOSVV

PMOSIgmn

−=−+=

−−⋅⋅

=−

=

)(

)(

)2(2

)(

)(2 2

max4

µ

(eq. 4.6)

Figure 4.15 Transconductance of the NMOS transistor Mn4

gmn4Sensingmode

Latchingmode

gmn4max

gmn4


Chapter 4 - 66 -

From eq. 4.5, the operating frequency of the divider can be improved

by increasing gmn4max, which can be achieved either by increasing the

transistor’s aspect ratio (W/L) or the bias current by increasing the gate-to-

source voltage bias (Vgs). However, increasing W/L would also increase the

output capacitance loading that would degrade the speed. On the other

hand, increasing the gate-to-source voltage to increase the bias current

would require higher supply voltage. As a result, there would be a trade-off

between the maximum operating frequency, the supply voltage and the

power consumption.

Another way to speed up the frequency divider is to minimize the

loading capacitance CL. Therefore donut transistors are used to implement

the frequency divider. By keeping all the transistors’s ratios constant and

shrinking the process from, say 0.35-µm to 0.18-µm CMOS process, the

loading capacitance can be reduced half and the transconductance can be

increased two times. Consequently, the maximum operating frequency can

be increased by more than four times. Another interesting point is that, since

the gm4max is a function of the input signal strength. A larger input signal will

result in a larger gm4max, it turns out that the frequency divider can achieve a

higher operating frequency.


Chapter 4 - 67 -

4.5 Half-Speed Divider & Multi-Modulus Divider


A second half-speed frequency divider divides the output of the first

divider by half. It then connects to a multi-modulus divider to divide the input

frequency by one of the modulus according to the control input. Figure 4.16

shows the location of the second divider and the multi-modulus divider. The

half speed divider co-operates with the multi-modulus divider to provide a

division ratio from 32 to 35.5 with a step 0.5. There are three bits to control

total eight-modulus division ratio.

Figure 4.16 Location of the second frequency divider & multi-modulus divider

In the previous section, a high-speed frequency divider was

presented. Basically, the design of the second frequency divider is almost

the same as the full speed one. The circuit architecture is still based on a

Master/Slave D-flip-flop [18]. The output signal drives the multi-modulus

divider for further processing. Because the requirement of half-speed

PhaseDetector

Charge Pump& LPF

Fref Fout




FrequencyDoubler X2

VCO

Fdiv


Chapter 4 - 68 -

frequency divider is not the same as full speed frequency divider, another

topology of D-flip-flop is adopted. Also a modified phase-selection multi-

modulus frequency divider will be presented in this section. The operation of

this kind frequency divider is based on the 90-degrees phase relationship

between the outputs of the half-speed frequency divider. Since the divider

consists of a lot sub-building blocks, a detailed description and analysis of

operation will be discussed in the following section. Tables 4.5 and 4.6

summarize the specifications of the two frequency dividers.

Table 4.5 Design specifications of the half-speed frequency divider


Voltage Supply 1.8VTopology SCL

Maximum Input Operating Frequency >0.7GHzOperating Frequency Range 0.4GHz-0.7GHz

Output Signal Strength >1.5Vpp


Table 4.6 Design specifications of the multi-modulus frequency divider


Voltage Supply 1.8VTopology Phase selection

Maximum Input Operating Frequency >0.35GHzOperating Frequency Range 0.1GHz-0.35GHz



Chapter 4 - 69 -


4.5.2.1 Half-Speed Frequency Divider

The operating principle of a fully differential half-speed frequency

divider is the same as the full-speed frequency divider. The half-speed

divider still employs a two D-flip-flops connected in a Master/Slave

configuration. Because of the slower speed requirement, the design of the

D-flip-flop is different. The schematic diagram of the design is shown in

figure 4.17.

Figure 4.17 Schematic of frequency divider

The main difference is that triode region PMOS transistors are used to

implement loading. As the input frequency is lower, the transistors can be

Mp1 Mp2 Mp3 Mp4

Mn1 Mn2 Mn6 Mn7

Mn3 Mn8

bias bias

Mn4 Mn5 Mn9 Mn10

clk clkbar


Chapter 4 - 70 -

made smaller, thus decreasing the power consumption. This flip-flop delivers

a rail-to-rail output signal so that the divided signal can directly connect to

standard logic without any amplification.

4.5.2.2 Multi-modulus Frequency Divider

Most phase-locked synthesizers incorporate high-speed multi-

modulus dividers [19]. Such circuits divide the input frequency by one of the

modulus according to control input. The division ratio can be 16, 16.25 … …

17.75 for the fractional-N synthesizer. The input frequency is around

300MHz and the output frequency is 18MHz when the loop is locked. As

shown in figure 4.18, the multi-modulus divider consists of a phase selecting

circuit, a chain of full-swing frequency dividers and digital-control logic.

Figure 4.18 System block diagram of multi-modulus divider

Quadraturephase outputsfrom second

divider

0o

90o

out180o

270o

/2 /2 /2 /2

Digital Control2-bit control

3-bit control

FdivPhase-Selection

/8 /16 /32 /64


Chapter 4 - 71 -

The phase-selection multi-modulus operates as follows. A quadrate-

phase output from the half-speed frequency divider is fed to the phase-

selection circuit. The basic idea is simply illustrated in figure 4.19. If the

phase-selection function is disabled by the 2-bit control signals, the phase-

selection circuit picks one of the quadrate-phase outputs and connects to the

chain of full-swing frequency divider. The resulting output frequency is a

factor of 16 slower than the input frequency. On the other hand, if the 3-bit

control signal of digital control circuit is enabled, the phase-selection circuit

selects the quadrate-phase output periodically (from 0o -> 90o -> 180o ->

270o -> 0o) within a certain period (16 periods in the design). Since the 0o

signal lags the 90o signal by 90o, the output of the phase-selection circuit will

be delayed due to this operation. The time shifting of output signal at one

fourth of the input frequency corresponds to swallow one pulse of the input

signal with a period T/4. Thus, the total average output period of the whole

multi-modulus divider is increased with this delay. It equals to 16T + T/4.

Figure 4.19 Phase-selection principle in the multi-modulus divider

T/4

00

900

ctrl

out


Chapter 4 - 72 -

A different modulus-division ratio can be achieved if the phase-

selection circuit is switched more than once per period. The output signal

frequency of the whole divider will divide by 16 + N/4, with N being the

number of switchings in a period. In the design, the phase switching occurs

up to eight times in a period. The value of N can be from zero to seven.

Theoretically, the signal connected to the chain of full-swing

frequency dividers could be switched once per cycle, accomplishing 16

different modulus. However, increasing the number of modulus will result in

increasing the complexity and the speed of the digital-control logic circuit.

Therefore, a larger power consumption is required to speed-up the operation

of control logic.

Phase Selection Circuit

The phase-selection circuit can be implemented using various

methods. A switchable amplifier is one method [19]. However, this amplifier

has trouble generating a large-amplitude output at high frequency. Another

simple way to implement the switching operation is using a four-to-one

multiplexer [20]. The multiplexer consists of three two-to-one multiplexers as

in figure 4.20. It is controlled by the two control outputs (C0, C1) of the digital

control circuit and the output is connected to a chain of frequency dividers.

The implemented two-to-one multiplexer is a transmission gate structure with

output digital buffers as shown in figure 4.21. The design is so simple that it

operates correctly at 500MHz input frequency.


Chapter 4 - 73 -

The design of the two-to-one multiplexer shown in figure 4.22 has a

strong effect on the correct operation of the whole multi-modulus divider.

Ideally, the input signals have a 50% duty cycle. If the duty cycle is less than

50% due to the process variation, it will cause some spikes in the output.

The division ratio will be incorrect at the output of whole modulus divider. In

order to avoid the problem, a larger than 50% duty cycle input signal was

designed after the input buffer. It ensures that there is no spike at the output

of the phase-selection circuit and it maintains a high-speed operation.

Figure 4.20 Block diagram of four-to-one multiplexer

2-to-1Multiplexer

2-to-1Multiplexer

2-to-1Multiplexer

0o

90o

180o

270o

C0 C0bar

C0 C0bar

C1 C1bar

out


Chapter 4 - 74 -

Figure 4.21 Schematic of the two-to-one multiplexer

Full Swing Frequency Divider

Other than the source-coupled logic (SCL) (described in section 4.4),

true single phase logic (TSPC) is another technique used to implement a

frequency divider [21][22]. A full swing TSPC frequency divider is shown in

figure 4.22. The circuit can be separated into three parts. The first part is a

clock-input enabled sensing stage. It includes Mp1, Mn1a and Mn1b. When the

clock (clk) signal is high, the first stage will copy the complementary result of

the present output (fout) to the input of the second stage. The second part is

the latch stage to store the output of the first stage when the clk signal is

high. The final stage is an inverter (buffer) to connect to the other full swing

frequency divider. The output of the D-flip-flop feeds back directly to the D-

input to obtain a divide by 2 function.

C0

C0bar

C0

in out


Chapter 4 - 75 -

Figure 4.22 Schematic of true single phase circuit (TSPC) frequency divider

The operation is divided into two phases. The first phase is pre-

charge phase when the clock signal (clk) is high. The node n1 is pre-

charged to a state opposite to the node n3, and node n2 is pre-charged to

be zero. Since Mp3 and Mn3 are turned off, node 3 remains the output state.

In the evaluation phase, the clock signal is low. If node n1 is pre-charged to

be high, node n2 is discharged. Transistors Mp3 and Mn3 are turned on and

off respectively, the node n3 is pulled up to high. On the other hand, if the

node n1 is pre-charged to be low, the node n2 is charged up. The transistor

Mn3 is discharged and pulls down the node n3.

This design is much simpler when compared to the SCL design. And

there is no static power consumption as there is no direct path from the

out

clk

Mp1 Mp2 Mp3 Mp4

Mn1a

Mn1b Mn2 Mn3 Mn4

Sensingstage

Latchingstage

Bufferstage

n1

n2n3

clk

clk


Chapter 4 - 76 -

voltage supply to the ground when the divider is operating. Also, the

maximum speed requirement is only 400MHz, so the divider can be

designed to consume smaller dynamic power. Furthermore, the output of this

kind frequency divider is rail-to-rail and this makes it easier to connect to

other digital logic circuits without any amplification of output signals.

Digital Control Logic

Digital control logic is a modulus control block as shown in figure 4.23.

The control block receives the divided signals (/8, /16, /32 and /64) from the

chain of frequency dividers and another 3-bit modulus control signal (mode1,

mode2 and mode4) is used to control the division rate of the whole multi-

modulus divider. The resulting digital output signal (next) acts as a clock

signal of a shift register. Whenever a clock pulse triggers the register, the 2-

bit control output signals (C0 and C1) counts once. This control signal

switches the quadrate-phase inputs of the phase selection circuit.

Figure 4.23 Block diagram of digital control circuit

Combinational Logic Shift Register

mode1

mode2

mode4

/8 /16 /32 /64

nextC0

C1


Chapter 4 - 77 -

The function of the combinational logic circuit is to deliver a number N

pulses on its output (next), where N is the number of switchings in every 16

periods. A circuit diagram shown in figure 4.24 is used to implement the

purpose. A high level, at mode 1,2 and 4 control bits, enables the

corresponding NOR gate to output a number of pulses 1,2 and 4 in every 16

periods respectively. All these pulses are combined by another NOR gate.

Figure 4.24 Digital control block

Shift Register

The shift register receives the output (next) of the digital control block

and sends out two control signals (C0, C1) to switch the phase of the phase-

selection circuit. Four D latches, as shown in figure 4.25, cascade together

Nor

Nor

/8bar

/16/32

/64bar

mode1

/8bar

/16/32bar

mode2

Nor/8bar

/16bar

mode4

Nor

N1

N2 next

N4


Chapter 4 - 78 -

to form a sequential counter to perform the function. The counter starts

counting from 00, 01, 11, 10 and then loops back.

Figure 4.25 Block diagram of sequential counter

D Q

Dbar Qbar

D Q

Dbar Qbar

D Q

Dbar Qbar

D Q

Dbar Qbar

next nextbar next nextbar


Chapter 4 - 79 -

4.6 Phase Frequency Detector & Charge Pump


Frequency synthesizer is a 4th order type II charge pump phase

locked loop. It includes a phase frequency detector and charge pump co-

operating with a loop filter to control the frequency of voltage-controlled

oscillator. Figure 4.26 shows the location of these building blocks.

Figure 4.26 Location of phase frequency detector, charge pump and LPF

The basic operating principle is as follow and illustrated in figure 4.27.

Phase frequency detector has two inputs signal (reference frequency fref and

divided VCO frequency fdiv) and two outputs signal (up and down). The

frequency or phase differences between the fref and fdiv causes the phase

frequency detector generating up or down control signals. These signals

open or close the two current sources of the charge pump. An up (down)

signal activates the upper (lower) current source generating a positive

(negative) output current. This output current is low-pass filtered to produce

PhaseDetector

Charge Pump& LPF

Fref Fout




FrequencyDoubler X2

VCO

Fdiv


Chapter 4 - 80 -

a DC voltage (vcont) that sustains the VCO operation at desired frequency.

Table 4.7 summarizes the specifications of the building blocks.

Table 4.7 Design specifications of the building blocks


Voltage Supply 1.8VTopology Type 2charge pump PLL

Filter order 3th orderMaximum Input Operating Frequency

(PFD)up to 30MHz

Reference frequency (fref) 18MHz

Figure 4.27 Transient response of a charge pump phase locked lock

PFDfref

fdiv

up

down

Vcont

LPF

fref

fdiv

up

down

vcont


Chapter 4 - 81 -


4.6.2.1 Phase Frequency Detector

The implementation of the phase frequency detector is shown in

figure 4.28. The phase frequency detector is included two TSPC D-flip-flop

and nor gate. As illustrated in Figure 4.27, the reference frequency (fref) has

a falling edge first, an up signal is generated by D-flip-flop to raise the control

voltage of the voltage-controlled oscillator. As a result, the oscillating

frequency will be smaller. After a certain time, the falling edge of the divided

VCO output (fdiv) stops and resets the phase frequency detector. It then pulls

down the up signal and stop the increment of the control voltage. If the

reference frequency is smaller than the divided VCO output frequency, the

up signal will generate continuously and its pulse width will increase

gradually. This topology can detect both the phase and frequency

differences. Also the nor gate provides a short delay, such that both up and

down signals are turned on simultaneously. Such a mechanism can

eliminate the dead zone problem. The TSPC D-flip-flop is implemented as

shown in figure 4.29 [23].


Chapter 4 - 82 -

Figure 4.28 Schematic of phase frequency detector

Figure 4.29 Schematic of TSPC D-flip-flop

4.6.2.2 Charge Pump

Since a dual path loop filter topology is employed, two charge pumps

with different biasing currents are considered. Ideally, a charge pump is a

two current sources that are switched on and off. A simple current steering

charge pump is shown in figure 4.30. All switches have to be operated at

clk QTSPC

D-flip-flopD reset

D resetTSPC

D-flip-flopclk Q

Nor

up

down

vdd

fref

fdiv

Q

clk

clk

reset


Chapter 4 - 83 -

saturation region, such that the output impedance is large enough. Since a

biasing current of the smaller charge pumps is 1µA that is not easy to be

biased accurately, a current mirror is designed 10 times larger than the

biasing current in these charge pump.

Figure 4.30 Schematic of charge pump

4.6.2.3 Loop Filter

The active filter described in the figure 3.7 is used to implement the

loop filter. The passive components and designed parameters are

summarized in table 3.2. A two-stage Opamp shown in figure 4.31 with 65dB

voltage-gain and 30-MHz unity gain bandwidth is used for the filter. In order

to minimize the noise of the amplifier, the transconductance of the amplifier

should be large to suppress the thermal noise. The drawback is that the

power consumption is large. Also, the width and length of the transistors size

are maximized to minimize the flicker noise. In this case the noise should be

up

downbar

upbar

down

vref


Chapter 4 - 84 -

dominated by the thermal noise. The simulated equivalent input voltage

thermal noise of the amplifier is 4.6x10-17. Using the equation in section

3.5.4, this noise will translate to the phase noise of the synthesizer with –

107.4dBc/Hz at 500kHz offset. Table 4.8 summarizes the requirements and

simulation results of the amplifier.

Figure 4.31 Schematic of two-stage amplifier

Table 4.8 Design specifications of amplifier and simulation results

Parameters Specification Simulation

Voltage Supply 1.8V 1.8VGain 60dB 65dB

Unity Gain Bandwidth 10MHz 30MHzPhase Noise @ 500kHz <108dBc/Hz 107.9dBc/Hz

Power 0.36mW 0.36mW

Ibias

in+ in-Vdd

Cc

out


Chapter 4 - 85 -

References

[1] Y. K. Seng, S. S. Rofail, “Design and analysis of a ±1V CMOS four-quadrant

analogue multiplier,” IEE Proc-Circuits Devices Syn, vol. 145, No. 3, June 1998

[2] J. Maligcorgos and J. R. Long, “A 2-V 5.1-5.8-GHz image-reject receiver with wide

dynamic range,” ISSCC 2000, pp.322-323.

[3] S. Hackl, J. Boeck, G. Ritzberger, M.Wurzer and H. Knapp, “45GHz SiGe Active

Frequency Multiplier,” ISSCC 2002, pp.62-63.

[4] Joseph M. C. Wong and H. C. Luong, "A 1.5-V 4-GHz Dynamic-Loading

Regenerative Frequency Doubler in a 0.35-µm CMOS Process," RFIC Symposium,

June 2002.

[5] C. W. Lo and H. C. Luong, "2-V 900-MHz Quadrature Coupled LC Oscillator with

Improved Amplitude and Phase Matchings," ISCAS, June 1999.

[6] S. Lee, B. Kim and K. Lee, “A novel high-speed ring oscillators for multiphase clock

generation using negative skewed delay scheme,” JSSCC, 1997, pp.289-291

[7] J. Craninckx and M. Steyaert, “A 1.8-GHz Low-Phase-Noise CMOS VCO using

Optimized Hollow Spiral Inductors,” IEEE JSSC vol. 32, pp.736-744, May 1997.

[8] Shao-Fu Chu; Chew, K.W.; Loh, W.B.; Wang, Y.M.; Onn, B.G.; Ju, Y.; Zhang, J.;

Shao, K., “High quality factor silicon-integrated spiral inductors achieved by using

thick top metal with different passivation schemes,” VLSI symposium, June 2001

[9] B. Razavi and J. Sung, “A 6-GHz 60-mW BiCMOS Phase Locked Loop with 2-V

Supply,” IEEE ISSCC Digest of Technical Papers, pp.114-115, Feb. 1994.

[10] A. Pottbacker and U. Langmann, “An 8-GHz Silicon Bipolar Clock Recovery and

Data Regenerator IC,” IEEE JSSC Circuits, vol. 29, pp.1572-1578, Dec. 1994.

[11] Seog-jin Lee, Beomsup Kim and Kwyro Lee, “A Novel High-Speed Ring Oscillator

for Multipase Clock Generation Using Negative Skewed Delay Scheme,” IEEE

JSSC, pp.289-291, Feb. 1997.

[12] A. Hajimiri, S. Limotyrakis, T. H. Lee, “Phase noise in multi-gigahertz CMOS Ring

Oscillator,” Proceedings of the IEEE 1998 CICC, pp. 49-52, 1998.


Chapter 4 - 86 -

[13] H. R. Rategh, et al., “A CMOS Frequency Synthesizer with an Injection-Locked

Frequency Divdier for a 5-GHz Wireless LAN Receiver,” IEEE J. Solid-State Circuit,

vol.35, pp. 780-787, May 2000.

[14] R. Chen, “High-Speed CMOS Frequency Divider,” Electronic Letter, vol. 33, no. 22,

pp.1864-1865, Oct. 1997.

[15] B. Razavi , et al., ”Design of High-Speed, Low-Power Frequency Dividers and

Phase-Locked Loops in Deep Sub-micron CMOS,” IEEE JSSC, vol. 30, pp.101-108,

Feb. 1995.

[16] H. Wang, “A 1.8-V 3-mW 16.8-GHz Frequency Divider in 0.25µm CMOS,” IEEE

ISSCC Digest of Tech. Papers, pp.196-197, Feb 2000.

[17] Joseph M. C. Wong, Vincent S. L. Cheung and Howard C. Luong, “A 1-V 2.5-mW

5.2-GHz Frequency Divider in a 0.35µm CMOS Process,” IEEE VLSI Symposium,

Oct. 2000

[18] B. Razavi, et al., ”Design of High-Speed, Low-Power Frequency Dividers and

Phase-Locked Loops in Deep Sub-micron CMOS,” IEEE JSSC, vol. 30, pp.101-108,

Feb. 1995

[19] J. Craninckx and Michel S. J. Steyaert, “A Fully Integrated CMOS DCS-1800

Frequency Synthesizer,” IEEE JSSC, vol.33 no.12, pp.2054-2065, Dec. 1998

[20] Ahola, R., Halonen, K., “A 4-GHz CMOS multiple modulus prescaler,” IEEE

International Conference, vol. 2, pp.323-326, 1998

[21] B. Chang, J. Park and W. Kim., “A 1.2-GHz CMOS dual-modulus prescaler using

new dynamic D-type flip flop,” IEEE JSSC, vol. 31, pp.749-752, May 1996

[22] J. Craninckx and M. Steyaert, “A 1.75-GHz/3-V dual-modulus divide-by-128/129

prescaler in 0.7-µm CMOS,” IEEE JSSC, vol. 31, pp.890-897, July 1996

[23] H. Yoshizawa, K. Taniguchi, K. nakashi, “An Implementation Technique of Dynamic

CMOS Circuit Applicable to Asynchronous/Synchronous Logic,” IEEE ISCAS, vol. 2,

pp.145-148, June 1998


Chapter 5 - 87 -

Chapter 5

Experimental Results

5.1 Chip Fabrication

The proposed frequency synthesizer is fabricated by using the TSMC

0.35-µm double-poly, and four metal layers CMOS process without using a

silicide block. The process is suitable for 3.3-volt or lower-supply applications

where PiP (poly2 over poly) capacitors (850 aF/µm²) are available.

Figure 5.1a is the floor plan of the proposed frequency synthesizer.

The placement of the building blocks follows the block diagram of the whole

synthesizer. Some high frequency building blocks are placed as close as

possible to minimize the routings. In order to test the chip conveniently, all

bonding pads are put on the top and bottom sides of the chip. The probing

pads (including signal-ground-signal probing pads and high-impedance

probing pads) are arranged on the right side of the chip. The voltage

supplies of different building blocks are separated, so that different parts can

be measured individually if necessary.


Chapter 5 - 88 -

As the presence of extra input probing pads for the dividers increase

the capacitance loading of the voltage-controlled oscillator, these would slow

down the operating frequency of the oscillator. On-chip output buffers for

voltage-controlled oscillator can be used before connecting to input probing

pads for the divider. However, the loss of the on-chip buffer usually is quite

large, and the reduced signal is not large enough to drive the frequency

divider. Thus, testing structures including frequency divider and multi-

modulus divider are tested separately. Moreover, the substrate coupling

from the frequency divider and the ring oscillator are minimized by putting a

guard ring around them. Figure 5.1b shows the die photo of the testing chip

and its core-chip area is 870 x 800/µm².


Chapter 5 - 89 -

Figure 5.1 (a) Floor plan and (b) die photo of the proposed synthesizer

TestingStructure

Low-PassFilter

VCO

Multi-ModulusDivider

FrequencyDoubler

CP

PFDFrequency

Divider

TestingStructure

Low-Pass Filter

VCOMulti-

ModulusDivider

FrequencyDoubler

CP

PFDFrequency

Divider


Chapter 5 - 90 -

5.2 Ring Oscillator

The testing setup of the ring oscillator for phase noise and tuning

range measurements is shown in figure 5.2. The setup consists of a

HP8510E spectrum analyzer, a pair of on-chip NMOS open-drain buffers, a

pair of bias-Ts and a power combiner. The bias-T acts as a 50Ω load for the

on-chip buffer and extracts the RF output signals. The power combiner

combines the differential RF signal into a single-ended signal. This

combined signal is measured by the spectrum analyzer.

Figure 5.2 Testing setup of ring oscillator

The ring oscillator is measured at 1.8V and it consumes 21.4mW

including the power consumption of the on-chip buffer. A frequency-tuning

plot of the oscillator is shown in figure 5.3. The maximum oscillating

frequency is 1.3GHz. The operating frequency is smaller than the expected

DC biasingRF

RF&DC

RF

RF&DC

Combiner

RingOscillator

Single-endedsignal

HP8510ESpectrum AnalyzerOn-chip

buffer

On-chipbuffer


Chapter 5 - 91 -

value, this is due to the underestimation of the parasitic capacitance at the

output node. The operating frequency range of the ring oscillator is between

824MHz and 1.3GHz with tuning voltage from 1V to 1.8V, and that is around

42% with respect to the center frequency. As discussed in section 4.3.2, this

large frequency tuning range is important to compensate the process

variation. The gain of the ring oscillator is almost 550MHz/V within the linear

region (from 1V to 1.8V).

Figure 5.3 Frequency vs. tuning voltage

The buffered output power spectrum of the ring oscillator operating at

1.239GHz is shown in figure 5.4. Since the oscillator is not locked by the

phase-locked loop, the output spectrum is fluctuating. The spectrum is not a

stable and pure tone. The single-ended output power is 10dBm, which is

almost 1.4Vpp.


Chapter 5 - 92 -

Figure 5.4 Buffered output power spectrum of the ring oscillator with RBW=10kHz

The phase noise of the ring oscillator is measured by the direct-

phase-noise-measurement method [1] and shown in figure 5.5. The

measured phase noise is –105dBc/Hz at 500kHz frequency offset. This is

worse compared to the theoretical estimation of –110dBc/Hz and simulation

result of –108dBc/Hz value at the same frequency offset. Since the

measured output power of the oscillator has dropped, the phase noise is

degraded. However it still meets the specification of the oscillator. Figure 5.6

shows the phase noise of oscillator operating at different operating

frequencies. The phase noise is quite constant over the entire range of

operation, The variation is less than 2dB throughout the whole operating

frequency range. Table 5.1 summaries the measurement results of the ring

oscillator.


Chapter 5 - 93 -

Figure 5.5 Phase noise of the ring oscillator

Figure 5.6 Phase noise at different operating frequencies

-105dBc/Hz


Chapter 5 - 94 -

Table 5.1 Measurements results of the ring oscillator

Parameters Specification Measurement

Voltage Supply 1.8V 1.8VDesired Frequency 1.2GHz 1.2GHz

Maximum Output Operating Frequency >1.3GHz 1.27GHzMinimum Output Operating Frequency 1.1GHz 0.8GHz

Tuning Range >17% 42%Gain 450MHz/V 550MHz/V

Phase Noise at 500kHz offset <-105dBc -105dBcPower Consumption <30mW 21.4mW


Chapter 5 - 95 -

5.3 Frequency Doubler

The testing setup of the frequency doubler for phase noise and tuning

range measurements is shown in figure 5.7. The setup is the same as the

testing setup of ring oscillator, it consists of a HP8510E spectrum analyzer, a

high-impedance probe and a low-noise amplifier (LNA). The signal drop of

the high-impedance probe is large, thus a low-noise amplifier is required to

amplify the signals. Since there is no extra-pad for the input signals of the

frequency doubler, the frequency of the ring oscillator is tuned and its signals

are directly fed to the frequency doubler.

Figure 5.7 Testing setup of frequency doubler

The frequency doubler is measured at 1.8V and it consumes 3.6mW

including the power consumption of the on-chip buffer. As the input signal is

FrequencyDoubler

Single-endedsignal

HP8510ESpectrum Analyzer

RingOscillator

inputsignal

Iout+

Iout-

High-Zprobe

LNA


Chapter 5 - 96 -

taken from the ring oscillator, the tuning range of the oscillator (from 0.8GHz

to 1.3GHz) limits the measurable operating range of the doubler. The

maximum operating frequency of the doubler is 2.6GHz and the measured

frequency range is between 1.6GHz to 2.6GHz, which is exactly twice the

oscillating frequency of the ring oscillator. This large frequency tuning range

is significance to guard against the process tolerance.

The output power spectrum of the frequency doubler operating at

2.4615GHz is shown in figure 5.8. Since the ring oscillator is not locked by

the phase-locked loop, the output signal of oscillator (input signal of doubler)

is fluctuating and the output spectrum of the doubler is not stable. The

single-ended output power is 0dBm, which is almost 0.2Vpp. This value

should be large enough to drive the next stage, for example the mixer.

Figure 5.8 Output power spectrum of the frequency doubler with RBW=10kHz


Chapter 5 - 97 -

The phase noise of the frequency doubler is measured by the direct-

phase-noise-measurement method [1] and shown in figure 5.9. The

measured phase noise of doubler is –97.6dBc/Hz at 500kHz offset with an

input signal phase noise of –105dBc/Hz at 500kHz.

Figure 5.9 Phase noise of the frequency doubler

Figure 5.10 shows the phase noise of the doubler operating at

different operating frequencies. For ease of comparison, the input signal

phase noise (from the oscillator) at different operating frequencies is also

plotted on the same figure. Theoretically, the phase noise of doubler should

be degraded by 6dB. However, the measurement results show that the

phase noise is degraded by around 7dB on average. This is because the

doubler itself contributes some noise to the output and that is unavoidable.

Since the phase noise of ring oscillator is quite constant over the entire

range of operation, the phase noise of doubler remains constant. The

-97.6dBc/Hz


Chapter 5 - 98 -

variation of phase noise is less than 2.5dB throughout the whole operating

frequency range. Table 5.2 summaries the measurement results of the

frequency doubler.

Figure 5.10 Phase noise measurement results of different input frequencies

Table 5.2 Measurements results of the frequency doubler


Voltage Supply 1.8V 1.8VMaximum Output Operating Frequency >2.4GHz 2.6GHz

Output Bandwidth / 1.6GHz-2.6GHzOutput Signal Strength >200mVpp 0dbm (~200mVpp)

Phase Noise / -97.6dBc@500kHzPower Consumption <5mW 3.6mW


Chapter 5 - 99 -

5.4 Frequency Divider & Multi-Modulus Divider

The measurement setup of frequency dividers is shown in figure 5.11.

Instead of measuring the dividers directly, a duplicated testing structure

including the high-speed frequency divider, half-speed frequency divider and

multi-modulus divider, are being measured. A single-ended input signal is

generated by a signal generator HP 4648C and converts it to the differential

signals by using a power splitter. The differential signal is applied to the

circuit through a high-speed (40GHz) signal-ground-signal (SGS) probe. A

high-impedance probe senses the buffered outputs of the dividers and an

HP54522A digital oscilloscope and HP8510E spectrum analyzer are used to

observe the signal.

Figure 5.11 Testing setup of frequency dividers and multi-modulus divider

SignalGenerator

PowerSplitter

Digital Scope

BufferedOutput

TestingStructure

S

G

S


Chapter 5 - 100 -

All frequency dividers and multi-modulus divider are measured at

1.8V supply. The measured maximum operating frequency is 1.3GHz. The

total power consumption is 23.4mW including the power of on-chip buffers. A

single-ended input signal swing generated by the signal generated is 8dBm

at 1.25GHz. The power splitter converts this signal to the differential input

signals, which is 5dBm (around 0.8Vpp). Figure 5.12 and 5.13 show the

output waveforms of the high-speed divider with input signal of 1.25GHz.

The multi-modulus divider is measured at different modulus (from 64-71).

Figure 5.14 shows the output waveforms of the multi-modulus divider with a

modulus 67. Table 5.3 summarizes the measurement result of the dividers.

Figure 5.12 Output waveform of full-speed frequency divider operating at 625MHz


Chapter 5 - 101 -

Figure 5.13 Output waveform of half-speed frequency divider operating at 312.5MHz

Figure 5.14 Output waveform of multi-modulus frequency divider with modulus 67

Table 5.3 Measurements results of the frequency dividers and multi-modulus divider


Voltage Supply 1.8V 1.8vMaximum Output Operating Frequency >1.3GHz 1.3GHz

Power Consumption <30mW 23.4mW


Chapter 5 - 102 -

5.5 Proposed Frequency Synthesizer

The measurement setup for the proposed frequency synthesizer is

shown in figure 5.15. A signal generator is used to provide the reference

frequency (fref = 18MHz) for the synthesizer. A DC-probe connected to the

digital oscilloscope (HP54522A) is used to measure the control voltage of

the synthesizer. The buffered outputs of the voltage-controlled oscillator and

the frequency doubler are probed by a high-speed signal-ground-signal

(SGS) probe and are measured by spectrum analyzer. The target of the

measurement is to test the spurious tone performance, phase noise, settling

time and I-Q mismatch performance of the frequency synthesizer.

Figure 5.15 Testing setup of proposed frequency synthesizer

High-speed probe

PhaseDetector

Charge Pump& LPF

Fout




FrequencyDoubler X2

VCO

Fdiv

SignalGenerator

DigitalScope

SpectrumAnalyzer

High-Z probe18MHz


Chapter 5 - 103 -

5.5.1 Spurious Tone Performance

The output power spectrum of the proposed synthesizer is shown in

figure 5.16 with a reference frequency (18MHz) operating at 2.448GHz.

Since there is a loss due to the high-impedance probe, the actual output

power is around 0dBm, which is corresponding to 0.2Vpp at 50Ω system. The

spurs are –51.5dBc at 18MHz frequency offset and –52.8dBc at 36MHz

frequency offset. The results are 2.5dB better than the specification at

18MHz.

Figure 5.16 Measurement results of the spurs at 2.448GHz with RBW=10kHz

5.5.2 Phase Noise

The phase noise of the closed-loop ring oscillator shown in figure 5.17

and is measured to be –99.6dBc/Hz at 500kHz offset operating at

-51.5dBc-52.8dBc


Chapter 5 - 104 -

2.448GHz. The corresponding phase noise of the closed-loop synthesizer

(frequency doubler) shown in figure 5.18 is measured to be –92.5dBc/Hz at

500kHz offset. The expected value is –94.6dBc/Hz at the same offset. The

degradation is mainly because the phase noise of the ring oscillator has

dropped by 3dB. Also, the noise coming from the frequency divider degrades

the total phase noise of the proposed synthesizer. Fortunately, the phase

noise of the synthesizer still meets the requirements of the specification (-

89dBc/Hz at 500kHz offset).

Figure 5.17Phase noise of the closed-loop ring oscillator

-99.6dBc/Hz


Chapter 5 - 105 -

Figure 5.18 Phase noise of the closed-loop frequency doubler

5.5.3 Settling Time

In order to measure the settling time of the synthesizer, the control

voltage of the voltage-controlled oscillator is measured. The control voltage

is probed by a DC probe and is monitored by a digital oscilloscope

(HP54522A) when the division ratio of the multi-modulus divider is changing.

The requirement of the settling time is 65µs. The measured settling time

shown in figure 5.19 is less than 55µs with a 72MHz frequency step of the

proposed synthesizer. The settling time of synthesizer is fast enough for the

Bluetooth system which adopts a frequency hopping scheme with a rate of

1600hops/s. The output frequency is within 100kHz of the final value (the

voltage settles within an accuracy of 0.2mV and corresponds to 0.2mV x

-92.5dBc/Hz


Chapter 5 - 106 -

500MHz = 100kHz considering the VCO gain is 500MHz). The

corresponding resolution is 10% of the channel bandwidth (1MHz).

Figure 5.19 Measured settling time with frequency step 72MHz

5.5.4 I-Q Mismatch

The I-Q mismatch of the synthesizer output is measured by using a

single-side-band mixer. The mixer up-converts a low-frequency signal with

the synthesizer outputs. The resulting signals contains three tones, an upper

sideband signal, a lower sideband signal and the output of the synthesizer.

Assuming the low frequency signal has a very good amplitude and phase

matching, the amplitude difference between the upper and lower sidebands

represents the mismatches of the quadrate-output of the synthesizer. The

measured spectrum is shown in figure 5.20. The amplitude difference is

23.2dB, which means that the quadrate outputs of the synthesizer can

provide 23.2dB image rejection when the outputs apply to an image-rejection

mixer.


Chapter 5 - 107 -

Figure 5.20 Measurement result of IQ-mismatch

23.2dB


Chapter 5 - 108 -

5.6 Summary of Measurement Results

Table 5.4 summarizes the performance of proposed frequency

synthesizer. The proposed design is fabricated in a standard 0.35µm CMOS

process. The synthesizer is designed for thr Bluetooth application and is

measured at 1.8V. The power consumption is 55.9mW. The operating

frequency ranges from 2.04GHz to 2.556GHz. This range covers the whole

bandwidth of the Bluetooth specification (from 2.4GHz to 2.4835GHz).

The phase noise of the synthesizer is –92.5dBc/Hz at 500kHz

frequency offset. However, the phase noise performance is lower than the

expected value of 95.6dBc/Hz at the same offset. This is mainly because of

two reasons: the phase noise of the ring oscillator is 3dB lower than the

simulated value; and noise coming from the frequency dividers is not

included in the design stage. Fortunately, the phase noise margin of 6dB is

large enough and the measured phase noise is still 3.5dB better than the

specification. The other performances of the synthesizer can meet the

design specifications including the supply voltage, power consumption,

frequency resolution, spurs, settling time and chip area.


Chapter 5 - 109 -

Table 5.4 Summary performance of frequency synthesizer


Voltage Supply 1.8V 1.8VFrequency Range 2.4GHz – 2.4835GHz 2.304GHz – 2.556GHz

Frequency Resolution 1MHz 100kHzTuning range ~3% ~12%

Output Signal Strength >200mVpp ~200mVpp

Phase Noise @ 500kHz <-89dBc/Hz -92.5dBc/Hz (doubler)-99.6dBc/Hz (oscillator)

Spurious tone <-49dBc@18MHz -51.5dBc @ 18MHz-52.8dBc @ 36MHz

Switching time <62.5µs ~55usI-Q mismatch >20dB 23.2dB

Power <70mW 55.9mWTechnology TSMC 0.35µm CMOS TSMC 0.35µm CMOSChip Area <1mm2 0.69mm2


Chapter 5 - 110 -

5.6 Comparison

Table 5.5 summarizes the performance of proposed synthesizer and

some other monolithic CMOS frequency synthesizers in recent years for

comparison. All of the reported designs are operated at 2.4GHz or 2.6GHz.

Assume the phase noise is roll-off of 20dB per decade, the phase noise

performances of all designs is recalculated to a frequency offset of 500kHz

for a fair comparison. Although all other designs are fabricated in a more

advance technology, the proposed design has the smallest chip area, lowest

supply voltage. Also this work is a truly monolithic CMOS design with on-chip

loop filter and without any on-chip spiral inductors. However, it can still

satisfy all the requirements of Bluetooth application. The other performances

are comparable to the others.


Chapter 5 - 111 -

Table 5.5 Comparison of recent reported designs

Parameters Ref. [2] Ref. [3] Ref. [4] This work

Voltage Supply 2.6V 3.3V 2.6V 1.8VArchitecture Fractional-N Fractional-N Integer-N Fractional-NFrequency 2.4GHz 2.5GHz 2.6GHz 2.4GHzReferenceFrequency

5MHz 24MHz 11.75MHz 18MHz

Loop Bandwidth 35kHz 700kHz N/A 100kHzTuning Range N/A N/A N/A 288MHzPhase Noise@ 500kHz

-88dBc/Hz -100dBc/Hz -84dBc/Hz -92.5dBc/Hz

Spurious tone -85dBc -77dBc -55dBc -51.5dBcSwitching time N/A 5µs 40µs 55µsI-Q mismatch N/A N/A N/A 23.2dB

Power 16mW 135mW 47mW 55.9mW

Technology0.35µm25GHz

BiCMOS

0.5µmCMOS

0.45µmCMOS

0.35µmCMOS

On-chip filter N/A No Yes YesOn-chip Inductor N/A Off-chip

VCOYes No

Chip Area 6.2mm2 3.5mm2 2 mm2 0.69mm2


Chapter 5 - 112 -

References

[1] T. Friedrich, “Direct Phase Noise Measurements Using a Modern Spectrum

Analyzer,” Microwave Journal, vol.35, pp. 94-104, Aug. 1992

[2] Woogeun Rhee, Member, IEEE, Biagio Bisanti, and Akbar Ali, B., “An 18-mW 2.5-

GHz/900-MHz BiCMOS Dual Frequency Synthesizer With <10-Hz RF Carrier

Resolution,” IEEE JSSC, vol. 37 pp. 515-520, Apr. 2002

[3] Wilingham, S., Perrott, M., Setterberg, B., Grzegorek, A. and McFarland,

B., “An 2.5-GHz Integrated Sigma/Delta Frequency Synthesizer with 5µs Settling

and 2Mb/s Closed Loop Modulation,” IEEE ISSCC, pp. 200-201, 2000

[4] Lam, C., Razavi, B., “A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-/spl mu/m

CMOS technology,” IEEE JSSC, vol.35, pp. 788-794, May. 2000


Chapter 6 - 113 -

Chapter 6

Conclusion

The goal of Bluetooth is robustness, low complexity, low power and

low cost. A 1.8-V 2.4-GHz fractional-N monolithic CMOS inductorless

frequency synthesizer is presented in order to fulfil the goal and the

specifications of Bluetooth application. A special architecture has been

proposed to meet the targets of Bluetooth standard.

The quality factor of on-chip spiral inductors is usually very low and is

not satisfied in standard CMOS process. These inductors occupy a large

chip area and are sensitive to process variation. One of the targets of the

proposed design is to avoid using these on-chip spiral inductors. Thus, a

frequency doubler is designed and used at the output of the voltage-

controlled oscillator to double the oscillating frequency. It relaxes the

operating frequency of the oscillator by half. Therefore ring oscillator without

any inductors can be used to replace an LC-oscillator. Because of ring

oscillator co-operating with the frequency doubler, their output oscillating

frequency range can be up to 1GHz, which should be large enough to


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compensate any process variation. It makes the implemented synthesizer

more robust.

Because of the speed requirement of the ring oscillator is relax, the

requirements of other high-speed building blocks, likes frequency dividers

and multi-modulus divider are also relax. It makes the complexity of the

designs can be greatly simplify and the power consumption of these building

blocks is much reduced.

Also, the Bluetooth system employs the frequency hop scheme, the

settling time of the synthesizer is very important. The loop bandwidth is

usually the critical parameters to affect the settling time. A large loop

bandwidth is desired to increase the time settling down before the hopping.

However, the phase noise coupling from the charge pump and loop filter is

so large that affects the total phase noise of the synthesizer. Fortunately, the

phase noise requirement is not critical. It means that the loop bandwidth can

be larger to tolerate the phase noise performance. The capacitance used to

implement the filter can be smaller. Without the on-chip spiral inductors and

smaller capacitor, the chip area is reduced significantly. It can save the cost

of implementation.

Implemented in a 0.35µm CMOS process and measured at a 1.8V

voltage supply, the results can meet all the requirements of the Bluetooth


Chapter 6 - 115 -

specification including frequency range, phase noise, spurious tone and

settling time. The synthesizer operates at 2.4GHz with a range of 288MHz

and consumes 55.9mW. The phase noise of the whole synthesizer achieves

–92.5dBc/Hz at 500-kHz frequency offset operating at 2.448GHz. The phase

noise performance is 3dB lower than the expected value, the degradation is

mainly due to the phase noise of the ring oscillator getting worse. The

spurious tone is –53dBc at 18-MHz frequency offset, which is 4dB better

than the specification. The settling time is 55µs and the chip area is

0.69mm2. The mismatch between I and Q of quadrature outputs is around –

23.2dB, which gives around –23.2dB image rejection if a quadrature down-

conversion receiver architecture is used.

Documents

A 1.8-V 2.4-GHz Monolithic CMOS Inductor-less Frequency … · 2003-08-14 · A 1.8-V 2.4-GHz Monolithic CMOS Inductor-less Frequency Synthesizer for Bluetooth Application By Wong