Analog Integrated Circuits and Signal Processing, 32, 219–230, 2002©C 2002 Kluwer Academic Publishers. Manufactured in The Netherlands.

A 1.2 V Rail-to-Rail Analog CMOS Rank-Order Filter with k-WTA Capability

YU-CHERNG HUNG AND BIN-DA LIUDepartment of Electrical Engineering, National Cheng Kung University, Tainan 70101, Taiwan, R.O.C.

E-mail: bdliu@cad.ee.ncku.edu.tw; ych@cad.ee.ncku.edu.tw

Received January 28, 2000; Revised September 16, 2000

Abstract. In this paper, we design a rank-order filter with k-WTA capability for 1.2 V supply voltage. The circuitcan find a rank order among a set of input voltages by setting different binary signals. Moreover, without modifyingthe circuit, the k-WTA function can be easily configured. The circuit has been designed using a 0.5 µm DPDMCMOS technology. Seven input voltages are used to verify the performance of the circuit. The results of HSPICEpost-layout simulation show that the response time of the circuit is 10 µs for each rank-order operation, the inputdynamic range is rail-to-rail, and the resolution is 10 mV for 1.2 V supply voltage. An experimental chip has beenfabricated, in which accuracy of the comparator is measured as 40 mV for low-voltage operation. The dynamicpower dissipation of the chip is 550 µW.

Key Words: low voltage operation, rank-order filter, k-WTA

1. Introduction

The rank-order filter is designed to select the kth largestelement ak among n variables a1, . . . , an . In circuit de-sign, these variables are represented by current or volt-age signals. It is an important function in digital im-age and signal processing application. A median filter(Med) finds the median variable among a window ofsamples. It is used to filter impulse noise so as to sup-press the impulsive distortions. The maximum (Max)and minimum (Min) filters are useful for pattern clas-sifier [1,2] and fuzzy logic design [3–5]. Nevertheless,all of them are a special situation in a rank-order fil-ter. The Winner-Take-All (WTA) network is an im-portant component of artificial neural networks. Thefunction of a WTA network is to select and identifythe largest variable from a specified set of variables.Instead of choosing only one winner, the k-WTA net-work selects the largest k numbers among n compet-ing variables (k ≤ n), which allows for more flexibilityin applications. In addition, portable equipment suchas biomedical electronics, calculator, computer andportable telecommunication equipment are frequentlyused in recent year. Battery operation and low-powerconsumption are essential requirements for portableequipment design. Moreover, it is necessary to reducethe voltage supply of the VLSI circuit for sub-micron

technologies due to the hot-electron effect. Thus, thecircuit design of a rank-order filter for these require-ments is useful for industrial applications. Many digitalarchitectures and analog circuits have been proposedfor the nonlinear filters [6–9]. However, the voltagesupply and power consumption of these circuits arenot low enough for these applications. In addition, inthe previous digital architectures, the analog to digital(A/D) converter is always needed if the input signal iscontinuous.

In this paper, we design a rank-order filter withk-WTA capability working at low voltage supply. Thisproposed circuit with regular structure is constitutedwith comparator cells and evaluation cells. In our de-signs, the comparator cell accepts two input voltagesand produces four outputs unit current to identify whichinput variable is large or small. The circuit of eachcomparator cell is identical within the rank-order fil-ter, and these cells operate in analog mode to allowrail-to-rail input dynamic range. In order to reduce theresponse time of the circuit, the dynamic logic oper-ation is adopted. After the comparator is processed,the results of the comparison are sent to these evalu-ation cells. In these cells, the current comparator anddecision circuits are designed. According to the binarysignals’ setting, the outputs of the evaluation cells in-dicate which input variables belong to this rank order.

220 Hung and Liu

Without modifying the circuit, this design can find thearbitrary rank order among a set of input variables bysetting different select-signals. Moreover, the filter canbe easily configured as a k-WTA function by an enablesignal.

Section 2 presents an outline of the rank-order fil-ter and k-WTA. In this section, we also describe thebuilding block circuits of the rank-order filter; there arethe comparator cell and the evaluation cell. For VLSIcircuit design, some factors must be considered to im-prove the speed and precision; there are described inSection 3. Section 4 demonstrates the post-layout sim-ulation and measurement results of the experimentalchip. Finally, a brief conclusion is given in Section 5.

2. Basic Concept and Circuit Description

2.1. Definition

A set of output voltages (Vo 1, Vo 2, . . . , Vo M ) corre-sponds to the output voltages of the rank-order filterfor inputting of a set of variables (V1, V2, . . . , VM ).The output status Di j of a comparator with two-inputterminals is defined as

Di j ={

1 if Vi > Vj

0 otherwise1 ≤ i, j ≤ M, j �= i (1)

where M is the number of the input variables. For con-venience of description, the temporal index Si definesthe total number of winners for the i th input variablecompared with the others. Thus, the Si can be repre-sented as

Si =M∑

j=1, j �=i

Di j 1 ≤ i ≤ M (2)

Based on the definition of equation (2), the Si can beexpanded as follows

S1 = D12 + D13 +· · ·+ D1M (3a)

S2 = D21 + D23 +· · ·+ D2M

= D12 + D23 +· · ·+ D2M (3b)

S3 = D31 + D32 +· · ·+ D3M

= D13 + D23 +· · ·+ D3M (3c)

. . .

SM = DM1 + DM2 +· · ·+ DM(M−1)

= D1M + D2M +· · ·+ D(M−1)M (3d)

Thus, from the left-hand side of equation (3),M(M −1) comparators’ cooperation is needed for Minput variables to identify the rank order. Because D ji

is the complementary of Di j (D ji = Di j ), the expres-sion can be replaced by Di j in the right-hand side ofequation (3). The physical meaning is that if both theoutput of the comparator and its complementary can begiven, the total number of comparators can be reducedfrom M(M −1) to M(M −1)/2.

In this paper, the proposed comparator generates aunit current Iunit when input variable Vi is larger thanVj . Thus, the index Si in equation (2) can be rewrittenas

S∗i =

M∑j=1, j �=i

Di j Iunit 1 ≤ i ≤ M

= nIunit, 0 ≤ n ≤ (M −1) (4)

where n is the number of the winner in comparison. Ifthe inputs are arranged in ascending order of magni-tude, V1, V2, . . . , VM , which satisfy

V1 < V2 < · · · < VM

then the S∗1 = 0, S∗

2 = Iunit, . . . , S∗M = (M −1)Iunit.

Obviously, we can find the minimum, next mini-mum, . . . , maximum input variables by checking theindex S∗

i . The k-WTA function is defined so that theoutputs must be logic high when

S∗i ≥ (M − k)Iunit

For example, if the input variables are (0.5, 0.6, 0.9,0.2, 0.4), the first variable 0.5 is larger than variables0.2 and 0.4. Thus, the index S∗

1 is 2Iunit; the meaning isthat the variable wins two other input variables amongall comparisons. For the same reason, the S∗

2 = 3Iunit,S∗

3 = 4Iunit, S∗4 = 0, S∗

5 = Iunit. Therefore, we can findthe rank order among the input variables by check-ing the index S∗

i . In this example, the output voltages(Vo 1, Vo 2, . . . , Vo 5) of the filter will be (0, 0, 1, 0, 0),(0, 1, 0, 0, 0), (1, 0, 0, 0, 0), (0, 0, 0, 1, 0) for maxi-mum operation, next maximum operation, median op-eration, minimum operation, respectively. The “0” and“1” are the logic low and high. Similarity, if the filteris configured as k-WTA function, the output voltages(Vo 1, Vo 2, . . . , Vo 5) of the filter will be (1, 1, 1, 1, 1),(1, 1, 1, 0, 1), (1, 1, 1, 0, 0), . . . , (0, 0, 1, 0, 0) for 5-WTA,4-WTA, 3-WTA, . . . , 1-WTA operation, respectively.

A 1.2 V Rail-to-Rail Analog CMOS Rank-Order Filter 221

Fig. 1. Basic auto-zero comparator cell and clock.

2.2. Comparator

To begin with, comparator is the essential circuit forthe rank filter. In order to increase the stability of thefilter in VLSI circuit design, an auto-zero technique isadopted. A basic auto-zero comparator [10] and clockwaveform are shown in Fig. 1. The comparator operatesin two phases, the auto-zero phase and the comparisonphase. In the auto-zero phase, the clock Vs1 goes highto sample V1 at node A and biases the inverter-1 athigh gain region (the inverter-1 biased at Vb). Duringthe comparison phase, Vs1 goes low and Vs2 goes high

Fig. 2. Low-voltage operating auto-zero comparator cell, clock, and symbol representation.

simultaneously to sample V2 at node A. By the chargeconservation at node B, the voltage Vx of node B at thismoment is

Vx = Vb + (V2 − V1)Cs

Cs +C p(5)

where Cs is the sampling capacitance, C p is the sum-mation of the parasitic capacitance and the input ca-pacitance of the inverter-1. The term Cs/Cs +C p is adegradation factor, and it will be discussed in Section 3.The succeeding inverter-2 and inverter-3 provide suf-ficient gain to amplify the magnitude of the differencevoltage V2 − V1. The voltage at node D is logic 1 if V1 islarger than V2, or vice versa. Because the performanceof the comparator is not sensitive to the dimension ofthe MOS transistors, it is more tolerant to the processvariation. However, the basic comparator can not workwell in low-voltage supply, especially when the voltageV2 is near the voltage V1. Therefore, a new auto-zerocomparator is designed to operate at low voltage supply.To improve the speed of the comparator, the gain stageis designed to operate in dynamic mode. The schematicdiagram of the new comparator is shown in Fig. 2.

Basically, the operation of the new comparator re-sembles the basic comparator in Fig. 1. In the auto-zerophase, the input V1 is sampled at the top plate of the

222 Hung and Liu

capacitor Cs , and the MOS transistor M11 is biasedat Vbias voltage. In next phase, the voltage at node Eis Vbias + (V2 − V1)(Cs/Cs +C p) during the compari-son phase. Then, the deviation voltage is amplified bytransistors M11 and M12. To reduce the power dissi-pation, the adjustable biasing voltage Vbias is chosenjust to overcome the threshold voltage of MOS tran-sistor, and the biasing voltage also can adjust the com-parator operation for different voltage supplies. Thesucceeding transistors M13 and M14 provide the cur-rent to generate the proper voltage at node F. Depend-ing on which input voltage is larger, either the voltageat node H or node G will be at logic high. The out-put node G of the comparator and its complementarynode H are fed into next stage to generate unit cur-rents Ilarge 1, Ilarge 2, Ismall 1, and Ismall 2. During theevaluation phase, the unit currents Ilarge 1, Ilarge 2 willbe presented when V1 is larger than V2. Otherwise, theIsmall 1, Ismall 2 are generated. The symbol representa-tion of the comparator cell is shown in the right-bottomof Fig. 2. The function of the comparator is summarizedas

V1 > V2

{Ilarge 1 = Ilarge 2 = Iunit,

Ismall 1 = Ismall 2 = 0

}

V1 < V2

{Ilarge 1 = Ilarge 2 = 0,

Ismall 1 = Ismall 2 = Iunit

}

where Iunit is the unit current of the PMOS transis-tor Mbase. The layout area of a single comparator is150×100 µm2 (including the sampling capacitor Cs)by using 0.5 µm CMOS technology.

2.3. Circuit Architecture

The structure of the filter is shown in Fig. 3 for seveninput variables. There are a total of n(n −1)/2 com-parators and n evaluation cells for n input variables.Each comparator cell accepts two input signals, andthe results of each comparison are fed into the individ-ual evaluation cell. In the first row of Fig. 3, the input V1

is compared with other input variables. In addition, theresults of the comparison will generate the proper unitcurrents Iunit. Then, these currents will be summed upin eval-1 cell if V1 is larger than the other samples; oth-erwise, the result of the comparison will be fed into thecorresponding evaluation cell. The connecting strategyis the same for other input variables. Therefore, equa-tion (4) have been realized in this architecture. For the

Fig. 3. The architecture of the rank-order filter for seven inputvariables.

structure of Fig. 3, the modular and expandable designis obvious.

The signal Vchoose in Fig. 3 is used to decide thefunction of the filter. The Vchoose is preset at logic highto allow the rank-order operation; otherwise, the k-WTA function is enabled. The sel 1, sel 2, and sel 3 bi-nary signals are used to determine which rank-order/k-WTA will be found. Based on the select signals (sel 1–3) setting, the logic states of the evaluating cells in-dicate which input variable belongs to this rank or-der. For example, in the rank-order operation, the(sel 1, sel 2, sel 3) signals are set to logic (0, 0, 0)to find the minimum voltage; the logic (0, 1, 1) and(1, 1, 0) setting are the median and maximum func-tions, respectively, when the number of input vari-ables is seven. Similarity, in the k-WTA operation, the(sel 1, sel 2, sel 3) is set as (0, 0, 1) and (1, 1, 0); there-fore, the 6-WTA and 1-WTA are obtained, respectively.For concision, the clock signals in comparators and thereset signal in evaluation cells are not shown in Fig. 3.

2.4. Evaluation Cell

The circuit of the evaluation cell is shown in Fig. 4,and the symbol representation of the cell is shown onthe right side. The rhombus symbol represents that theevaluation cell is a decision object. The MOS transis-tors Mgen and Munit reproduce the same unit current.The unit current is equal to the Ilarge 1, Ilarge 2, Ismall 1,and Ismall 2 in Fig. 2. In order to find the various rankorders for all input signals, the cell must identify thatthe unit-current summation in equation (4) comes fromthe Out com1 and Out com2 terminals. It is not easy

A 1.2 V Rail-to-Rail Analog CMOS Rank-Order Filter 223

Fig. 4. Evaluation cell and symbol representation.

to identify the exact current value in the VLSI circuit.However, we can check whether the summation currentS∗

i lies inside a valid range or not by the criterion,

nIunit − δ1 < S∗i < nIunit + δ2 (6)

It is a reasonable and safe design to choose the δ1 =δ2 = Iunit/2. Therefore, the dimensions of these MOStransistors are designed as(

W

L

)M1

=(

W

L

)M5

= 4

(W

L

)Munit(

W

L

)M2

=(

W

L

)M6

= 2

(W

L

)Munit(

W

L

)M3

=(

W

L

)M7

=(

W

L

)Munit(

W

L

)M4

=(

W

L

)M8

= 1

2

(W

L

)Munit

where W is channel width and L is channel length.MOS transistors Madd1 and M4 realize the δ2 effect,and the M8 realizes the −δ1 one. Depending on thesel 1–3 signals setting, the transistors Mcnt 1–6 enablethe corresponding binary-weight current. The invert-ers inv4–7 support sufficient gain to amplify the cur-rent difference between the currents which come fromOut com1–2 terminals and the binary-weight currents.This mechanism is like a current comparator. In theupper row of Fig. 4, the extra PMOS transistor Madd1

generates an extra unit current, so the voltage Vout-h isalways larger or equal to Vout−l . If the Vchoose is presetto 0, the dash block in Fig. 4 resets the Vout-l to 0. Thenthe effect of lower row in Fig. 4 is disabled. Now, thefunction of the cell resembles only checking the

S∗i < nIunit + δ2 (7)

Thus, this is a k-WTA criterion.

224 Hung and Liu

Take an example to describe the function of the eval-uation cell. The number of input variables is seven, andthe sel 1–3 signals are set as (0, 0, 1) to find the nextminimum input voltage. Because the next minimumis only larger than the minimum one, only a singleunit current comes from the Out com1–2 terminals ofthe corresponding evaluation cell. In the upper row ofFig. 4, the summation of one unit current and the extraunit current (Madd1) is larger than binary weight cur-rent 1.5Iunit, so the Vout h is logic 1. In contrast withthe upper row, the unit current Iunit (which comes fromthe Out com1–2 terminals) is smaller than the binaryweight current 1.5Iunit in the lower row, so the Vout l

is logic 0. Thus, the transistors Mid1 and Mid2 only al-low the situation (Vout h, Vout l) = (1, 0) to pull up thecorresponding output (Vo n, n = 1, . . . , 7) to logic 1.Otherwise, the status of Vo n will be logic 0 or openstate for other cases. Therefore, by inspecting the logicstate of output voltage Vo n , it will be found which inputvariable belongs to this desired rank order.

3. Design Consideration

There are many factors which must be considered todesign a low-power low-voltage rank order filter, suchas precision, speed, process variation, and chip area.

3.1. Low Voltage and Low Power Limitation

The average power consumption of the circuit can bedescribed by

P = Pdynamic + Pstatic + Pshort current = f CV 2DD

+ (Io + Ileakage)VDD + Qsc f VDD (8)

where f is the frequency, C is the capacitance in thecircuit, VDD is the voltage supply, Io is the standbycurrent, Ileakage is the leakage current, and the Qsc is theshort-current charge during the clock transient period.In order to reduce the power consumption, the voltagesupply VDD must be reduced, and the standby currentin the comparator and evaluation cell must be designedas small as possible. The clock and its complementaryare generated locally to reduce delay and mismatch inlayout path. Thus, the probability of a short currentoccurring in the circuit is minimized.

Because the threshold voltage VT of MOS transistor,the noise in current, the precision of MOS current, the

speed requirement, and the signal-to-noise ratio (S/N )of the circuit will limit the design of a low-voltagelow-power circuit, three techniques are adopted in thispaper.

1. The inverter-type comparator is designed to reducethe number of MOS transistor stacks in the DC pathand to avoid the threshold voltage VT effect.

2. Dynamic logic is used in the comparator to improvethe operating speed.

3. The circuit is designed with rail-to-rail input capa-bility to further promote the S/N .

3.2. Speed and Precision

The accuracy of the comparators determines the reso-lution of the filter. In the comparator, the smallest dif-ference voltage that can be distinguished correctly isinfluenced by two factors. One is the charge-injectionerror in analog switches, and the other is the parasiticcapacitor C p effect. When these switches in the com-parator cell are turned off, the charges stored in theMOS transistor channel will escape to disturb the pro-cessed voltage. The effect can be reduced by enlargingthe sampling capacitor Cs and making the switchesdimension as small as possible.

The response time τ of the rank filter is the sum-mation of the auto-zero time τaz , the comparison timeτcmp, and the evaluation time τeval.

τ = τaz + τcmp + τeval (9)

Reducing the τaz , τcmp and τeval will improve theresponse time τ . The minimum auto-zero time τaz isneeded to sample the input voltage correctly at sam-pling capacitor Cs and to bias the inverter properly athigh gain region. The switches with larger dimensionshown in Fig. 2 can reduce auto-zero time τaz . How-ever, the clock feed-through error and charge injectionerror will also be enlarged during the clock transition.In the same situation, the smaller sample capacitor Cs

will reduce the time τaz . Unfortunately, it will be suf-fered more severely from the Cs/(Cs +C p) term inequation (5). This term will reduce the net magnitudeof the difference voltage; thus, the comparator accu-racy will be degraded. The comparison time τcmp dom-inates the filter response time τ , especially when theinput voltages are near each other. Because the shapeof transition region of the CMOS inverter operating atlow voltage supply is not very sharp, the comparator

A 1.2 V Rail-to-Rail Analog CMOS Rank-Order Filter 225

must take a long time to identify which input voltageis larger. The evaluation time τeval is defined so that thetime interval between the comparator cells generatesthe proper currents and the filter has finished findingthe rank order. The τeval is a function of the current Iunit,and the maximum number M of the input variables isalso influenced by the current Iunit. Although reduc-ing the magnitude of the current Iunit can reduce thepower consumption, however, the relationship amongτeval, Iunit and maximum number M in this structure isa complicated function. It is a tradeoff between speedand precision requirement for the filter.

3.3. Process Variation Analysis

With contemporary technology, variation during fabri-cation cannot be completely eliminated, so mismatcherror must be noticed in VLSI circuit design. The matchin dimension of the binary-weight MOS in the evalu-ation cell (M1–M8 in Fig. 4) is an important factorfor the filter operation. Due to the process variation,the mismatch error is not avoidable in VLSI. If themismatch error induces an error current Ierr larger (orsmaller) than half of the unit current Iunit, the decisionof the evaluation cell will fail. Thus, a rough estimatedconstraint for Ierr is

Ierr < Iunit/2 (10)

In addition, mismatch error in transistors M11–M14shown in Fig. 2 degrades the comparator’s accuracy. Tosimply this analysis, the variations in threshold volt-ages are omitted for clear expression. In Fig. 2, thetransistors M11–M14 and the biasing voltage Vbias aredesigned to make the voltage at node F as close asthe voltage Vb and to reduce power consumption dur-ing auto-zero phase. Nominally, assume that the aspectratio of the transistors M11–M14 are (W/L)M11,(W/L)M12, (W/L)M13 and (W/L)M14, respectively,and these dimensions are designed as

(W/L)M13

(W/L)M11= r and

(W/L)M14

(W/L)M12= s (11)

where r and s are constants. Since the process variationoccurs, the actual dimensions of M13 and M14 can beexpressed as

(W/L)∗M13 = (W/L)M13(1+�M13) (12)

(W/L)∗M14 = (W/L)M14(1+�M14) (13)

where �M13 and �M14 are deviation percentage of M13and M14, respectively. During the comparison phase,the drain-to-source currents of these MOS transistorsoperated in the saturation region are given by

IM11 = 1

2µnCox

(W

L

)M11

(Vgs − Vtn)2

= 1

2µnCox

(W

L

)M11

×(

�VCs

Cs +C p+ Vbias − Vtn

)2

(14)

IM13 = 1

2µnCox

(W

L

)∗

M13

(Vgs − Vtn)2

= 1

2µnCox

(W

L

)M13

(1+�M13)(Vbias − Vtn)2

(15)

IM14 = (W/L)∗M14

(W/L)M12IM12 = (W/L)∗M14

(W/L)M12IM11

= s(1+�M14)IM11 (16)

where

µn mobility of electron;Vgs gate-to-source voltage;Vtn threshold voltage of NMOS;

�V input differential voltage V2 − V1;Cs sampling capacitance;C p parasitic capacitance.

For a successful comparison, the voltage at node F islower than the voltage Vb after comparison phase ifinput voltage V2 is smaller than V1(�V < 0). Thus, theconstraint

IM14 < IM13 (17)

must be satisfied. Using equations (11)–(17), the con-straint due to the variation of dimensions can be derivedas

|�V | >

(1+ C p

Cs

)(Vbias − Vtn)

×(

1−√

r(1+�M13)

s(1+�M14)

)(18)

Consider C p/Cs = 0.01, Vbias = 0.9 V, Vtn = 0.7 V,r/s = 0.96, and no variation (�M13,M14 = 0). Accord-ing to equation (18), the maximum accuracy of thecomparator cell is about 4 mV. In addition, if variation

226 Hung and Liu

percentage of M13 is 1% (�M13 = 0.01) and the accu-racy of 10 mV is required, then, the variation percent-age of M14 must be smaller than 7% (�M14 < 0.07) tomake a successful comparison. However, equation (18)is a rough estimation for mismatch-error effect in com-parator cells because many non-ideal factors are omit-ted in previous derived such as clock feed-througheffect, variation of threshold voltage, voltage-supplynoise, and finite inverter’s gain.

4. Simulation and Measurement Results

4.1. Simulation Results

Seven variables were used as the experimental chip in-puts to verify the circuit performance. This number ofinput variables is sufficient to use in fuzzy logic andone-dimensional signal processing. Based on the res-olution and wide input range inspection, we set theinput voltages (V1, V2, V3, . . . , V7) to (0, 0.01, 0.59,0.6, 0.61, 1.19, 1.2 V) as testing input voltages. Theselecting signals sel 1–3 determine which rank willbe found, and it sets the rank order from minimum,next minimum, . . . , maximum in turn for every 10 µsperiod. The times of the auto-zero, comparison, andevaluation phases are 1, 6 and 3 µs, respectively. Thecircuit is designed by 0.5 µm CMOS technology. Thebias voltage Vbias is set to 0.9 V in this design. The sam-pling capacitor Cs is 0.8 pF, and these analog switchesin this circuit are implemented by CMOS transmis-sion gates. The micrograph of the experimental chip isshown in Fig. 5, and the active area is 610×780 µm2.

The post-layout simulated results of HSPICE areshown in Fig. 6(a). When the filter is configured asrank-order function (Vchoose is set to 1), then the mini-mum input voltage V1 will be identified at 10 µs, andthe next minimum voltage V2 will be found at 20 µs.For the same reason, other rank orders will be found at30, 40, 50, 60, and 70 µs, respectively. In this design,the operation of the filter for each rank order findingwill be finished at 10 µs cycle. Similarity, when thek-WTA is enabled (Vchoose is set to 0), Fig. 6(b) showsthe output results of the filter using the same testinginput voltages. The outputs of the filter show 7-WTA,6-WTA, . . . , 1-WTA operation at t1, t2, . . . , t7, respec-tively. Obviously, the results show that 10 mV can bedistinguished in 0–1.2 V input. The resolution of thefilter is near seven bits, so it can be used in many in-dustrial applications.

Fig. 5. Micrograph of the experimental chip.

4.2. Measurement Results

A seven-input experimental chip was fabricated usinga 0.5 µm CMOS double-poly-double-metal (DPDM)technology. The sampling capacitors were imple-mented by two layers of polysilicons. An individualcomparator cell was built in this chip for measuringthe accuracy. Under low-voltage operation, the supplyvoltage of the core circuit, the supply voltage of theinput/output pads, and the voltage of logic “1” were allset as 1.2 V. The accuracy of individual comparator wasmeasured as 40 mV, that is, the resolution of the com-parator was near five bits under 1.2 V supply-voltageoperation. Input variables (V1, V2, . . . , V7) were set at(0, 0.3, 0.5, 0.7, 0.9, 1.0, 1.2 V) to test the rank-orderfunction and k-WTA function. For simplicity, Fig. 7(a)showed output voltages Vo 1–Vo 4. The minimumvariable was found at t1, then, the next minimum onewas found at t2. Obviously, rank-order function wasachieved. Figure 7(b) showed the function of the k-WTA using the same inputs, but the Vchoose was setto 0. The functions of the 7-WTA, 6-WTA, . . . , and4-WTA were obtained at t1, t2, . . ., and t4, respectively.On the average, the accuracy of whole circuit was about150 mV. The performance of the chip was degraded bymany factors such as the mismatch in comparator cells,the different capacitance at input terminals of the eval-uation cells, and the clock feed-through error. Due to

A 1.2 V Rail-to-Rail Analog CMOS Rank-Order Filter 227

Fig. 6. The results of the HSPICE post-layout simulation of the filter for the input voltages (V1, V2, . . . , V7) = (0, 0.01, 0.59, 0.6, 0.61, 1.19,

1.2 V). The selecting signals (sel 1, sel 2, sel 3) are set to logic (0, 0, 0), (0, 0, 1), . . . , (1, 1, 0) in turn for every 10 µs. (a) The filter findsthe minimum, next minimum, . . . , maximum variables at t1, t2, . . . , t7 for rank-order function, respectively. (b) The outputs of the filter show7-WTA, 6-WTA, . . . , 1-WTA operations at t1, t2, . . . , t7 for k-WTA function, respectively.

228 Hung and Liu

Fig. 7. The measurement results of the experimental chip for the input voltages (V1, V2, . . . , V7) = (0, 0.3, 0.5, 0.7, 0.9, 1.0, 1.2 V). Theselecting signals (sel 1, sel 2, sel 3) are set to logic (0, 0, 0), (0, 0, 1), . . . , (1, 1, 0) in turn for every 20 µs. For simplicity, only output voltagesVo 1–Vo 4 are shown in this figure. (a) Rank-order function. (b) k-WTA function.

these non-ideal effects, each rank-order function wasfinished in 20 µs. After increasing supply voltage upto 1.5 V and adjusting proper biasing voltage Vbias,the performance of the circuit was improved. Includ-

ing power consumption of the input/output pads, thestatic power consumption of the chip was 1.4 mW. Thedynamic power consumption was 550 µW. The char-acteristics of the circuit were summarized in Table 1.

A 1.2 V Rail-to-Rail Analog CMOS Rank-Order Filter 229

Table 1. Summary of the rank-order filter.

Technology 0.5 µm DPDM CMOSResponse time 20 µs for each rank-order finderSupply voltage 1.2 VComparator resolution 40 mVPower consumption static 1.4 mW, dynamic 550 µWDynamic input range rail to railSampling capacitor 0.8 pFChip active area 610 × 780 µm2 for seven inputsStructure n(n −1)/2 comparators,

n evaluation cells for n inputs.

5. Conclusion

A 1.2 V analog CMOS rank-order filter with k-WTAcapability was presented. The circuit could find the rankorder in 10 µs period, and it could distinguish 10 mVamong a set of input voltages by simulation. A seven-input experimental chip with rank-order and k-WTAfunctions was fabricated using a 0.5 µm CMOS tech-nology. Measurement results showed that the proposedcomparator with 40 mV accuracy could operate suc-cessfully within 20 µs. Without needing any charge-pump technique and A/D converter, the circuit couldwork at low voltage supply. Since the power consump-tion of this design was low, more elements could beaggregated together in a single chip without degradingthe performance. The circuit could be integrated withother battery-operation circuits for a portable equip-ment design. Moreover, the wide dynamic input rangewas more flexible to use in various applications.

Acknowledgments

This work was supported by the Chip ImplementationCenter and the National Science Council, Republic ofChina, under Grant NSC89-2215-E-006-021.

References

1. Robinson, M. E., Yoneda, H. and Sanchez-Sinencio, E., “A mod-ular CMOS design of a hamming network.” IEEE Trans. NeuralNetworks 3(3), pp. 444–455, 1992.

2. Choi, J. and Sheu, B. J., “A high-precision VLSI winner-take-allcircuit for self-organizing neural networks.” IEEE J. Solid-StateCircuits 28(5), pp. 576–583, 1993.

3. Sasaki, M., Inoue, T., Shirai, Y. and Ueno, F., “Fuzzy multiple-input maximum and minimum circuits in current mode andtheir analyses using bounded-difference equations.” IEEE Trans.Comput. 39(6), pp. 768–774, 1990.

4. Huang, C. Y. and Liu, B. D., “Current-mode multiple input max-imum circuit for fuzzy logic controllers.” Electron. Lett. 30(23),pp. 1924–1925, 1994.

5. Huang, C. Y., Wang, C. J. and Liu, B. D., “Modular current-modemultiple minimum circuit for fuzzy logic controllers,” in Proc.1996 Int. Symp. Circuits Syst., Atlanta, Georgia, pp. 361–363,1996.

6. Morgan, D. R., “Analog sorting network ranks inputs by ampli-tude and allows selection.” Electron. Design, pp. 72–73, 1973.

7. Lin, J. S. J. and Holmes, W. H., “Analog implementation of me-dian filters for real-time signal processing.” IEEE Trans. CircuitsSyst. 35, pp. 1032–1033, 1988.

8. Liu, B. D., Tsay, C. S., Chen, C. H., Lu, E. H. and Laih, C. S.,“An analog median filter with linear complexity for real-timeprocessing,” in Proc. IEEE Int. Symp. Circuits Syst., pp. 2565–2568, 1991.

9. Jarske, T. and Vainio, O., “A review of median filter systems foranalog signal processing.” Analog Integr. Circuits Signal Process3, pp. 127–135, 1993.

10. Hosotani, S., Miki, T., Maeda, A. and Yazawa, N., “An 8-bit20-MS/s CMOS A/D converter with 50-mW power consump-tion.” IEEE J. Solid-State Circuits 25(1), pp. 167–172, 1990.

Yu-Cherng Hung was born in Changhua, Taiwan,Republic of China, on May 22, 1964. He receivedthe M. S. degree in electronics engineering from theNational Chiao Tung University, Hsinchu, Taiwan in1992. He is currently working toward the Ph.D. degreeat National Cheng Kung University. His main researchinterests include analog circuit design, low-voltageVLSI design, and neural network applications.

Bin-Da Liu received the B. S., M. S., and Ph.D.degrees all in electrical engineering from the NationalCheng Kung University, Tainan, Taiwan, Republic ofChina, in 1973, 1975, and 1983, respectively.

From 1975 to 1977, he served as electrical officer inthe Combined Service Forces. Since 1977 he has beenon the faculty of the National Cheng Kung University,where he is currently professor and chair in the Depart-ment of Electrical Engineering. During 1983–1984, hewas a visiting assistant professor in the Departmentof Computer Science, University of Illinois at Urbana-Champaign. During 1988–1992, he was the Directorof Electrical Laboratories, National Cheng Kung Uni-versity. During 1996–1999, he was associate chair ofthe Electrical Engineering Department. From 1990 to1993 he was appointed as a member of the EvaluationCommittee for Junior Engineering College, Ministry of

230 Hung and Liu

Education, Republic of China. Since 1995 he has beena consultant of the Chip Implementation Center, Na-tional Science Council. His current research interestsinclude physical design and testing for VLSI circuits,

high-voltage integrated circuit design, and VLSI imple-mentation for fuzzy-neural networks and video signalprocessors. He has published more than 140 technicalpapers.