A 0.5-V Capless LDO with 30-dB PSRR at 10-kHzUsing a Lightweight Local Generated Supply

Chao Yang, Student Member, IEEE, Kaixuan Ye, Student Member, IEEE, and Min Tan*, Member, IEEE

Abstract—An analog low dropout regulator (LDO) that canoperate at ultra-low voltage (ULV) with high power supplyrejection ratio (PSRR) is presented in this brief. The suppliesof the error amplifier and the power stage in this LDO areseparated, and a lightweight local generated supply (LLGS) isproposed to guarantee the proper function of the associated erroramplifier in ULV mode. This LLGS assisted analog LDO hasbeen experimentally verified in 0.13µm CMOS technology and itonly occupies an active area of 0.035mm2. Measurement resultsindicate that this LDO can achieve greater than 30 dB PSRR upto 10 kHz at supply voltage as low as 0.5 V.

Index Terms—Low dropout regulator, Ultra-low voltage, HighPSRR, Charge pump, Lightweight local generated supply, Outputcapacitor free

I. INTRODUCTION

ULTRA-low voltage (ULV) mode operation is highly at-tractive in the state-of-art System-on-Chip (SoC) circuit

designs for its great advantage in power saving [1]. However,with the supply voltage of SoC continuously scaling down, thedesign of power management circuits, such as low dropoutregulator (LDO), for the noise-sensitive modules becomesincreasingly challenging.

Traditional analog LDO (Fig. 1 (a)) mainly consists of anerror amplifier and a power stage, and it forms a negativefeedback loop to generate a stable output voltage that isimmune to supply fluctuation and load change. To guaranteethe stability of the negative feedback loop, the supply voltageof the error amplifier should be sufficiently high to ensurethe associated transistors can operate in the saturation region.However, to obtain high energy efficiency, the dropout voltagebetween the supply and output of LDO should be kept as smallas possible. In ULV mode operation, the required output ofLDO is in the vicinity of the threshold voltage of the associatedtransistors, hence the supply voltage of LDO is either too lowfor the error amplifier to function properly or too high to beenergy efficient. In short, traditional analog LDO is unsuitablefor ULV mode operation.

To enable the LDO function properly in ULV mode, onepossible solution is to replace the analog LDO with all-digitalcircuits [2]–[9] (Fig. 1 (b)). However, as some units of thepower MOS array in digital LDO always toggle between fully

Manuscript received July 23, 2019; revised September 20, 2019 and October10, 2019; accepted November 10, 2019. This work was supported by theNational Natural Science Foundation of China under Grant 61904061. Thisbrief was recommended by Associate Editor H. Sekiya. (Chao Yang andKaixuan Ye are co-first authors.) (Corresponding author: Min Tan.)

The authors are with School of Optical and Electronic Information,Huazhong University of Science and Technology, Wuhan 430074, China(email: mtan@hust.edu.cn).

Error amplifier

Load

-+

Vref

VoutVfb

Power transistor

R1

R2

Vdd

Cout

(c)

VbatBattery

Error amplifier

Load

-+

Vref

VoutVfb

Power transistor

R1

R2

Vdd

Cout

(d)

LLGS

Load

Vout

R1

R2

Cout

Shift register

Power MOS array

CLK

Comp.

VrefVdd

…

(b)

Error amplifier

Load

-+

Vref

VoutVfb

Power transistor

R1

R2

Vdd

Cout

(a)

Fig. 1. Structures of (a) traditional analog LDO; (b) digital LDO; (c) analogLDO with two global supplies; (d) the proposed LLGS assisted analog LDO.

Traditional analog LDO

Digital LDO

Analog LDO with two global supplies

This work

ULV mode No Yes Yes Yes

High PSRR Yes No Yes Yes

Output ripple Small Large Small Small

Number of global supplies 1 1 2 1

TABLE ICOMPARISON OF THESE FOUR STRUCTURES

PropertyStructure

turned on and off, the digital LDO suffers from large steady-state ripple and the power supply rejection ratio (PSRR) per-formance is much worse than the analog counterpart. Anothersolution is to provide different voltages for the error amplifierand the power stage with two global supplies [1] (Fig. 1 (c)).Although it can achieve good PSRR performance and operatein ULV mode, the additional global supply would increase thedesign complexity of the power management module in SoCsas the number of LDOs increases. In this brief, we presenta novel low dropout regulator structure that can achieve highPSRR and small output ripple in ULV mode. The conceptof the proposed design is discussed in Section II. Section III

M01Vbp1

Vref

Rf1

Rf2

Vbn1

Vbn2

MP

Charge pump

M02A M02B

M03 M04

M05

M06

M07

M08

M09

M11

M12A

M21A

M31A

M32 M33 MN

Cm1Cm

RA RB

Rf3

Rf4

Vbp2

Vdd

Vllgs

Vset

Vout

Vfb1

Vfb2

Vcpin

M12B

M21B

M22A

M23A

M22B

M23B

M31B

gm2

gm3

gmp

gmn

gm1

Lightweight Local Generated Supply Error amplifier Power stage

Input pair First stage Second stage

Fig. 2. Schematic of the proposed LLGS assisted analog LDO.

presents the experiment results. And Section IV draws theconclusion.

II. PROPOSED LLGS ASSISTED ANALOG LDO

A. Operating Principles

The main limitation that prevents the traditional analogLDO from operating in ULV mode is that the error amplifiercannot function properly when the supply becomes too low.As a result, the output voltage may experience large under-shoot/overshoot and require a long time to recover duringload changes, worse still, the total feedback loop even failto operate at all. Therefore, an effective approach to extendthe operating region of the analog LDO into ULV region is togenerate a high voltage local supply with the ultra-low globalsupply Vdd. The structure of the proposed LDO is shown inFig. 1 (d). Contrary to the traditional analog LDO in whichthe supplies of the error amplifier and the power stage areprovided by the same global supply Vdd, the error amplifieris powered by a lightweight local generated supply (LLGS)in the proposed structure. In ULV mode operation, the LLGSboost Vdd to a higher voltage Vllgs that is adequate for the erroramplifier, while the supply of the power stage is still providedby the global supply Vdd. Consequently, the dropout voltageof the proposed LDO can be kept small without deterioratingthe overall performances. Moreover, as the power stage of theproposed LDO is never fully turned on and the ripple of theLLGS would not be coupled to the output of the proposedLDO directly, it shows much better PSRR performance andsmaller ripple than the digital LDO at ULV mode. In addition,given that the error amplifier in an analog LDO has relaxedrequirements on speed and loading capability of the supply, theLLGS is more energy- and area-efficient than the additionalhigh-performance global supply solution. TABLE I comparesthe proposed LDO with the existing three structures. In short,

Vllgs

Vdd(a) (b)

1.21.00.80.60

0.9

1.0

CLK NCLK

Vcpin (input)

M1

M2

M3

M4C1

C2

C3

Vllgs (output)0

Vcpin

The capacitances for C1, C2, and C3 are 2.5pF, 6pF, and 2.5pF respectively, and all capacitors are integrated on-chip.

0Vcpin

Fig. 3. (a) Structure of the charge pump. (b) Monte Carlo simulation resultsof the relationship between Vdd and Vllgs.

the proposed structure can achieve high PSRR, small outputripple, and ULV mode operation simultaneously.

Another advantage of the proposed structure is that itremoves the constraint on the type of power transistors atULV mode. In traditional analog LDO, the power transistorcan only be PMOS because the large Vgs,power would resultin large dropout voltage of NMOS power transistor. In theproposed LDO, the gate voltage of the NMOS power transistoris independent with the supply of the power stage (Vdd) andcan be higher than that at ULV mode, so the dropout voltagecan be kept small even if there is a large Vgs,power. AlthoughPMOS power transistor is still selected for comparison, theability to drive the NMOS power stage with high efficiencyprovides new opportunities for future ULV LDO designs.

Fig. 2 shows the schematic of the proposed LDO. The

+

-

gm1

12Vin

gm1

12Vin

R1C1 R2C2

V11

V12

gm2V11

gm2V12

R1C1 R2C2

V21

V22 Cm

V3 Vout

R3C3 R4C4

-gm3V22

gm3V

21

gmpV3

gmnV12

Vin

Fig. 4. Small-signal model of the proposed LLGS assisted analog LDO.

error amplifier is a fully differential structure that showsgood transient performance without any additional complextransient boosting circuitry [11]. The common-mode feedbackresistors are 1.28 MΩ, and the compensation capacitors Cm1

and Cm are 0.08 pF and 0.2pF respectively. As the outputvoltage and feedback voltage will be very low at ULV mode,the input stage of the fully differential error amplifier shouldbe PMOS.

B. Lightweight Local Generated Supply

The function of LLGS is to provide an appropriate localsupply voltage for the error amplifier so that it can provideenough gain and regulate the LDO output to targeted value.When global supply becomes too low, it is feasible to generatethe local supply voltage with a charge pump. However, theconversion ratio of a charge pump is normally fixed, and theoutput voltage may be boosted too high as the input voltageof the charge pump increases. In other words, to generate anappropriate Vllgs in a wide supply range, the input of the chargepump needs to be insensitive to Vdd.

The structure of the proposed LLGS is shown in Fig. 2. Itmainly consists of a charge pump, a two-stage amplifier, and aregulating stage. The structure of the charge pump adopted inour design is shown in Fig. 3 (a) [12], the clock frequency forthe charge pump is 10 MHz,which is common in the clock treeof SoCs. The input of the charge pump is connected with theoutput of the regulating stage, and the conversion ratio of thecharge pump is 2. As the LLGS only serves as the supply ofthe error amplifier in the proposed LDO, the ripple introducedfrom the charge pump would have negligible influence onthe regulated output of the proposed LDO. Moreover, as theerror amplifier in LDO consumes little quiescent current, thesize of M09 in the regulating stage can be very small. Inour design, the input of the LLGS, Vset, equals to 250 mVand Rf1/Rf2 is set to be 1. When the global supply Vdd isa normal value, for instance, 1 V, the two-stage amplifier andthe regulating stage in LLGS form an effective regulation loop,

@Vdd = 0.6V,Iload = 100µA@Vdd = 0.6V,Iload = 100mA

@Vdd = 1.0V,Iload = 100mA@Vdd = 1.0V,Iload = 100µA

Gai

n (d

B)Ph

ase

(deg

ree)

0

20

40

60

-2010 100 1k 10k 100k 1M 10M

10 100 1k 10k 100k 1M 10M

160°

120°

80°

40°

@Vdd = 0.6V,Iload = 100µA@Vdd = 0.6V,Iload = 100mA

@Vdd = 1.0V,Iload = 100mA@Vdd = 1.0V,Iload = 100µA

Fig. 5. Simulated frequency responses of the proposed LLGS assisted analogLDO structure at different supply voltages and loading current.

and the input voltage of the charge pump is regulated to around2Vset, or 500 mV. Consequently, the local generated supplyvoltage Vllgs is approximately 1 V, which is sufficiently highfor the error amplifier in LDO to function properly. When theglobal supply Vdd is a ULV value, although the regulationloop in LLGS is not as strong as in the normal condition,the input voltage of the charge pump is still regulated toaround 500 mV in spite of errors, hence the LLGS can stillprovide a reliable supply to the error amplifier of LDO in thiscondition. Fig. 3 (b) shows the Monte Carlo simulation resultsof the relationship between Vdd and Vllgs, although Vllgs variesslightly at different global supply voltages, as long as Vllgs issufficiently high, the absolute value of Vllgs has little influenceon the overall performances.

C. Small-Signal Analysis

The open-loop small-signal model of the proposed LDOstructure is shown in Fig. 4. The LLGS is ignored in the small-signal model as it only serves as a supply. For convenience,it is also assumed that the operating points of M31A andM31B are identical in the error amplifier. gmi (i = 1, 2, 3), gmp,and gmn are the transconductance of the input pair, the firststage amplifier, the second stage amplifier, the power transistorand the MN. Ci and Ri (i = 1, 2, 3, 4) are the correspondingsmall-signal resistors and capacitors at the input pair, thefirst stage, the second stage, and the power stage. Cm is thecompensation capacitor. The following assumptions have beenmade to simplify the open-loop transfer function:

a) Poles at each stage are far away from each other.b) Parasitic capacitors are much smaller than the compen-

sation capacitor and the output capacitor.Equation (1) shows the open-loop transfer function of the

proposed LDO. According to (1), the DC gain of the proposed

H(s) =vOvi

≈gm1gm2gm3gmpR1R2R3R4

(1 + 1

2 sR1Cm

)(1 + sgm2gm3gmpR1R2R3R4Cm) (1 + sR1C1) [1 + s(R2C2 + R3C3)]

(1 + s C4

gm2gm3gmpR2R3

) (1)

PAD

PADPAD

PAD

PAD

PAD

PAD

PAD

PAD

LLGSanalog LDO

140µm

420µm

60µm

125µm

Fig. 6. Microphotograph of the proposed LLGS assisted analog LDO.

LDO is given by the product of the gain of the input pair, firststage amplifier, second stage amplifier, and the power stage.And it presents four poles and one left-half-plane zero:

p0 =1

gm2gm3gmpR1R2R3R4Cm(2)

p1 =1

R2C2 + R3C3(3)

p2 =1

R1C1(4)

p3 =gm2gm3gmpR2R3

C4(5)

z0 =2

R1Cm(6)

Since the value of gmp and R4 change dramatically indifferent load conditions, the location of different poles willalso vary. We must consider different cases when analyzingthe stability of the proposed LDO structure. Fig. 5 showsthe simulated frequency responses of the proposed LDOstructure when Vdd = 0.6 V(1.0 V), Vout = 0.5 V(0.9 V), andthe maximum and minimum loading current are 100µA and100 mA respectively. It is observed that the stability of heavyload is more difficult to achieve than the light load. Accordingto Fig. 5, the phase margin in all conditions are around 80,indicating that the proposed LDO can be stable in ULV modeduring the whole dynamic range and load range with theassistance of the proposed LLGS structure.

III. EXPERIMENTAL RESULTS

The proposed LDO structure has been fabricated in standard0.13µm CMOS technology. Fig. 6 is the chip micrograph,which shows an active area of 0.035 mm2.

Fig. 7 (a) shows the measured PSRR performance of theproposed LDO at 100 mA load current. The injected supplyripple is 10 kHz and 100 mV, and the measured output rippleis less than 2.7 mV. Fig. 7 (b) shows the measured PSRRperformances across the entire frequency range when loadcurrent is 1 mA and 100 mA, both conditions indicate thatthe proposed LDO achieves PSRR greater than 30 dB up to10 kHz at 0.5 V. Fig. 8 shows the line regulation response

500

480

460

440

520

540

560(mV)

398

397

399

400

401(mV)

396

420

100µs

100µsVdd

Vout

100mV

1ms 1.1ms 1.2ms900µs800µs

1ms 1.1ms 1.2ms900µs800µs

2.7mV

1mA100mA

(dB)

-5

-10

-15

-20

-25

-30

-35

-40

1mA100mA

10 100 1K 10K 100K 1M 10M

PSR

Frequency (Hz)

(a)

(b)

Fig. 7. Measured PSRR performance of the proposed analog assisted analogLDO in (a) time domain, and (b) frequency domain.

400

380

360

420

440

460

0

200

400

600

800

1000

1200

(mV)

(mV)

45ms 55ms 65ms 75ms 85ms

45ms 55ms 65ms 75ms 85ms

95ms

95ms

700mV

17mV

100ns

10ms

10ms20mV

200mVVdd

Vout

Fig. 8. Measured line regulation of the proposed LLGS assisted analog LDO.

of the proposed LDO structure when the output voltage is400 mV and load current is 100 mA. The output of the LDOonly changes 17 mV when Vdd changes from 0.5 V to 1.2 V,and the line regulation is 24.8µV/mV.

The transient response of the proposed LDO when Vdd= 1.2 V is shown in Fig. 9. As the supply voltages for theerror amplifier and the power stage are both sufficiently high,the transient response of the proposed LDO is similar to thetraditional analog LDO structure. According to Fig. 9, theundershoot/overshoot are 42 mV and 31 mV respectively whenthe load current change between 100µA and 100 mA. Fig. 10shows the transient response of the proposed LDO when Vdd= 0.5 V. As the proposed LLGS structure can still providea Vllgs close to 1V in this condition, the error amplifier inthe proposed LDO still shows a relatively good performance.According to Fig. 10, the undershoot/overshoot at the output

1.08

1.06

1.10

-150

-100

-50

0

100

(mA)

(V)

5µs 10µs 15µs 20µs 25µs 30µs

5µs 10µs 15µs 20µs 25µs 30µs

50

150

1.12

1.14

1.16

42mV

31mV

100µA~100mA

500ns300ns

5µs

5µs50mA

20mV

Vout

Iload

Fig. 9. Measured transient response of the proposed LLGS assisted analogLDO when Vdd = 1.2 V.

[2] 2010 CICC

[5] 2017 JSSC

[6] 2017 JSSC

[8] 2014 JSSC

[10] 2017 ISSCC

This Work

Structure DLDO DLDO DLDO DLDO ALDOLLGS

Assisted ALDO

Technology (nm) 65 65 28 32 65 130

VIN (V) 0.5 0.6-1.0 1.1 0.7-1.0 0.2 0.5-1.2

VOUT (V) 0.45 0.55-0.95 0.9 0.5-0.9 0.05-0.15 0.4-1.1

IOUTMAX (mA) 0.2 500 200 5 0.1 100

COUT (nF) 100 1.5 23.5 N.A. 0.04 0.05

Edge time ∆t (ns) N.A. 2 400 10 10000 300

∆IOUT(mA) 0.2 100 180 0.8 0.05 100

∆VOUT(mV) 40 50 120 150 34.8 89

IQ(µA) 2.7 300 110 92 0.41 21

Load reg. (mV/mA) 0.65 0.25 0.57(1) N.A. N.A. 0.15

Active area(mm2) 0.072 0.158 0.021 0.070 (1) 0.016 0.035

PSRR@10kHz(dB) N.A. 20 N.A. N.A. 22.9 30

FoM (2) (ps) 270000 2.3 7.75 184 228.3 0.009

(1) Estimated from figure or content.

(2) FoM = (COUT × ∆VOUT × IQ) / I2 MAX [5].

TABLE IICOMPARISON OF RESULTS

are 89 mV and 40 mV respectively in this condition. TABLE IIsummarizes the performances of the proposed LDO structureand other recent published LDO structures. Compared withother designs, the proposed design shows a good figure ofmerit (FoM) and much better PSRR performance.

IV. CONCLUSION

An analog LDO structure that can operate at ultra-lowsupply voltage with good PSRR performance has been pro-posed and experimentally verified. With the assistance of theproposed LLGS structure, the proposed LDO can achievegreater than 30 dB PSRR up to 10 kHz at supply voltage aslow as 0.5 V. In addition, the proposed LLGS structure can

350

300

400

-150

-100

-50

0

100

(mA)

(mV)

5µs 10µs 15µs 20µs 25µs

50

150

450

500

550

5µs 10µs 15µs 20µs 25µs

89mV40mV

100µA~100mA

500ns300ns

5µs

5µs

50mV

50mA

Vout

Iload

Fig. 10. Measured transient response of the proposed LLGS assisted analogLDO when Vdd = 0.5 V.

be further optimized to save the chip area. Furthermore, thisapproach is general, and the LLGS structure can be combinedwith existing analog LDOs to form LLGS assisted analogLDOs, which have extended supply voltage range. For ULVapplications, LLGS assisted analog LDOs provide an attractivealternative to digital LDOs with enhanced PSRR performance.

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