99-1 Under-Graduate Project Design of Datapath Controllers

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Graduate Institute of Electronics Engineering, NTU

99-1 Under-Graduate Project99-1 Under-Graduate ProjectDesign of Datapath ControllersDesign of Datapath Controllers

Speaker: Shao-Wei FengAdviser: Prof. An-Yeu Wu

Date: 2010/10/14

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P. 2

OutlineOutlineSequential Circuit ModelFinite State MachinesUseful Modeling Techniques


P. 3

Model of Sequential CircuitsModel of Sequential Circuits System outputs depend not only on current input

Depend on inputs Depend on current state

Fundamental components Combinational circuits Memory elements

CombinationalLogic

Memory Elements

Inputs Outputs

NextState

CurrentState

clock


P. 4

Types of Memory ElementsTypes of Memory ElementsFlip-FlopLatchRegistersOthers

Register FilesCache Flash memoryROMRAM


P. 5

D-FF vs. D-Latch D-FF vs. D-Latch FF is edge sensitive (can be either positive or negative edge)

At trigger edge of clock, input transferred to output Latch is level sensitive(can be either active-high or active-low)

When clock is active, input passes to output (transparent) When clock is not active, output stays unchanged

D Q FFclk

in out D Q

E clk

in out

clk

in

out

Latch

clk

in

out


P. 6

FF Based, Edge Trigger ClockingFF Based, Edge Trigger Clocking Td = delay of combinational logic

Tcycle = cycle time of clock Duty cycle does not matter

Timing requirements for Td

Tdmax < Tcycle –Tsetup – Tcq no setup time violation

Tdmin > Thold – Tcq no hold time violation

FF FF

clkTcycle

CombinationalLogic Td

Tcq Td Tsetup


P. 7

Latch Based, Single Phase ClockingLatch Based, Single Phase Clocking Pulse Mode clocking Tcycle = cycle time of clock; Tw = pulse width of clock

Timing requirements for Td

Tdmax < Tcycle –Tdq data latched correctly

Tdmin > Tw – Tdq no racing through next stage

clk

CombinationalLogic Td

LatchLatch

Tcycle

Tdq Td

Tw


P. 8

Comparison Comparison Flip-Flop Based

− Larger in area− Larger clocking overhead (Tsetup, Tcq) Design more robust Only have to worry about Tdmax

Tdmin usually small, can be easily fixed by buffer Pulse width does not matter

Latch Based Single Phase Smaller area Smaller clocking overhead ( only Tdq)

− Worry about both Tdmax and Tdmin

− Pulse width does matter (unfortunately, pulse width can vary on chip)


P. 9

D Flip-Flop with Positive-Edge ClockD Flip-Flop with Positive-Edge Clock

module flop (Q, D, C, S, R); output Q; // Flip-Flop Output input D; // Data Input input C; // Positive Edge Clock input E; // Clock Enable reg Q; // Register Type

always @(posedge C) begin if (E) // Check Enable Q <= D; end endmodule

D Q

C

D Q

CE


P. 10

D Flip-Flop with Positive-Edge ClockD Flip-Flop with Positive-Edge Clockmodule flop (Q, D, C, S, R); output Q; // Flip-Flop Output input D; // Data Input input C; // Positive Edge Clock input R; // Asynchronous Reset input S; // synchronous Set reg Q; // Register Type

always @(posedge C or negedge R) begin if (!R) Q <= 1’b0; else if (S) Q <= 1’b1; else Q <= D; end endmodule

D Q

C

S

R


P. 11

Latch IssueLatch Issue Latches are to be avoided in most designs!

Prone to timing violations and glitchesCannot implement synchronous operations

Common mistakes that generate latchesalways@( a or b ) begin if( a == 2’d0 ) z = 1’b0; else if( a == 2’d1 ) z = ~b; else if( a == 2’d2 ) z = b; // no else statement!end

always@( a or b ) begin case( a ) 2’d0: z = b; 2’d1: z = ~b; 2’d2: z = c; // no default statement! endcaseend always@( /*forget edge!*/ clk )

begin z <= b;end

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Finite State Machine Finite State Machine


P. 13

What is FSMWhat is FSM A model of computation consisting of

a set of states, (limited number) a start state, input symbols, a transition function that maps input symbols and current states

to a next state.


P. 14

Elements of FSMElements of FSM Memory Elements (ME)

Memorize Current States (CS) Usually consist of FF or latch N-bit FF have 2n possible states

Next-state Logic (NL) Combinational Logic Produce next state

Based on current state (CS) and input (X)

Output Logic (OL) Combinational Logic Produce outputs (Z)

Based on current state Based on current state and input


P. 15

Mealy MachineMealy Machine Output (Z) is function of both

Input (X) Current state (CS)


P. 16

Moore MachineMoore Machine Output(Z) is function of

Current state (CS) only


P. 17

Mealy Finite State Machine Mealy Finite State Machine A serially-transmitted BCD (8421 code) word is to be converted into an Excess-3 code. An Excess-3 code word is obtained by adding 3 to the decimal value and taking the binary equivalent. Excess-3 code is self-complementing [Wakerly, p. 80], i.e. the 9's complement of a code word is obtained by complementing the bits of the word.

D ecim al 8-4-2-1 E xcess-3D igit C ode C ode

(B C D )

0 0000 00111 0001 01002 0010 01013 0011 01104 0100 01115 0101 10006 0110 10017 0111 10108 1000 10119 1001 1100

E xcess-3C ode

C onverte r

c lk

B out = 8 Excess-3

1 0 0 0+

1 1 10

B in = 8 bcd

B out

0 0 1 1

1 0 1 1

LSBM SB

0 0 0 1

t

LSB M SB

t

M SB

B in


P. 18

Mealy Finite State Machine Mealy Finite State Machine

The vertices of the state transition graph of a Mealy machine are labeled with the states. The branches are labeled with (1) the input that causes a transition to the indicated next state, and

(2) with the output that is asserted in the present state for that input. The state transition is synchronized to a clock. The state table summarizes the machine's behavior in tabular format.

The serial code converter is described by the state transition graph of a Mealy FSM.

S _5

S _0

inpu t / ou tpu t

1 /00 /1

0 /1

0 /0 , 1 /1

1 /0

0 /11 /0

0 /10 /0 , 1 /1

0 /0 , 1 /1

S _1 S _2

S _4S _3

S _6

State Transition Graph

sta tenext sta te /ou tput

input0 1

S _0 S _1 / 1 S _2 / 0S _1 S _3 / 1 S _4 / 0S _2 S _4 / 0 S _4 / 1S _3 S _5 / 0 S _5 / 1S _4 S _5 / 1 S _6 / 0S _5 S _0 / 0 S _0 / 1S _6 S _0 / 1 - / -

N ext S ta te /O utputTab le


P. 19

Design of a Mealy Finite State MachineDesign of a Mealy Finite State MachineTo design a D-type flip-flop realization of a FSM having the behavior described by a state transition graph, (1) select a state code, (2) encode the state table, (3) develop Boolean equations describing the input of a D-type flip-flop, and (4) using K-maps, optimize the Boolean equations.

sta tenext sta te /output

input0 1

S_0 S_1 / 1 S_2 / 0S_1 S_3 / 1 S_4 / 0S_2 S_4 / 0 S_4 / 1S_3 S_5 / 0 S_5 / 1S_4 S_5 / 1 S_6 / 0S_5 S_0 / 0 S_0 / 1S_6 S_0 / 1 - / -

N ext S ta te /O utput Tab le

1

0 1

q0

S _0

S _6 S _4

S _2

S _5 S _31

1 0

0 1

0 0

q2 q1

S _1

S ta te A ssigm ent q2 q1 q0 q2+ q1

+ q0+

input

0 1

sta te next sta te output

input

0 1

S _0 000 001 101 1 0

001 111 011 1 0

101 011 011 0 1

111 110 110 0 1

011 110 010 1 0

110 000 000 0 1

010 000 - 1 -

100 - - - -

S _1

S _2

S _3

S _4

S _5

S _6

E ncoded N ext sta te / O utput Tab le


P. 20

Design of a Mealy Finite State MachineDesign of a Mealy Finite State Machine

q2 q1

00

10

11

01

00 01 11 10

1q2 q1

q0 B in

1 1 1

0 0 0

0 0 0 0

x x 1 1

0

q0+ = q1 '

S_0 S_0 S_1 S_1

S_6 S_6 S_4 S_4

S_5 S_5 S_3 S_3

S_2 S_2

00

10

11

01

00 01 11 10

0q2 q1

q0 B in

0 1 1

0 1 1

0 0 1 1

x x 1 1

0

q1+ = q 0

S_0 S_0 S_1 S_1

S_6 S_6 S_4 S_4

S_5 S_5 S_3 S_3

S_2 S_2

00

10

11

01

00 01 11 10

1

q0 B in

0 0 1

1 0 1

0 1 1 0

x x 1 0

0

B out = q 2 'B in ' + q 2B in

S_0 S_0 S_1 S_1

S_6 S_6 S_4 S_4

S_5 S_5 S_3 S_3

S_2 S_2

00

10

11

01

00 01 11 10

0q2 q1

q0 B in

1 0 1

0 0 1

0 0 1 1

x x 0 0

0S_0 S_0

q2+ = q 1 'q 0 'B in + q 2 'q 0B in ' + q 2q1q0

S_1 S_1

S_6 S_6 S_4 S_4

S_5 S_5 S_3 S_3

S_2 S_2

q2+ = q1 'q0 'B in + q2 'q0B in ' + q 2q1q0

q2+ = q1 'q0 'B in + q2 'q0B in ' + q 2q1q0

q2+ = q1 'q0 'B in q2 'q0B in ' q 2q1q0

q2+ = q1 'q0 'B in q2 'q0B in ' q 2q1q0

Note: We will optimize the equations individually. In general - this does not necessarily produce the optimal (area, speed) realization of the logic. We'll address this when we consider synthesis.


P. 21

Design of a Mealy Finite State MachineDesign of a Mealy Finite State MachineRealization of the sequential BCD-to-Excess-3 code converter (Mealy machine):

q 1 'q 0 '

q 2 'q 0

q 0q 1q 2

D

Q

Q

D

Q

Q

D

Q

Q

B out

B in

clk

q 2 '

q 2

q 1 '

q 1

q 0

q 0 '

q 1 '

q 0

B in

B in 'B in '

q2+ = q1 'q0 'B in + q2 'q0B in ' + q2q1q0

q2+ = q1 'q0 'B in + q2 'q0B in ' + q2q1q0

q2+ = q1 'q0 'B in q2 'q0B in ' q2q1q0

q2+ = q1 'q0 'B in q2 'q0B in ' q2q1q0


P. 22

Design of a Mealy Finite State MachineDesign of a Mealy Finite State Machine

0 10 0

1 11 0

B_in

B_out

Simulation results for Mealy machine:

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Building Behavioral ModelsBuilding Behavioral Models


P. 24

Modeling FSM in VerilogModeling FSM in Verilog Sequential Circuits

Memory elements of States (CS)

Combinational Circuits Next-state Logic (NL) Output Logic (OL)

Three coding styles (1) Separate CS, OL and NL (2) Combines NL+ OL, separate CS (3) Combine CS + NL, separate OL


P. 25

Coding Style 1 – Separate CS, NL, OLCoding Style 1 – Separate CS, NL, OL

CS

NL

OL


P. 26

Coding Style 2 – Coding Style 2 – Combine NL+OL; Separate CSCombine NL+OL; Separate CS

CS

NL+OL


P. 27

Coding Style 3 – Coding Style 3 – Combine CS+NL; Separate OLCombine CS+NL; Separate OL

CS+NL

OL


P. 28

State EncodingState Encoding


P. 29

lowspeed

stopped

mediumspeed

highspeed

brake =1

brake =0acce le ra tor=1

brake =1

brake=0

accelerator=1

brake =1

brake =1 brake =0acce le ra tor=1

brake =0acce le ra tor=1

brake

acce le ra tor

c lock

spe e d

Behavioral Models of FSMBehavioral Models of FSM Example: Speed Machine Example: Speed Machine


P. 30

FSM Architecture ModelingFSM Architecture Modeling

Coding style 2Coding style 2 fits this architecture very well!

Build combinational and sequential parts separately!


P. 31

Verilog Sample Code Verilog Sample Code (using coding style 2)(using coding style 2)


Gate-Level Simulation Gate-Level Simulation of the Speed Machineof the Speed Machine

P. 32


P. 33

Conclusion Conclusion FSM Design

Partition FSM and non-FSM logicPartition combinational part and sequential partUse parameter to define names of the state vectorAssign a default (reset) state

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99-1 Under-Graduate Project Design of Datapath Controllers