Datapath Design

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session 7. Datapath Design

Cesar Llorente1

General Objective:

Determine the hardware requirement o a digital computerbased on its instruction set.

!peciic Objectives:

Describe the general concepts in designing the data path o adigital computer rom its instruction set.

Design the data processing elements such as the arithmetic circuits" counters and registers. Design data routing circuits that transport data to various

processing elements. Draw the interconnections o the various elements.


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Mnemonic OpCode Description

LDA 0000 Load ACC with the contents of the memory specified

address.

ADD 0001 Add the contents of the ACC with the contents of the Bregister and place the result in the ACC.

SB 0010 SBtract the contents of the B register from the ACC and

store the result in the ACC.

O! 0011 O!put he contents of the ACC to the O!" register.

#L! 1111 #alt or stop MSA$.

$nstruction !et

$nstruction %ormat

D% D& D' D( D) D* D1 D0

O$COD+ O$+"A,D

General concepts in designing the data path o a digital computerrom its instruction set.


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'(tracting hardware requirements rom the $nstruction !et

1. !tarting with the arithmetic instructions" )DD and !*+"

)DD ,-address and !*+ ,-address which mean add /subtract0 the contents o thememor speciied in the instruction rom the contents o the accumulator and storethe results to the accumulator. !mbolicall"

)CC 23 )CC 4 ,-address or )CC 23 )CC 5 ,-address

one addend /minuend0 is alread in the )CC" while the other addend /subtrahendis ound in the memor. $t is tpical that the data read rom the memor is stored ina temporar register. 6his will lead to a coniguration below

)CC

6,8

4

)CC

6,8

5


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combining the add and subtract operations"

)CC

6,8

45

su

6he addition or subtraction operation is selected b su.;hen su 3


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#. ,emor Operation. Data manipulated b the arithmetic operations are stored

in the memor. )ccessing the memor requires two signals the address signal which speciies the location o the data in the memor" and the rd control signal which speciies the e(act time data is outputted b the memor.

6he address must be constantl applied to the memor during the entire memorread ccle. 6his necessitates the use o a register to hold the address" thus it isnamed the ,emor )ddress >egister /,)>0.6he si?e o ,)> is equal to the

number o address bits. !mbolicall" memor read operation is represented as"

rd : >'G 23 ,-,)>

,emor *nit/#@( ,

)ddress

Data out

rd

,

@,)>

>'G


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9. %etch Ccle and Operand %etchDuring the OpCode %etch" the instruction code is read rom memor and then stored in aspecial register called as the $nstruction >egister /$>0.

During the operand etch" the address o the operand is stored in ,)> in preparationto read the data rom memor. Generall" data read rom memor during operand etchis stored in a general purpose register /e(ample" the )CCumulator register0.

,emor *nit/#@( ,0

)ddress

Data out

rd

,

@,)>

8C

$>

,emor *nit/#@( ,0

)ddress

Data out

rd

,

@,)>

8C

)CC


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=. 6o support Data 6ranser Operations" registers should have the capabilit to

receive data in parallel /parallel load0. 6he load control input when activeenables the data at the data inputs to be loaded in parallel on the ne(t clocB pulse.

Din Load clB

Dout


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A. Data 6ranser Operations. 6o support instructions that moves data between registers

/to support arithmetic operations0" various registers must be organi?ed /interconnected0to acilitate the transer o data. Data >outing Circuits" route data rom source registersto the inputs o all registers. !ource registers are selected b multiple(ers and thetarget register is selected b a decoder.

>egeg1

>eg#

>eg@

eset


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1&

Combinational@etworB

,emor/!tate0

Control *nit Datapath

General 8urpose 8rocessor

$nstruction !et )rchitectureComple( $nstruction !et ComputerDirect )ddressing ,ode

>eset


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session 7. Datapath Design/General Data 8rocessor0: %etch Ccle

Cesar Llorente

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,emor/!tate0


$>

>eset

,emor

8C


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session 7. Datapath Design/General Data 8rocessor0 : '(ecute Ccle

Cesar Llorente

1=


,emor/!tate0


$>

>eset

,emor

8C

)CC

6,8 45

su8rocessing'lements


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session 7. Datapath Design/General Data 8rocessor0 : '(ecute Ccle

Cesar Llorente

1A


,emor/!tate0


$>

>eset

,emor

8C

)CC

6,8 45

su8rocessing'lements

Data>outingcircuits


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1

!imple )s 8ossible Computer /!)80

MEMORY


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1E

!imple )s 8ossible Computer /!)80

FetchCycle

Elements


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#ead Onl ,emor


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#=

,emor )ddress >egister


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#A

# 5 1 ,*L6$8L''>


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#7

)L* 5)rithmetic Logic *nit


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#

)dder!ubtractor Circuit


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5+$6 >'G$!6'> 6$,$@G


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session 7 Datapath Design


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clrpc incpc desSel srcSel rd su Micro operations Description

1 0 000- 000- 0 0 $C . 0 CL+A" $C or reset

0 0 000- 000- 0 0 MA" . $C $C to MA"

0 0 100- 001- 1 0 /" . MMA" M+MO"2 !O /" 3opcode fetch4

0 1 000- 000- 0 0 $C . $C 5 1 /,Crement $C

0 0 000- 101 0 0 MA" . /")60 /" !O MA" !ransfer operand

0 0 001- 001- 1 0 A . MMA" M+Mory to ACC memory read to A

0 0 010- 001- 1 0 B . MMA" M+Mory to B memory read to B

0 0 001- 100- 0 0 A . A 5 B AL to ACC 3addition4

0 0 001- 100- 0 1 A . A 7 B AL to ACC 3su8traction4

0 0 011- 010- 0 0 O!" . A ACC to O!"

session 7 Datapath Design


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clrpc incpc desSel srcSel rd su Hexcode Micro operations

"+S+!

1 0 000- 000- 0 0 *00 $C 0

9etch Cycle

0 0 000- 000- 0 0 000- MA" $C

0 1 100- 001- 1 0 1:& /" MMA"; $C $C 5 1

LDA

0 0 000- 101 0 0 010- MA" /")60

0 0 001- 001- 1 0 0*&- A MMA"; goto 9etch

ADD

0 0 000- 101 0 0 010- MA" /")60

0 0 010- 001- 1 0 0(&- B MMA"

0 0 001- 100- 0 0 0)0- A A 5 B; goto 9etch

SB

0 0 000- 101 0 0 010- MA" /")60

0 0 010- 001- 1 0 0(&- B MMA"

0 0 001- 100- 0 1 0)1- A A 7 B; goto 9etch

O!

0 0 011- 010- 0 0 0&:- O!" A; goto 9etch

#L!

0 0 000- 000- 0 0 000- enstate 0


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Datapath Design