970 IEEE ELECTRON DEVICE LETTERS, VOL. 37, NO. 8, AUGUST 2016

Ultra-High Aspect Ratio InP Junctionless FinFETsby a Novel Wet Etching Method

Yi Song, Parsian K. Mohseni, Seung Hyun Kim, Jae Cheol Shin, Tatsumi Ishihara,Ilesanmi Adesida, Fellow, IEEE, and Xiuling Li, Senior Member, IEEE

Abstract— Junctionless FinFETs with an array of ultra-highaspect ratio (HAR) fins, enabled by inverse metal-assisted chem-ical etching, are developed to achieve high on-current per fin. Thenovel device fabrication process eliminates dry etching-inducedplasma damage, high energy ion implantation damage, andsubsequent high-temperature annealing thermal budget, ensuringinterface quality between the high-k gate dielectric and the HARfin channel. Indium phosphide junctionless FinFETs, of recordHAR (as high as 50:1) fins, are demonstrated for the first timewith excellent subthreshold slope (63 mV/dec) and ON/OFF ratio(3 × 105).

Index Terms— FinFET, high aspect ratio, metal-assisted chem-ical etching, junctionless, interface states, nanofabrication.

I. INTRODUCTION

F inFET, which uses a double or tri-gate surrounding thefin channel to enhance gate electrostatic control over the

channel, has become the mainstream technology for state-of-art transistor scaling [1]. Significant challenges remain inmeeting the aggressively demanding dimensional and perfor-mance requirements for future generations beyond the 14 or 10nm node using FinFETs [2]. Dry etching-induced surface dam-age and its non-vertical profile are some of the most seriousproblems for multigate FinFETs, especially for post-Si CMOStechnologies using high mobility III-V compound semicon-ductors [3], [4]. In addition, in aggressively scaled CMOScircuits, the effect of interconnections is getting more and morepronounced since the transistor is getting smaller and morecrowded such that RC delay associated with the increasednumber of interconnection layers increases [5]. Therefore, aneven stronger demand for high drive current per unit area isrequired in order to compensate for the interconnection delay.

Manuscript received May 23, 2016; accepted June 2, 2016. Date ofpublication June 6, 2016; date of current version July 22, 2016. This workwas supported in part by the National Science Foundation through the Civil,Mechanical and Manufacturing Innovation under Grant 14-62946 and in partby the International Institute for Carbon-Neutral Energy Research and a giftfrom Lam Research Corporation. The review of this letter was arranged byEditor S. Hall. (Corresponding author: Xiuling Li.)

Y. Song, S. H. Kim, and I. Adesida are with the Micro and NanotechnologyLaboratory, Department of Electrical and Computer Engineering, Universityof Illinois at Urbana–Champaign, Urbana, IL 61801 USA.

P. K. Mohseni was with the Micro and Nanotechnology Laboratory, Univer-sity of Illinois, Urbana, IL 61801 USA, and is currently with the RochesterInstitute of Technology, Rochester, NY 14623 USA.

J. C. Shin is with Yeungnam University, Gyeongsan 712-749, South Korea.T. Ishihara is with the International Institute for Carbon-Neutral Energy

Research (I2CNER), Kyushu University, Fukuoka 819-0395, Japan.X. Li is with the Micro and Nanotechnology Laboratory, Department

of Electrical and Computer Engineering, University of Illinois at Urbana–Champaign, Urbana, IL 61801 USA, and also affiliated with the I2CNER,Kyushu University, Fukuoka 819-0395, Japan (e-mail: xiuling@illinois.edu).

Color versions of one or more of the figures in this letter are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/LED.2016.2577046

One can use multiple planar channels stacked in the ver-tical direction [6], [7] or densely packed vertical nanowirechannels [8] to increase current density per chip surface area.Both of these device geometries obviously require compli-cated growth or process flows and faces poor uniformityissues. Ultra-high aspect ratio (HAR) FinFET is a morestraightforward way to boost current density for a givensurface area. However, it is extremely challenging to fabricateconventional inversion-mode FinFETs of ultra-HARs. Thisis because deep source and drain (S/D) doping profiles inultra-HAR FinFETs would require deep implantation thatis normally achieved with high energy ions and subsequenthigh temperature annealing. These steps can potentially createirreversible severe crystal damage and high thermal budget-related compatibility issues. In addition, doping uniformitywould be difficult to control over the entire depth. Also,scaling the channel length while preventing S/D punch-throughthroughout the depth direction is nearly impossible due to thedeep S/D junction. To avoid these difficulties, the junctionlesstransistor structure [9]–[11] which does not require lateralp-n junctions, should be used for ultra-HAR FinFETs.

In this letter, we demonstrate extremely HAR (as highas 50:1) junctionless InP FinFETs with near-ideal subthresholdslope (63 mV/dec) and on/off current ratio of 3 × 105,enabled by a novel wet etching method, inverse metal-assistedchemical etching (i-MacEtch), for the first time. This demon-stration confirms that, beyond channel length scaling, ultra-HAR FinFETs are a feasible route to deliver high current whilemaintaining excellent gate electrostatic control.

II. DEVICE FABRICATION

Fig. 1 presents a schematic view of the process flow for fab-ricating a HAR InP FinFET. A 600 nm thick InP epitaxial layer(n type, Si-doped, 8×1017 cm−3) was first grown by MOCVDon a semi-insulating InP substrate (Fig. 1(a)). The device areawas defined by e-beam lithography patterning into parallelstripe openings, followed by a 30-nm Au layer deposition bye-beam evaporation and subsequent lift-off process to form theAu strips on top of the substrate (Fig. 1(b)). This was followedby the i-MacEtch [12], [13] process to form the InP fins inFig. 1(c), where Au served as the catalyst to initiate the localelectrochemical etching of InP in the solution of H2SO4 andH2O2. In contrast to conventional forward MacEtch [14], [15],Au was employed here as a catalytic mask to induce mater-ial dissolution starting from the off-metal areas, instead ofdirectly underneath the metal. In this manner, time-controlledetching allowed for the formation of localized nanofin arraystructures, predefined by the location of Au catalyst patterns.The S/D region was intentionally made wider than the channelregion to reduce parasitic resistance by simply modifying themetal pattern layout, which is an inherent merit of i-MacEtch.

0741-3106 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

SONG et al.: ULTRA-HAR InP JUNCTIONLESS FinFETs 971

Fig. 1. Schematic diagram and the corresponding description of the process flow (a)-(g) for the fabrication of an InP junctionless-MOSFET by i-MacEtch.

Fig. 2. Structure characterization: (a) 45° tilted-view SEM image of anarray of InP fins. (b) Titled top-view SEM image of a fully-fabricated devicewith 14 fins. (c) 52° tilted-view SEM image showing the cross-section of a14 nm wide 700 nm tall InP fin with Al2O3 high-k and Ti/Au metal gate.(d) HR-TEM image showing the smooth sidewall after i-MacEtch.

After the doped epitaxial layer (600 nm) was reached, an inten-tional over etching (100 nm) into the insulating substrate wasdone to ensure that the fin channel was fully isolated fromthe substrate. The etching process was performed at roomtemperature effectively prohibited gold from diffusion into InP.After etching, Au was removed (Fig. 1(d)) by standard Auetchants (TFA, Transene Co.) without attacking InP.

After a dilute HF dipping, surface passivation was firstperformed in dilute (NH4)2S solution, then the samples wereimmediately loaded into an ALD chamber for Al2O3 gatedielectric (∼9 nm) deposition, followed by a 30 s RTA at500 °C (Fig. 1(e)). In order to fully wrap the metal contactsover the high-AR InP fins, tilted sputtering of Ge/Au/Ni/Au forsource/drain (S/D) pads (Fig. 1(f)), and Ti/Au (10 nm/100 nm)for the gate metal (Fig. 1(g)) were employed. Before gatedeposition, the S/D contacts were annealed by RTA in N2 at400 °C for 30 s. Note that metal lift-off above the tall fins isvery challenging and for this work, only long channel deviceswere realized.

Fig. 2(a) shows the SEM image of an array of InP fins of∼20 nm in width and ∼700 nm in height. Fig. 2(b) showsthe corresponding titled top-view of a fully-fabricated InPFinFET structure showing the gate is well-aligned in the centerbetween the source and drain contacts. Fig. 2(c) shows thecross-sectional view of a single fin that is 14 nm wide at itsnarrowest part and 700 nm tall (AR of 50:1), surrounded by

Fig. 3. Measured transfer and output characteristics. (a) ID-Vgs semi-logcurves and (b) ID-Vds curves, of a representative device with Lg = 560 nm,Wfin = 20 nm, and Hfin = 600 nm. A sharp turn-on and well-behaved Ionsaturation are observed.

9 nm high-k Al2O3 and 10 nm Ti/100 nm Au gate metal.It can be seen that the gate stack is coated conformal to theentire fin, as a result of the isotropic deposition (Al2O3) byatomic layer deposition (ALD) and rotated sputtering of themetal layers (Ti/Au). In addition to being free of ion-induceddamages, unique to this i-MacEtch technique, the resultingsidewall etching profile is remarkably smooth and independentof the metal pattern edge roughness; this is in contrast toforward MacEtch where the etched sidewall morphology mir-rors the metal edge saw-tooth pattern [16]. This is crucial forfin to fin uniformity, reducing performance variations due tointerface unevenness and line width fluctuations [17]. A high-resolution transmission electron microscopy (HR-TEM)image of the sidewall of an InP nanofin fabricated byi-MacEtch is shown in Fig. 2(d), confirming its atomicallysmooth surface [12].

III. RESULTS AND DISCUSSION

Fig. 3(a) shows the measured transfer characteristics of anInP FinFET with gate length Lg = 560 nm, fin width W f in =20 nm, and active fin height H f in = 600 nm. The draincurrent, ID , is plotted as a function of gate-source voltage,Vgs , for drain-source voltage, VDS of 0.1, 0.5 and 1.0 V.Fig. 3(b) shows the output characteristics, where ID is plottedas a function of VDS, for the same device. There are 14 finsin each device. ID was normalized by the total perimetersof all fins, (number of fins) x (perimeter of a single fin).Note that the high negative threshold voltage, Vth , observedhere probably results from a combination of non-optimizedgate metal work function, relatively thick fin body (20 nm),and immobile trapped charges in high-k Al2O3. Nonetheless,the device exhibits sharp turn-on and well-behaved pinch-offcharacteristics with an on/off ratio of ∼3 × 105.

We first discuss the off-state performance. The total deviceleakage (∼0.01 – 0.1 nA/μm for VDS = 0.1 – 1 V) is

972 IEEE ELECTRON DEVICE LETTERS, VOL. 37, NO. 8, AUGUST 2016

Fig. 4. (a) Measured Subthreshold slope (left axis) and extractedlow-field electron mobility μ (right axis) vs. Wfin. (b) Threshold voltageVth (left axis) and on-state resistance Ron (right axis) vs. Wfin. All deviceshave Lg = 560 nm, EOT = 3.9 nm and active fin height Hfin = 600 nm.

at the same level of the substrate leakage (measured on abare substrate across two contact pads). The off-state currentremains constant with Vgs under all VDS, implying that thegate-induced barrier lowering is negligible. The measuredgate leakage is also quite small (∼1pA/μm2). This confirmsthat the main device leakage comes from the semi-insulatingsubstrate instead of the fin channels, manifesting the excellentgate electrostatic control of the structure. In addition, nohysteresis was observed in the ID/Vgs curves when sweepingVgs in opposite directions, implying few charge traps at theinterface between InP and the high-k dielectric.

Fig. 4(a) shows the minimal sub-threshold slope Ss atVDS = 0.1 V (left y-axis) and extracted field effect mobil-ity (right y-axis) as a function of the fin width, W f in .Ss decreases with W f in , as a result of increased gate electrosta-tic coupling. At W f in of 20 nm, Ss is ∼63 mV/dec, approach-ing the ideal value of 60 mV/dec. The estimated Dit is low at∼2.4 × 1011 cm−2eV−1, since Ss = (1 + q × A × Dit/Cox) ×60 mV/dec (A and Cox are the total gate area and gatecapacitance respectively). The extracted low field mobilityvalues, estimated from the flat-band I-V equation [9], are inthe range of 600-1000 cm2/V-s for these devices (W f in of20 - 60 nm), which is higher than the field effect mobilityof InP nanowires (200 – 500 cm2/V-s for 100 nm diameterundoped nanowires [18]) and approaching the measured bulkhall mobility (1780 cm2/V-s). The excellent off-state perfor-mance is a direct indication of high interface quality with lowmobile charge trap density between the fin channel surfaceand the high-k dielectric [19], [20], which is attributed to theatomically smooth and damage-free sidewall surface producedby i-MacEtch.

We now discuss the on-state performance. The drive currentIon reaches 7.2 μA per fin or 6 μA/μm when normalized bythe gate periphery (Fig. 3(a)), at VDS = VGS − Vth = VDD =1.0 V, where VGS = Vth was defined when ID = 0.1 μ A/μm.The peak transconductance gm is 14.4 μS per fin or 12 μS/μmby the same normalization method. The Ion value per finachieved is reasonable considering the long channel geometryand un-optimized parasitic resistance especially from the S/Dextension region. In fact, it is much higher comparing withthat of low aspect ratio junctionless Si FinFETs (0.25 μA perfin at VDD = 1.0 V) with gate lengths Lg = 1 μm [9] andsimilar to the stacked Si nanowire channels with Lg = 250 nm(20 μA per stack at VDD = 1.0 V) [7] and 14 nm nodeSi FinFET Lg = 14 nm technology (33.7 μA per fin atVDD = 0.8 V) [2]. The 3-stacked In0.53Ga0.47As nanowirechannel with Lc = 200 nm and Lg = 1 μm, reported thehighest Ion [21] (480 μA per stack at VDD = 1.0 V), althoughthe trade-off there was a passable Ss and high off-stateleakage.

Due to the extraordinarily HAR of the fin structure, theprocess challenge to shrink the channel length is significantlyincreased. For example, a very thick photoresist layer was usedin order to cover the entire tall vertical fins, which makes itdifficult to scale the lateral dimension. As a result, one majorsource of the parasitic resistance comes from the large gap(∼600 nm) between gate and S/D in our devices due to thenon-self-aligned process. RS/D should be around 2/3 of thetotal on-state resistance Ron at flat-band condition, since theungated fin length is almost 2X the channel length (Fig. 2b).Fig. 4(b) plots Ron, which was extracted from the linear regionof the output curve, and threshold voltage Vth as a functionof W f in . Vth increases as Wfin decreases as expected, dueto conduction constriction. Ron suffers severely from Wfinscaling, along with that for the long ungated S/D extensionregion. For the 20 nm Wfin device (Fig. 3), Ron = 23.8 k�-μm, and the intrinsic drive current can be projected to reach 18μA/μm, or 21.6 μA per fin, at VDD = 1.0 V after removingthe ungated S/D extension resistance (∼2/3 of Ron). Note thatthe contact resistance is negligible [22] because it is muchsmaller than Ron.

Therefore, removing the huge parasitic resistance from theungated S/D extension is a critical issue to address in futurework for performance improvement. This can be done byincreasing the doping concentration in the S/D extension,developing self-aligned process [23] and advanced 3D pattern-ing to shrink the source to drain distance and achieve shortchannel devices.

Despite of the un-optimized geometry, it is clear thatincreasing Hfin can indeed boost the absolute value of Ion.However, it also proportionally increases the gate intrinsiccapacitance Cgate, canceling the advantage of Ion increaseon circuit delay τtot = CtotalVD D/Ion. The total capacitancein a CMOS logic circuit, Ctotal, is comprised of multipleparts in parallel connection, including interconnect wire lateralcapacitance on the same layer and area capacitance betweenwires on different layers (Cwire), parasitic fringing capacitance(Cfringe), and Cgate. In aggressively scaled CMOS circuits,the effect of interconnect wires becomes more and moreprominent, which Cgate becomes less significant to Ctotal.Therefore, by increasing Hfin (or aspect ratio for the sameWfin) for a given Cwire, Ion increases faster than Ctotal, thusthe total delay τtot is reduced. The larger Cwire is relative toCgate, the sharper the decrease is in τtot. Note that Cwire/Cgateratio goes up as the technology node scales down, therefore,the benefit of increasing AR in FinFETs should become morepronounced.

IV. CONCLUSION

We have reported the design, fabrication, device perfor-mance of ultra-HAR junctionless FinFETs. The device struc-ture consists of a uniformly doped extremely-tall fin body asthe channel and S/D without p-n junctions. An unconventionalwet etching method, i-MacEtch, has enabled the fabricationof InP junctionless FinFETs with ultra-high ARs (∼50:1).This novel approach eliminates the need for dry etchingrelated ion-induced damage ion implantation, and subsequentthermal budgets, crucial to producing high quality surfacesand interfaces. The fabricated devices have shown high drivecurrent per fin, a near-ideal subthreshold slope, and lowleakage current. HAR junctionless FinFETs presented hereprovide a viable route to achieve high Ion transistors and fastdelay high speed circuits.

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