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8254 Timer/Counter
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Block diagram of 8254D 0 -D 7 Data busCLK n Clock gate
inputs
GATE n Counter gate input
OUT n Counter output
RD Read
WR Write
CS Chip select
A0-A1 Counter select
Vcc /GND +5 V supply /Ground
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Pin diagram of 8254
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1. Data bus buffer:-Bidirectional 8 bit data bus buffer and is
used to
interface 8254 data bus with system bus2. Read/write logic:-used
for read and write operation
3. CS-Chip select
4. counters:-Three independent 16 bit down counters. Eachcounter
is having 2 input i.e. CLK and GATECLK is used as an input to
counter
GATE is used to control the counter.Counter gives output on OUT
pin
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5. Address lines A 0 and A 1 :-
A1 A0 Selection
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control word register
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Control word registerformat
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Read back command:-
Powerful command which allows theuser to check the count value
,programmed mode and currentmode and current status of
thecounter
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Mode 0:-Interrupt on Terminal CountIn this mode, the counter
will start counting from the
initial COUNT value loaded into it, down to 0.Counting rate is
equal to the input clock frequency.
Mode 1:-Hardware-Triggered One Shot In this mode 8254 can be
used as mono-stable
multi-vibrator.
GATE input is used as trigger input.OUT will be initially high.
OUT will go low on the
CLK pulse following a trigger to begin the one-shot pulse, and
will remain low until the Counter
reaches zero. OUT will then go high and remainhigh until the CLK
pulse after the next trigger.
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Mode 2 (X10): Rate GeneratorIn this mode, the device acts as a
divide-by-n
counter, which is commonly used to generate areal-time clock
interrupt.
Mode 3 (X11): Square Wave Generator This mode is similar to mode
2. However, the
duration of the high and low clock pulses of the
output will be different from mode 2.Mode 4 (100): Software
Triggered StrobeAfter Control Word and COUNT is loaded, the
output will remain high until the counterreaches zero. The
counter will then generate a
low pulse for 1 clock cycle (a strobe) - afterthat the output
will become high again.
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Mode 5 (101): Hardware Triggered
Strobe This mode is similar to mode 4.
However, the counting process is
triggered by the GATE input.
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Applications:-
Used for controlling real-time eventssuch as real-time clock,
eventscounter, and motor speed anddirection control
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8085
8254 interfacing in I/Omapped I/OIn I/O mappe d I/O scheme the
address
of the I/O ports is of 8 bits. The A 0-A7 contents are copied
onA8-A15A15/7 A14/6 A13/5 A12/4 A11/3 A10/2 A9/1 A8/0
Operations
0 0 Counter 0
0 1 Counter 1
1 0 Counter2
1 1 Controlregister
Used to
enable thedecoder
Used as input to
decoder
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8254 interfacing in I/Omapped I/O
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