8086 Internal Block Diagram Enotes

Prof. S. Jagannathan,HOD – Dept of E & C Engg,R.V. C. E, Bangalore

8086 Internal Block diagram (Intel Corp.)

eNotes

By

Prof. S. Jagannathan,

HOD – Department of Electronics and Communication Engineering,

R.V. College of Engineering, Bangalore


Session - III

ADVANCED MICROPROCESSORS Contents

• Block Diagram of 8086

• segment registers

• 8086 flag register format

8086 Internal Block diagram (Intel Corp.)

The block diagram of 8086 is as shown. This can be subdivided into two parts, namely

the Bus Interface Unit and Execution Unit. The Bus Interface Unit consists of segment

registers, adder to generate 20 bit address and instruction prefetch queue.

Once this address is sent out of BIU, the instruction and data bytes are fetched from

memory and they fill a First In First Out 6 byte queue.


Execution Unit:

The execution unit consists of scratch pad registers such as 16-bit AX, BX, CX and DX

and pointers like SP (Stack Pointer), BP (Base Pointer) and finally index registers such as

source index and destination index registers. The 16-bit scratch pad registers can be split

into two 8-bit registers. For example, AX can be split into AH and AL registers. The

segment registers and their default offsets are given below.

Segment Register Default Offset

CS IP (Instruction Pointer)

DS SI, DI

SS SP, BP

ES DI

The Arithmetic and Logic Unit adjacent to these registers perform all the operations. The

results of these operations can affect the condition flags.

Different registers and their operations are listed below:

Register Operations

AX Word multiply, Word divide, word I/O

AL Byte Multiply, Byte Divide, Byte I/O, translate, Decimal Arithmetic

AH Byte Multiply, Byte Divide

BX Translate

CX String Operations, Loops

CL Variable Shift and Rotate

DX Word Multiply, word Divide, Indirect I/O


Generation of 20-bit Physical Address:

IP

SR

DI

SI

BP

SP

DX

CX

AX

BX

ES

SS

DS

CS

Instruction Pointer

Code Segment Register

Data Segment Register

Stack Segment Register

Extra Segment Register

AH

Stack Pointer Register

AL

BE BL

CE CL

DH DL

Break Pointer Register

Source Index Register

Destination Index Register

Status Register

Code Segment (64Kb)

Data Segment (64Kb)

Stack Segment (64Kb)

Extra Segment (64Kb)

FFFFF16

00000016

8086/8088 MPU MEMORY


LOGICAL ADDRESS

SEGMENT REGISTER 0000

ADDER

20 BIT PHYSICAL MEMORY ADDRESS


8086 flag register format

There are three internal buses, namely A bus, B bus and C bus, which interconnect the

various blocks inside 8086.

The execution of instruction in 8086 is as follows:

The microprocessor unit (MPU) sends out a 20-bit physical address to the memory and

fetches the first instruction of a program from the memory. Subsequent addresses are sent

(a) : CARRY FLAG – SET BY CARRY OUT OF MSB (b) : PARITY FLAG – SET IF RESULT HAS EVEN PARITY (c) : AUXILIARY CARRY FLAG FOR BCD (d) : ZERO FLAG – SET IF RESULT = 0 (e) : SIGN FLAG = MSB OF RESULT (f) : SINGLE STEP TRAP FLAG (g) : INTERRUPT ENABLE FLAG (h) : STRING DIRECTION FLAG (i) : OVERFLOW FLAG

(i)

(h)

(g)

(f)

(e)

(d)

(b)

(c)

(a)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

U U U U 0F DF IF TF SF ZF U AF U PF U CF

U= UNDEFINED

BIT


out and the queue is filled upto 6 bytes. The instructions are decoded and further data (if

necessary) are fetched from memory. After the execution of the instruction, the results

may go back to memory or to the output peripheral devices as the case may be.

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8086 Internal Block Diagram Enotes