Pin Diagram of 8086 Handouts

8/13/2019 Pin Diagram of 8086 Handouts

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Gursharan Singh [email protected]

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Intel 8086

Intel 8086 was launchedin 1978.

It was the first 16-bitmicroprocessor.

This microprocessor hadmajor improvement overthe execution speed of8085.

It is available as 40-pinDual-Inline-Package(DIP).

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Intel 8086 It is available in three

versions:

8086 (5 MHz)

8086-2 (8 MHz)

8086-1 (10 MHz)

It consists of 29,000transistors.


Intel 8086 It has a 16 line data

bus.

And 20 line addressbus.

It could address up to1 MB of memory.

It has more than20,000 instructions.

It supportsmultiplication anddivision.


Pin Diagram of Intel 8086


AD0 AD15Pin 16-2, 39 (Bi-directional) These lines are multiplexed bi-

directional address/data bus.

During T1, they carry lowerorder 16-bit address.

In the remaining clock cycles,they carry 16-bit data.

AD0-AD7 carry lower order byteof data.

AD8-AD15 carry higher orderbyte of data.



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A19/S6, A18/S5, A17/S4, A16/S3Pin 35-38 (Unidirectional)

These lines aremultiplexed unidirectionaladdress and status bus.

During T1, they carryhigher order 4-bit address.

In the remaining clockcycles, they carry statussignals.


BHE / S7Pin 34 (Output)

BHE stands for Bus HighEnable.

BHE signal is used toindicate the transfer of dataover higher order data bus(D8 D15).

8-bit I/O devices use thissignal.

It is multiplexed with statuspin S7.


RD (Read)Pin 32 (Output)

It is a read signal used forread operation.

It is an output signal.

It is an active low signal.


READYPin 22 (Input)

This is an acknowledgementsignal from slower I/Odevices or memory.

It is an active high signal.

When high, it indicates thatthe device is ready to

transfer data.

When low, thenmicroprocessor is in waitstate.


RESETPin 21 (Input)

It is a system reset.


When high,microprocessor enters intoreset state and terminatesthe current activity.

It must be active for atleast four clock cycles toreset the microprocessor.


INTRPin 18 (Input)

It is an interrupt requestsignal.

It is active high.

It is level triggered.



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NMIPin 17 (Input)

It is a non-maskableinterrupt signal.

It is an active high.

It is an edge triggeredinterrupt.


TESTPin 23 (Input)

It is used to test thestatus of math co-processor 8087.

The BUSY pin of 8087 isconnected to this pin of8086.

If low, execution continueselse microprocessor is inwait state.


CLKPin 19 (Input)

This clock input providesthe basic timing forprocessor operation.

It is symmetric squarewave with 33% duty cycle.

The range of frequency ofdifferent versions is 5MHz, 8 MHz and 10 MHz.


VCC and VSSPin 40 and Pin 20 (Input)

VCC is power supply signal.

+5V DC is suppliedthrough this pin.

VSS is ground signal.


MN / MXPin 33 (Input)

8086 works in two modes:

Minimum Mode

Maximum Mode

If MN/MX is high, it worksin minimum mode.

If MN/MX is low, it worksin maximum mode.


MN / MXPin 33 (Input)

Pins 24 to 31 issue twodifferent sets of signals.

One set of signals is issuedwhen CPU operates inminimum mode.

Other set of signals isissued when CPU operatesin maximum mode.



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Pin Description for

Minimum Mode


INTAPin 24 (Output)

This is an interruptacknowledge signal.

When microprocessorreceives INTR signal, itacknowledges theinterrupt by generatingthis signal.



ALEPin 25 (Output)

This is an Address LatchEnable signal.

It indicates that validaddress is available on busAD0 AD15.

It is an active high signal

and remains high during T1state.

It is connected to enable pinof latch 8282.


DENPin 26 (Output)

This is a Data Enablesignal.

This signal is used toenable the transceiver8286.

Transceiver is used toseparate the data from theaddress/data bus.



DT / RPin 27 (Output)

This is a DataTransmit/Receive signal.

It decides the direction ofdata flow through thetransceiver.

When it is high, data istransmitted out.

When it is low, data isreceived in.


M / IOPin 28 (Output)

This signal is issued by themicroprocessor todistinguish memory accessfrom I/O access.

When it is high, memory isaccessed.

When it is low, I/O devicesare accessed.



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WRPin 29 (Output)

It is a Write signal.

It is used to write data inmemory or output devicedepending on the status ofM/IO signal.



HLDAPin 30 (Output)

It is a Hold Acknowledgesignal.

It is issued after receivingthe HOLD signal.



HOLDPin 31 (Input)

When DMA controllerneeds to use address/databus, it sends a request tothe CPU through this pin.


When microprocessorreceives HOLD signal, itissues HLDA signal to theDMA controller.


Pin Description for

Maximum Mode


QS1

and QS0Pin 24 and 25 (Output)

These pins provide thestatus of instructionqueue.


QS1 QS0 Status

0 0 No operation

0 1 1st byte of opcode from queue

1 0 Empty queue

1 1 Subsequent byte from queue

S0, S

1, S

2Pin 26, 27, 28 (Output)

These status signalsindicate the operationbeing done by themicroprocessor.

This information isrequired by the BusController 8288.

Bus controller 8288generates all memory andI/O control signals.



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S0, S1, S2Pin 26, 27, 28 (Output)


S2 S1 S0 Status

0 0 0 Interrupt Acknowledge

0 0 1 I/O Read

0 1 0 I/O Write

0 1 1 Halt

1 0 0 Opcode Fetch

1 0 1 Memory Read

1 1 0 Memory Write

1 1 1 Passive

LOCKPin 29 (Output)

This signal indicates thatother processors should notask CPU to relinquish thesystem bus.

When it goes low, allinterrupts are masked andHOLD request is notgranted.

This pin is activated by usingLOCK prefix on anyinstruction.


RQ/GT1 and RQ/GT0Pin 30 and 31 (Bi-directional)

These are Request/Grantpins.

Other processors request theCPU through these lines torelease the system bus.

After receiving the request,CPU sends acknowledgesignal on the same lines.

RQ/GT0 has higher priority

than RQ/GT1.

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Pin Diagram of 8086 Handouts