8085 Programming[1]

ER.PERUMAL MANIMEKALAI COLLEGE OF ENGINEERING

CONTENTS

1. 8085 PROGRAMING

i) 8-Bit Additionii) 8-Bit Subtractioniii) 8-Bit Divisioniv) Logical Operationv) Smallest Datavi) Largest Datavii) Ascending Orderviii) Descending Orderix) Look Up Tablex) Factorialxi) Square Rootxii) Average

2. 8086 PROGRAMING

i) 8-Bit Additionii) 8-Bit Subtractioniii) 8-Bit Divisioniv) Logical Operationv) Smallest Datavi) Largest Datavii) Ascending Orderviii) Descending Order

3. 8086 PROGRAMING

i) 8-Bit Additionii) 8-Bit Subtractioniii) 8-Bit Divisioniv) Logical Operationv) Smallest Datavi) Largest Data

DEPT OF ECE 1


vii) Ascending Orderviii) Descending Order

DEPT OF ECE 2


8085 PROGRAMMING

1. PROGRAMS BASED ON ARITHMETIC AND LOGIC INSTRUCTIONS

i) 8-BIT ADDITION USING 8085

INPUT: (4150)=21 OUTPUT:(4152)=56

(4151)=35

ii) 8-BIT SUBTRACTION USING 8085

MEMORY ADDRESS

OPCODES MNEMONICS OPERANDS

4100 3A LDA 41504101 504102 414103 47 MOV B,A4104 3A LDA 41514105 514106 414107 90 SUB B4108 32 STA 41524109 52410A 41

410B 76 HLT 76

DEPT OF ECE 3

MEMORY ADDRESS


4100 3A LDA 41504101 504102 414103 47 MOV B,A4104 3A LDA 41514105 514106 414107 80 ADD B4108 32 STA 41524109 52410A 41410B 76 HLT 76


INPUT: (4150) = 43 OUTPUT: (4152) = 0E (4151) = 51

iii) 8-BIT MULTIPLICATION USING 8085

MEMORY ADDRESS

OPCODES LABEL MNEMONICS OPERANDS

4100 21 LXI H,42004101 004102 424103 0E MVI C,004104 004105 AF XRA A4106 46 MOV B,M4107 23 INX H4108 56 MOV D,M4109 82 REPT: ADD D410A D2 JNC AHEAD

410B 0E

410C 41

410D 0C INR C

410E 05 AHEAD: DCR B

410F C2 JNZ REPT

4110 09

4111 41

4112 23 INX H

4113 77 MOV M,A

4114 23 INX H

4115 71 MOV M,C

4116 76 HLT

INPUT: (4200) = 06 OUTPUT: (4202) = 18 (4201) = 04 (4203) = 00

iv) 8-BIT DIVISION USING 8085

MEMORY ADDRESS


DEPT OF ECE 4


4100 3A LDA 42014101 014102 424103 47 MOV B,A4104 3A LDA 42004105 004106 424107 0E MVI C,004108 004109 B8 AGAIN: CMP B410A DA JC STORE

410B 12

410C 41

410D 90 SUB B

410E 0C INR C

410F C3 JMP AGAIN

4110 09

4111 41

4112 32 STORE: STA 4203

4113 03

4114 42

4115 79 MOV A,C

4116 32 STA 4202

4117 02

4118 42

4119 76 HLT

INPUT: (4201) = 05 (4200) = 40HRESULT: (4203) = 04 (REMINDER)

(4202) = 0CH (QUOTIENT)

v) LOGICAL OPERATIONS USING 8085

MEMORY ADDRESS


4100 3A LDA 4150

DEPT OF ECE 5


4101 504102 414103 47 MOV B,A4104 3A LDA 41524105 514106 414107 4F MOV C,A4108 A0 ANA B4109 32 STA 4152410A 52

410B 41

410C 79 MOV A,C

410D B0 ORA B

410E 32 STA 4153

410F 53

4110 41

4111 79 MOV A,C

4112 A8 XRA B

4113 32 STA 4154

4114 54

4115 41

4116 79 MOV A,C

4117 2F CMA A

4118 32 STA 4155

4119 55

411A 41

411B 76 HLT

INPUT: (4150) = FF (4151) = 88HOUTPUT: (4152) = 88H (4153) = FFH (4154) = 77H (4155) = 77H

2) i) SMALLEST DATA USING 8085

MEMORY ADDRESS


4100 21 LXI H,42004101 004102 42

DEPT OF ECE 6


4103 46 MOV B,M4104 23 INX H4105 7E MOV A,M4106 05 DCR B4107 23 LOOP: INX H4108 BE CMP M4109 DA JC AHEAD410A 0D

410B 41

410C 7E MOV A,M

410D 05 AHEAD: DCR B

410E C2 JNZ LOOP

410F 07

4110 41

4111 32 STA 4300

4112 00

4113 43

4114 76 HLT

INPUT: (4200)= 05 -- COUNT (NO OF ELEMENTS) (4201)= 03 (4202)= 0A (4203)= FF (4304)= 01 (4305)= 12

RESULT: (4300)= 01

ii) LARGEST DATA USING 8085

MEMORY ADDRESS


4100 21 LXI H,42004101 004102 424103 46 MOV B,M4104 23 INX H4105 7E MOV A,M4106 05 DCR B4107 23 LOOP: INX H4108 BE CMP M4109 D2 JNC AHEAD410A 0D

DEPT OF ECE 7


410B 41

410C 7E MOV A,M

410D 05 AHEAD: DCR B

410E C2 JNZ LOOP

410F 07

4110 41

4111 32 STA 4300

4112 00

4113 43

4114 76 HLT

INPUT: (4200)= 05 -- COUNT (NO OF ELEMENTS) (4201)= 03 (4202)= 0A (4203)= FF (4304)= 01 (4305)=12

RESULT: (4300)= FF

3) i) ARRANGING DATA IN DECENDING ORDER USING 8085

MEMORY ADDRESS


4100 3A LDA 42004101 004102 424103 47 MOV B,A4104 05 DCR B4105 21 LOOP2: LXI H,42004106 004107 424108 4E MOV C,M4109 0D DCR C410A 23 INX H

410B 7E LOOP1: MOV A,M

410C 23 INX H

410D BE CMP M

410E D2 JNC AHEAD

410F 16

4110 41

4111 56 MOV D,M

DEPT OF ECE 8


4112 77 MOV M,A

4113 2B DCX H

4114 72 MOV M,D

4115 23 INX H

4116 0D AHEAD: DCR C

4117 C2 JNZ LOOP1

4118 0B

4119 41

411A 05 DCR B

411B C2 JNZ LOOP2

411C 05

411D 41

411E 76 HLT

INPUT: (4200)=05 -- COUNT(NO OF ELEMENTS) (4201)= 04 (4202)= FE (4203)=23 (4204)=CD (4205)= 34

OUTPUT:(4201)=FE (4202)=CD (4203)=34 (4204)=23 (4205)=04

3) i) ARRANGING DATA IN ASCENDING ORDER USING 8085

MEMORY ADDRESS


4100 3A LDA 42004101 004102 424103 47 MOV B,A4104 05 DCR B4105 21 LOOP2: LXI H,42004106 004107 424108 4E MOV C,M4109 0D DCR C410A 23 INX H

410B 7E LOOP1: MOV A,M

410C 23 INX H

410D BE CMP M

DEPT OF ECE 9


410E DA JC AHEAD

410F 16

4110 41

4111 56 MOV D,M

4112 77 MOV M,A

4113 2B DCX H

4114 72 MOV M,D

4115 23 INX H

4116 0D AHEAD: DCR C

4117 C2 JNZ LOOP1

4118 0B

4119 41

411A 05 DCR B

411B C2 JNZ LOOP2

411C 05

411D 41

411E 76 HLT

INPUT: (4200)=05 -- COUNT(NO OF ELEMENTS) (4201)= 04 (4202)= FE (4203)=23 (4204)=CD (4205)= 34

OUTPUT:(4201)=04 (4202)=23 (4203)=34 (4204)=CD (4205)=FE

4) CODE CONVERSIONS USING 8085 i) ASCII TO HEX CONVERSION

MEMORY ADDRESS


4100 3A LDA 45004101 004102 454103 D6 SUI 304104 304105 FE CPI 0A4106 0A4107 DA JC SKIP

DEPT OF ECE 10


4108 0C4109 41410A D6 SUI 07

410B 07

410C 32 SKIP: STA 4501

410D 01

410E 45

410F 76 HLT

INPUT: (4500)=31 OUTPUT:(4501)=01

ii) HEX TO ASCII CONVERSION

MEMORY ADDRESS


4100 3A LDA 42004101 004102 424103 47 MOV B,A4104 E6 ANI 0F4105 0F4106 CD CALL SUB14107 1A4108 414109 32 STA 4201410A 01

410B 42

410C 78 MOV A,B

410D E6 ANI F0

410E F0

410F 07 RLC

4110 07 RLC

4111 07 RLC

4112 07 RLC

4113 CD CALL SUB1

4114 1A

4115 41

4116 32 STA 4202

DEPT OF ECE 11


4117 02

4118 42

4119 76 HLT

411A FE SUB1: CPI 0A

411B 0A

411C DA JC SKIP

411D 1F

411E 41

411F C6 ADI 07

4120 07

4121 C6 SKIP: ADI 30

4122 30

4123 C9 RET

INPUT: (4200)=04 OUTPUT: (4201)=34 (4202)=30

iii) HEX TO BCD

MEMORY ADDRESS


4100 21 LXI H,41504101 504102 414103 16 MVI D,004104 004105 AF XRA A4106 4E MOV C,M4107 C6 LOOP2: ADI 014108 014109 27 DAA410A D2 JNC LOOP1

410B 0E

410C 41

410D 14 INR D

410E 0D LOOP1: DCR C

DEPT OF ECE 12


410F C2 JNZ LOOP2

4110 07

4111 41

4112 32 STA 4151

4113 51

4114 41

4115 7A MOV A,D

4116 32 STA 4152

4117 52

4118 41

4119 76 HLT

INPUT: (4150)=FF OUTPUT: (4151)= 55 (LSB) (4152)= 02 (MSB)

iv) BCD TO HEX

MEMORY ADDRESS


4100 21 LXI H,41504101 504102 414103 7E MOV A,M4104 87 ADD A4105 47 MOV B,A4106 87 ADD A4107 87 ADD A4108 80 ADD B4109 23 INX H410A 86 ADD M

410B 23 INX H

410C 77 MOV M,A

410D 76 HLT

INPUT: (4150) = 02 – MSD RESULT: (4152) = 1D H = 29 D (4151) = 09 – LSD

DEPT OF ECE 13


5) PROGRAM TO FIND SQUARE OF A GIVEN NUMBER USING LOOK UP TABLE

MEMORY ADDRESS

OPCODES LABLE MNEMONICS OPERANDS

4100 21 LXI H,4125

4101 25

4102 41

4103 3A LDA 4150

4104 50

4105 41

4106 FE CPI 0A

4107 0A

4108 DA JC AFTER

4109 11

410A 41

410B 3E MVI A,FF410C FF410D 32 STA 4151410E 51410F 414110 76 HLT4111 3D AFTER: DCR A4112 4F MOV C,A4113 06 MVI B,004114 004115 09 DAD B4116 7E MOV A,M4117 32 STA 41514118 514119 41411A 76 HLT

LOOK UP TABLE

(4125)=01 (4128)=16 (412B)=49 (4126)=04 (4129)=25 (412C)=64 (4127)=09 (412A)=36 (412D)=81

INPUT: (4150) = 05 OUTPUT: (4151) = 25

DEPT OF ECE 14


INPUT: (4150) = 11 OUTPUT: (4151) = FF

6) PROGRAM TO FIND FACTORIAL OF A NUMBER USING 8085

MEMORY ADDRESS


4100 31 LXI SP,4200

4101 00

4102 42

4103 3A LDA 4300

4104 00

4105 43

4106 FE CPI 02

4107 02

4108 DA JC LAST

4109 1A

410A 41

410B 16 MVI D,00410C 00410D 5F MOV E,A410E 3D DCR A410F 4F MOV C,A4110 CD CALL FACTO4111 214112 414113 EB XCHG4114 22 SHLD 44004115 004116 444117 C3 JMP END4118 1D4119 41411A 21 LAST: LXI H,0001411B 01411C 00411D 22 END: SHLD 4401411E 01411F 44

DEPT OF ECE 15


4120 76 HLT4121 21 FACTO: LXI H,OOOO4122 004123 004124 41 MOV B,C4125 19 BACK: DAD D4126 05 DCR B4127 C2 JNZ BACK4128 254129 41412A EB XCHG412B 0D DCR C412C C4 CNZ FACTO412D 10412E 41412F C9 RET

INPUT: (4300) = 04 OUTPUT: (4401) = 18H

7. PROGRAM TO FIND SQURE ROOT OF A NUMBER

MEMORY ADDRESS


4100 3A LDA 4200H

4101 00

4102 42

4103 47 MOV B,A

4104 0E MVI C,02H

4105 02

4106 CD CALL DIV

4107 1F

4108 41

4109 5A REP: MOV E,D

410A 78 MOV A,B

410B 4A MOV C,D410C CD CALL DIV410D 1F410E 41410F 7A MOV A,D4110 83 ADD E

DEPT OF ECE 16


4111 0E MVI C,02H4112 024113 CD CALL DIV4114 1F4115 414116 7B MOV A,E4117 BA CMP D4118 C2 JNZ RPT4119 09411A 41411B 32 STA 4201H411C 01411D 42411E 76 HLT411F 16 DIV: MVI D,00H4120 004121 91 NEXT: SUB C4122 14 INR D4123 B9 CMP C4124 D2 JNC NEXT4125 214126 414127 C9 RET

INPUT: (4200) = 04 RESULT: (4201) = 02

8. PROGRAM TO FIND AVERAGE OF N NUMBERS

MEMORY ADDRESS


4100 21 LXI H,4200

4101 00

4102 42

4103 4E MOV C,M

4104 41 MOV B,C

4105 AF XRA A

4106 23 INX H

DEPT OF ECE 17


4107 56 RPT: MOV D,M

4108 82 ADD D

4109 23 INX H

410A 0D DCR C

410B C2 JNZ RPT410C 07410D 41410E 0E MVI C,00410F 004110 B8 CMP B4111 DA JC STORE4112 194113 414114 90 SUB B4115 0C INR C4116 C3 JMP AGAIN4117 104118 414119 79 STORE: MOV A,C411A 32 STA 4300411B 00411C 43411D 76 HLT

INPUT: (4200) = 04 --- COUNT (4201) = 01 (4202) = 02 (4203) = 03 (4204) = 05

RESULT: (4300) = 02

DEPT OF ECE 18


8086 PROGRAMMING

8086 PROGRAMMING

1. ADDITION OF TWO 16-BIT NUMBERS

INPUT: [1100] = 1234 RESULT: [1200] = 68AC [1102] = 5678

2. 16-BIT SUBTARACTION

DEPT OF ECE 19

MEMORY ADDRESS


1000 8B MOV AX,[1100]

1001 06

1002 00

1003 11

1004 03 ADD AX,[1102]

1005 06

1006 02

1007 11

1008 89 MOV [1200],AX

1009 06

100A 00

100B 12

100C F4 HLT


INPUT: [1100] = 9999 RESULT: [1200] = 62FD

[1102] =369C

3. 16-BIT MULTIPLICATION

DEPT OF ECE 20

MEMORY ADDRESS


1000 8B MOV AX,[1100]

1001 06

1002 00

1003 11

1004 2B SUB AX,[1102]

1005 06

1006 02

1007 11

1008 89 MOV [1200],AX

1009 06

100A 00

100B 12

100C F4 HLT


INPUT: [1100] = FEDC

RESULT: [1200] = B9C3

[1102] =BA98 [1202] = 2AA0

4. 32-BIT DIVISION

DEPT OF ECE 21

MEMORY ADDRESS


1000 8B MOV AX , [1100]

1001 06

1002 00

1003 11

1004 8B MOV BX , [1102]

1005 1E

1006 02

1007 11

1008 F7 MUL BX

1009 E3

100A 89 MOV [1200] , DX

100B 16

100C 00

100D 12

100E 89 MOV [1202] , AX

100F 06

1010 02

1011 12

1012 F4 HLT


DEPT OF ECE 22

MEMORY ADDRESS


1000 8B MOV DX, [1100]

1001 16

1002 00

1003 11

1004 8B MOV AX, [1102]

1005 06

1006 02

1007 11

1008 8B MOV CX, [1104]

1009 0E

100A 04

100B 11

100C F7 DIV CX

100D F1

100E 89 MOV [1200] , AX

100F 06

1010 00

1011 12

1012 89 MOV [1202] , DX

1013 16

1014 02

1015 12

1016 F4 HLT


DATA: DIVIDEND: [1100]=0000 RESULT:QUOTIENT: [1200] = 0001 [1102]=FFFF REMAINDER:[1202]=0000

DIVISOR: [1104]=FFFF

5. LOGICAL OPERATIONS

DEPT OF ECE 23


RESULT: [1500] = F2 [1501] = F2

[1502] = 00 [1503] = FF

6. ASCENDING ORDER

DEPT OF ECE 24

MEMORY ADDRESS


1000 C6 MOV AH,0FF

1001 C4

1002 FF

1003 C6 MOV AL,0F2

1004 C0

1005 F2

1006 20 AND AH,AL

1007 C4

1008 88 MOV [1500],AH

1009 26

100A 00

100B 15

100C 08 OR AH,AL

100D C4

100E 88 MOV [1501],AH

100F 26

1010 01

1011 15

1012 30 XOR AH,AL

1013 C4

1014 88 MOV [1502],AH

1015 26

1016 02

1017 15

1018 F6 NOT AH

1019 D4

101A 88 MOV [1503],AH

101B 26

101C 03


DEPT OF ECE 25

MEMORY ADDRESS


1000 C7 MOV SI,1100

1001 C6

1002 00

1003 11

1004 8A MOV CL,[SI]

1005 0C

1006 FE DEC CL

1007 C9

1008 C7 REPEAT: MOV SI,1100H

1009 C6

100A 00

100B 11

100C 8A MOV CH,[SI]

100D 2C

100E FE DEC CH

100F CD

1010 46 INC SI

1011 8A REPCOM: MOV AL,[SI]

1012 04

1013 46 CMP AL,[SI]

1014 3A

1015 04

1016 72 JC AHEAD

1017 05

1018 86 XCHG AL,[SI]

1019 04

101A 86 XCHG AL,[SI-1]

101B 44

101C FF


INPUT : [1100] = 05 ---- COUNT [1101] = 0F [1102] = 13 [1103] = 34 [1104] = 21 [1105] = 10RESULT: [1101] = 0F [1102] = 10 [1103] = 13 [1104] = 21 [1105] = 34

7.DECENDING ORDER

DEPT OF ECE 26


DEPT OF ECE 27

MEMORY ADDRESS


1000 C7 MOV SI,1100

1001 C6

1002 00

1003 11

1004 8A MOV CL,[SI]

1005 0C

1006 FE DEC CL

1007 C9

1008 C7 REPEAT: MOV SI,1100H

1009 C6

100A 00

100B 11

100C 8A MOV CH,[SI]

100D 2C

100E FE DEC CH

100F CD

1010 46 INC SI

1011 8A REPCOM: MOV AL,[SI]

1012 04

1013 46 CMP AL,[SI]

1014 3A

1015 04

1016 73 JNC AHEAD

1017 05

1018 86 XCHG AL,[SI]

1019 04

101A 86 XCHG AL,[SI-1]

101B 44

101C FF


INPUT : [1100] = 05 ---- COUNT [1101] = 0F [1102] = 13 [1103] = 34 [1104] = 21 [1105] = 10RESULT: [1101] = 34 [1102] = 21 [1103] = 13 [1104] = 10 [1105] = 0F

7. SMALLEST NUBER IN THE ARRAY

DEPT OF ECE 28


DEPT OF ECE 29

MEMORY ADDRESS


1000 C7 MOV SI,1100

1001 C6

1002 00

1003 11

1004 C7 MOV DI,1200

1005 C7

1006 00

1007 12

1008 8A MOV CL,SI

1009 0C

100A 46 INC SI

100B 8A MOV AL,[SI]

100C 04

100D FE DEC CL

100E C9

100F 46 AGAIN: INC SI

1010 8A MOV BL,[SI]

1011 1C

1012 38 CMP AL,BL

1013 D8

1014 72 JC AHEAD

1015 02

1016 88 MOV AL,BL

1017 D8

1018 FE AHEAD: DEC CL

1019 C9

101A 75 JNZ AGAIN

101B F3

101C 88 MOV [DI],AL


INPUT : [1100] = 05 ---- COUNT [1101] = 0F [1102] = 13 [1103] = 34 [1104] = 21 [1105] = 10RESULT: [1200] = 0F

8. LARGEST DATA

DEPT OF ECE 30


DEPT OF ECE 31

MEMORY ADDRESS


1000 C7 MOV SI,1100

1001 C6

1002 00

1003 11

1004 C7 MOV DI,1200

1005 C7

1006 00

1007 12

1008 8A MOV CL,SI

1009 0C

100A 46 INC SI

100B 8A MOV AL,[SI]

100C 04

100D FE DEC CL

100E C9

100F 46 AGAIN: INC SI

1010 8A MOV BL,[SI]

1011 1C

1012 38 CMP AL,BL

1013 D8

1014 73 JNC AHEAD

1015 02

1016 88 MOV AL,BL

1017 D8

1018 FE AHEAD: DEC CL

1019 C9

101A 75 JNZ AGAIN

101B F3

101C 88 MOV [DI],AL


INPUT : [1100] = 05 ---- COUNT [1101] = 0F [1102] = 13 [1103] = 34 [1104] = 21 [1105] = 10RESULT: [1200] = 34

INTERFACING PROGRAMS

1. AIM: TO INITIALIZE PORT A AS INPUT PORT AND PORT B AS OUTPUT PORT IN MODE 0

MEMORY ADDRESS


4100 3E MVI A,904101 904102 D3 OUT 0C6H4103 C64104 DB IN 0C0H4105 C04106 32 STA 4500H4107 004108 454109 76 HLT

CONTROL WORD

DEPT OF ECE 32


ADDRESS FOR FOUR REGISTERS IN 8255

REGISTER ADDRESSCONTROL REGISTER C6

PORT A C0PORT B C2PORT C C4

PROCEDURE:1. Enter the program starting from user RAM address 4100h.2. Set a known data at the SPDT switches.3. Execute the program4. The data as set by the SPDT switch settings is input into the accumulator and is stored at location 4500.5. The data output at the 4500 is same as the SPDT switch settings

2. AIM: TO INITILIZE 8253 AND 8251 AND TO CHECK THE TRANSMISSION AND RECEPTION OF A CHARACTER

DEPT OF ECE 33


PROCEDURE: 1.The program first initializes 8253 to give an output clock frequency of 150 khz at channel 0 which will give a 9600 baud rate of 8251.2. Output of channel 0 is connected to transmitter clock and receiver clock of 8251.3. Connect RTS with CTS and TXD with RXD, by setting the jumpers accordingly. Now execute the program.

I/O DECODING 8251 is selected with address

Since the address line A1 is connected to control/data input (C/D) of 8251, the control register of 8251 is selected when

The data register is selected with the address

The I/O address for control register, Channel 0, Channel 1 and Channel 2 are

A7 A6 A5 A4 A3 A2 A1 A0 HEXCONTROL REG 1 1 0 0 1 1 1 0 CE

CHANNEL 0 1 1 0 0 1 0 0 0 C8CHANNEL 1 1 1 0 0 1 0 1 0 CACHANNEL 2 1 1 0 0 1 1 0 0 CC

MEMORY ADDRESS


DEPT OF ECE 34


4100 3E MVI A,364101 364102 D3 OUT 0CEH4103 CE4104 3E MVI A,0AH4105 0A4106 D3 OUT 0C8H4107 C84108 3E MVI A,004109 00410A D3 OUT 0C8H410B C8410C 3E MVI A,4E410D 4E410E D3 OUT 0C2H410F C24110 3E MVI A,37H4111 374112 D3 OUT 0C2H4113 C24114 3E MVI A,414115 414116 D3 OUT 0C0H4117 C04118 CF RST 1

3. AIM: ROLLING DISPLAY (DISPLAY MESSAGE IS “HELP US”)

MEMORY ADDRESS


4100 21 START: LXI H,POINTER4101 2C4102 414103 16 MVI D,0FH4104 0F4105 3E MVI A,10H4106 104107 D3 OUT CNT4108 C24109 3E MVI A,0CCH

DEPT OF ECE 35


410A CC410B D3 OUT CNT410C C2410D 3E MVI A,90H410E 90410F D3 OUT CNT4110 C24111 76 LOOP: MOV A,M4112 D3 OUT DAT4113 C04114 CD CALL DELAY4115 1F4116 414117 23 INX H4118 15 DCR D4119 C2 JNZ LOOP411A 11411B 41411C C3 JMP START411D 00411E 41411F 06 DELAY: MVI B,0A0H4120 A04121 0E LOP1: MVI C,0FFH4122 FF4123 0D LOP2: DCR C4124 C2 JNZ LOP24125 234126 414127 05 DCR B4128 C2 JNZ LOP14129 21412A 41412B C9 RET412C FF412D FF412E FF412F FF4130 FF4131 FF

DEPT OF ECE 36


4132 FF4133 FF4134 884135 684136 7C4137 C84138 1C4139 29413A FF413B FF

LOOK-UP TABEL:

[412C] = FF FF FF FF[4130] = FF FF FF FF[4134] = 98 68 7C C8[4138] = FE 1C 29 FF

SEGMENT DEFINITION:

CORRESPONDENCE BETWEEN THE DATA BUS AND OUTPT PORT BITS OF 8279 AND SEGMENT RELATIONSHIP.

DATA BUS D7 D6 D5 D4 D3 D2 D1 D08279 OUTPUT A3 A2 A1 A0 B3 B2 B1 B0SEGMENTS d c b a dp g f e

D0 bit of the byte send to the display RAM corresponds to B0 and D7 of the byte sent to the display RAM corresponds A3. In order to light up a segment the corresponding bit of data written into the display RAM should be a “0”.

DEPT OF ECE 37


4. ANALOG TO DIGITAL CONVERTION

PROCEDURE: 1.Place jumper J2 in C position 2.Place jumper J5 in A position 3.Enter and execute the program 4.Vary th analog input(using trimpot) and verify the digital data displayed with that data stored in memory

MEMORY ADDRESS


4100 3E MVI A,104101 104102 D3 OUT 0C8H4103 C84104 3E MVI A,184105 184106 D3 OUT 0C8H4107 C84108 3E MVI A,014109 01410A D3 OUT 0D0H410B D0410C AF XRA A410D AF XRA A410E AF XRA A410F 3E MVI A,004110 004111 D3 OUT 0D0H4112 D04113 DB LOOP: IN 0D8H4114 D84115 E6 ANI 014116 014117 FE CPI 014118 014119 C2 JNZ LOOP411A 13411B 41

DEPT OF ECE 38


411C DB IN 0C0H411D C0411E 32 STA 4150H411F 504120 414121 76 HLT

Theory: A 3 to 8 decoded 74LS138(U2) is employed to generate I/O decoding logic.Pin1,Pin2 and Pin3 of 74LS138(U2) is employed to generate I/O decoding logic.Pin1, Pin2 and Pin3 of 74LS138 are connected to address lines A3,A4 and A5 respectively.IOR and IOW signals are NANDed together and the NAND gate output is connected to Pin6 of 74LS138. Similarly the Address lines A6 and A7 are NAND gate output lied to Pin5 of the 3 to 8 decoder.Pin4 is grounded.

The I/O address for the latch 74LS174 which latches the data bus to ADD A,ADD B, ADD C and ALE 1 and ALE 2 is

The buffer 74LS244 transfers the converted data outputs to data bus is selected when

The flip flop 74LS74 which transfers the D0 line status to the SOC pin ADC 0809 is selected

The EOC output ADC1 and ADC2 is transferred to D0 line by means of two tristate buffers. The EOC1 is selected when

DEPT OF ECE 39


Table gives data to be outputted to port address C8 for channels 0 to 7

CHANNEL NUMBER

EOC ADDRESS(IN

HEX)

DATA (IN HEX)CH NO ALE

LOW OE HIGH

CH NO ALE HIGH OE

HIGH

CH NO ALE LOW OE

HIGHCH0 D8 10 18 10CH1 D8 11 19 11CH2 D8 12 1A 12CH3 D8 13 1B 13CH4 D8 14 1C 14CH5 D8 15 1D 15CH6 D8 16 1E 16CH7 D8 17 1F 17

5. To generate a saw tooth wave at the output of DAC-1

MEMORY ADDRESS


4100 3E START: MVI A,004101 004102 D3 L1: OUT 0C0H4103 C04104 3C INR A4105 C2 JNZ L14106 024107 414108 C3 JMP START4109 00410A 41

THEORY:DAC 0800 is a monolithic, high speed ,current output Digital to Analog converter.

DEPT OF ECE 40


I/O DECODING: The IC’s 74LS138 and 74LS00 form the address decoding logic in this interface board. The address lines A3,A4 and A5 are tied to pin1,pin2 and pin3 of 74ls138 respectively. The address lines A6 and A7 are NANDed together and the NAND gate output is conncted to pin 5 of 74LS138.Similarly IOW and IOR signals are NANDed and the NAND gate output is connected to pin 6 of 74LS1328.Pin 4 is grounded.

6. To run the stepper motor in both forward and reverse direction with delay

MEMORY ADDRESS


4100 21 START: LXI H,LOOK UP4101 1A4102 414103 06 MVI B,04H4104 044105 7E REPT: MOV A,M4106 D3 OUT 0C0H4107 C04108 11 LXI D,0303H4109 03410A 03410B 00 DELAY: NOP410C 1B DCX D410D 7B MOV A,E410E B2 ORA D410F C2 JNZ DELAY4110 0B4111 414112 23 INX H4113 05 DCR B4114 C2 JNZ REPT

DEPT OF ECE 41


4115 054116 414117 C3 JMP START4118 004119 41411A 09 LOOK UP: DB 09 05 06 0A411B 06411C 06411D 0A

PROCEDURE:1. Enter the program starting from location 4100.2. Execute the program3. Stepper motor runs in forward direction4.speed can be varied by varying the count at DE pair4. To run the stepper motor in anticlockwise direction the sequence should be given is 0Ah,06H,05H,09H

Theory: A motor in which the rotor is able to assume only discrete stationary angular position is a stepper motor. The rotary motion occurs in a stepwise manner from one equilibrium position to the next.As shown in the figure below the four pole structure is continuous with the stator frame and the magnetic field passes through the cylindrical stator annular ring. The rotor magnetic system has two end faces. The left face is permanently magnetized as south pole and the right face as north pole. The south pole structure and north pole structure possess similar pole faces. The north pole structure is twisted with respect to the south pole structure so that south pole comes precisely between two north poles. The north pole structures offset with respect to the south pole structure by one pole pitch.

The step size is

WhereNs is the No. of stator polesNr is the No. of pairs of rotor poles

DEPT OF ECE 42


FIGURE: Stepper Motor Cross-sectional View

Table: Wave switching scheme

ANTICLOCKWISE CLOCKWISESTEP A1 A2 A3 A4 STEP A1 A2 A3 A4

1 1 0 0 0 1 1 0 0 02 0 0 0 1 2 0 0 1 03 0 1 0 0 3 0 1 0 04 0 0 1 0 4 0 0 0 1

8051 PROGRAMMING

1.To perform addition of two 8-bit data using 8051

MEMORY ADDRESS


4100 74 MOV A,#DATA14101 204102 24 ADD A,#DATA24103 104104 90 MOV DPTR,#45004105 454106 004107 F0 MOVX @DPTR,A4108 80 HERE: SJMP HERE4109 FE

DEPT OF ECE 43


RESULT: INPUT: DATA1=20 DATA2=10OUTPUT: [4500]=30

2. TO PERFORM SUBTRACTION OF TWO 8 BIT DATA USING 8051

MEMORY ADDRESS


4100 74 MOV A,#DATA14101 204102 94 SUBB A,#DATA24103 104104 90 MOV DPTR,#45004105 454106 004107 F0 MOVX @DPTR,A4108 80 HERE: SJMP HERE4109 FE

RESULT: INPUT: DATA1=20 DATA2=10OUTPUT: [4500]=10

3. To obtain product of two 8-bit number using 8051

MEMORY ADDRESS


4100 74 MOV A,#DATA14101 0A4102 75 MOV B,#DATA24103 F04104 884105 A4 MUL AB4106 90 MOV DPTR,#45004107 454108 004109 F0 MOVX @DPTR,A410A A3 INC DPTR410B E5 MOV A,B410C F0

410D F0 MOVX @DPTR,A

DEPT OF ECE 44


410E 80 HERE: SJMP HERE

410F FE

INPUT: DATA1:0A DATA2:88

OUTPUT: [4500] = 50 (LSB) [4501] = 05 (MSB)

4. 8 BIT DIVISION USING 8051

MEMORY ADDRESS


4100 74 MOV A,#DATA14101 654102 75 MOV B,#DATA24103 F04104 084105 84 DIV AB4106 90 MOV DPTR,#45004107 454108 004109 F0 MOVX @DPTR,A410A A3 INC DPTR

410B E5 MOV A,B

410C F0

410D F0 MOVX @DPTR,A

410E 80 HERE: SJMP HERE

410F FE

DATA: DATA1 = 65-DIVIDEND DATA2 = 08-DIVISOR

RESULT: [ 4500 ] = 0C – QUOTIENT [ 4501 ] =05 – REMAINDER

2. CODE CONVERSION2.1 HEX TO DECIMAL CONVERTION USING 8051:

DEPT OF ECE 45


MEMORY ADDRESS


4100 90 MOV DPTR,#45004101 454102 004103 E0 MOVX A,@DPTR4104 75 MOV B,#644105 F04106 644107 84 DIV AB4108 90 MOV DPTR,#45014109 45410A 01

410B F0 MOVX @DPTR,A

410C E5 MOV A,B

410D F0

410E 75 MOV B,#0A

410F F0

4110 0A

4111 84 DIV AB

4112 A3 INC DPTR

4113 F0 MOVX @DPTR,A

4114 A3 INC DPTR

4115 E5 MOV A,B

4116 F0


4118 80 HLT: SJMP HLT

4119 FE

DATA: [4500] = FF RESULT: [4501] = 02 [4502] = 05 [4503] = 05

2.2. DECIMAL TO HEX CONVERSION USING 8051

MEMORY ADDRESS


4100 90 MOV DPTR,#42004101 42

DEPT OF ECE 46


4102 004103 E0 MOVX A,@DPTR4104 75 MOV B,#0A4105 F04106 0A4107 A4 MUL AB4108 F5 MOV B,A4109 F0410A A3 INC DPTR

410B E0 MOVX A,@DPTR

410C 25 ADD A,B

410D F0

410E A3 INC DPTR

410F F0 MOVX @DPTR,A


4111 FE

DATA: [4200] = 03 [4201] = 06 RESULT: [4202] = 24

3.1 LARGEST DATA USING 8051

MEMORY ADDRESS


4100 90 MOV DPTR,#42004101 424102 004103 E0 MOVX A,@DPTR4104 F5 MOV 40H,A4105 404106 7D MOV R5,#034107 034108 A3 INC DPTR4109 E0 LOOP3: MOVX A,@DPTR410A B5 CJNE A,40H,LOOP1

410B 40

410C 08

410D A3 LOOP2: INC DPTR

410E DD DJNZ R5,LOOP3

DEPT OF ECE 47


410F F9

4110 E5 MOV A,40H

4111 40



4114 FE

4115 40 LOOP1: JC LOOP2

4116 F6

4117 F5 MOV 40H,A

4118 40

4119 80 SJMP LOOP2

411A F2

DATA: [4200] = 05 [4201] = 06 [4202] = 0F [4203] = 01RESULT: [4204] = 0F

3.2 SMALLEST DATA USING 8051

MEMORY ADDRESS


4100 90 MOV DPTR,#42004101 424102 004103 E0 MOVX A,@DPTR4104 F5 MOV 40H,A4105 404106 7D MOV R5,#034107 034108 A3 INC DPTR4109 E0 LOOP3: MOVX A,@DPTR410A B5 CJNE A,40H,LOOP1

410B 40

410C 08

410D A3 LOOP2: INC DPTR

410E DD DJNZ R5,LOOP3

410F F9

DEPT OF ECE 48


4110 E5 MOV A,40H

4111 40



4114 FE

4115 50 LOOP1: JNC LOOP2

4116 F6

4117 F5 MOV 40H,A

4118 40

4119 80 SJMP LOOP2

411A F2

DATA: [4200] = 05 [4201] = 06 [4202] = 0F [4203] = 01RESULT: [4204] = 01

4.1 ASCENDING ORDER USING 8051

MEMORY ADDRESS


4100 7B MOV R3,#44101 044102 7C MOV R4,#44103 044104 90 MOV DPTR,#45004105 454106 004107 AD REPT1: MOV R5,DPL4108 824109 AE MOV R6,DPH410A 83


410C F5 MOV B,A

410D F0

410E A3 REPT: INC DPTR

410F E0 MOVX A,@DPTR

4110 F8 MOV R0,A

DEPT OF ECE 49


4111 C3 CLR C

4112 95 SUBB A,B

4113 F0

4114 50 JNC CHKNXT

4115 13

4116 C0 EXCH: PUSH DPL

4117 82

4118 C0 PUSH DPH

4119 83

411A 8D MOV DPL,R5

411B 82

411C 8E MOV DPH,R6

411D 83

411E E8 MOV A,R0


4120 D0 POP DPH

4121 83

4122 D0 POP DPL

4123 82

4124 E5 MOV A,B

4125 F0


4127 88 MOV B,R0

4128 F0

4129 DB CHKNXT: DJNZ R3,REPT

412A E3

412B 1C DEC R4

412C EC MOV A,R4

412D FB MOV R3,A

412E 0C INC R4

412F 8D MOV DPL,R5

4130 82

4131 8E MOV DPH,R6

DEPT OF ECE 50


4132 83

4133 A3 INC DPTR

4134 DC DJNZ R4,REPT1

4135 D1


4137 FE

DATA: [4500] = 2A [4501] = 1C [4502] = F9 [ 4503] = 88 [4504] = 76RESULT: [4500] =1C [4501] = 2A [4502] =76 [ 4503] = 88 [4504] = F9

4.2 DESCENDING USING 8051MEMORY ADDRESS


4100 7B MOV R3,#44101 044102 7C MOV R4,#44103 044104 90 MOV DPTR,#45004105 454106 004107 AD REPT1: MOV R5,DPL4108 824109 AE MOV R6,DPH410A 83


410C F5 MOV B,A

410D F0

410E A3 REPT: INC DPTR

410F E0 MOVX A,@DPTR

4110 F8 MOV R0,A

4111 C3 CLR C

4112 95 SUBB A,B

4113 F0

4114 50 JC CHKNXT

DEPT OF ECE 51


4115 13

4116 C0 EXCH: PUSH DPL

4117 82

4118 C0 PUSH DPH

4119 83

411A 8D MOV DPL,R5

411B 82

411C 8E MOV DPH,R6

411D 83

411E E8 MOV A,R0


4120 D0 POP DPH

4121 83

4122 D0 POP DPL

4123 82

4124 E5 MOV A,B

4125 F0


4127 88 MOV B,R0

4128 F0

4129 DB CHKNXT: DJNZ R3,REPT

412A E3

412B 1C DEC R4

412C EC MOV A,R4

412D FB MOV R3,A

412E 0C INC R4

412F 8D MOV DPL,R5

4130 82

4131 8E MOV DPH,R6

4132 83

4133 A3 INC DPTR

4134 DC DJNZ R4,REPT1

4135 D1

DEPT OF ECE 52



4137 FE

DATA: [4500] = 2A [4501] = 1C [4502] = F9 [ 4503] = 88 [4504] = 76RESULT: [4500] =F9 [4501] =88 [4502] =76 [ 4503] =2A[4504] = 1C

5.1 AVERAGE OF N NUMBERS USING 8051

MEMORY ADDRESS


4100 90 MOV DPTR,#42004101 424102 004103 E0 MOVX A,@DPTR4104 F8 MOV R0,A4105 FA MOV R2,A4106 75 MOV B,#004107 F04108 004109 A3 INC DPTR410A E0 ADD: MOVX A,@DPTR

410B 25 ADD A,B

410C F0

410D F5 MOV B,A

410E F0

410F A3 INC DPTR

4110 D8 DJNZ R0,ADD

4111 F8

4112 E5 MOV A,B

4113 F0

4114 8A MOV B,R2

4115 F0

4116 84 DIV AB

4117 90 MOV DPTR,#4500

4118 45

4119 00

DEPT OF ECE 53


411A F0 MOVX @DPTR,A

411B 80 HLT: SJMP HLT

411C FE

DATA: [4200] = 04 --- COUNT [4201] = 03 [4202] = 04 [4203] = 06 [4204] = 03

RESULT: [4500] = 04

8085 OPCODES

HEX MNEMONIC HEX MNEMONIC HEX MNEMONIC

CE ACI 8-BIT BC CMP H 2C INR L8F ADC A BD CMP L 34 INR M88 ADC B BE CMP M . 03 INX B89 ADC C D4 CNC 16-BIT 13 INX D8A ADC D C4 CNZ 16-BIT 23 INX H8B ADC E F4 CP 16-BIT 33 INX SP8C ADC H EC CPE 16-BIT DA JC 16-BIT8D ADC L FE CPI 8-BIT FA JM 16-BIT8E ADC M E4 CPO 16-BIT C3 JMP 16-BIT87 ADD A CC CZ 16-BIT D2 JNC 16-BIT80 ADD B 27 DAA C2 JNZ 16-BIT81 ADD C . 09 DAD B F2 JP 16-BIT82 ADD D 19 DAD D EA JPE 16-BIT83 ADD E 29 DAD H E2 JPO 16-BIT84 ADD H 39 DAD SP CA JZ 16-BIT85 ADD L 3D DCR A 3A LDA 16-BIT86 ADD M . 05 DCR B 0A LDAX BC6 ADI 8-BIT 0D DCR C 1A LDAX DA7 ANA A 15 DCR D 2A LHLD 16-BITA0 ANA B 1D DCR E . 01 LXI B,16-BITA1 ANA C 25 DCR H 11 LXI D,16-BITA2 ANA D 2D DCR L 21 LXI H,16-BITA3 ANA E 35 DCR M 31 LXI SP,16-BITA4 ANA H 0B DCX B 7F MOV A,AA5 ANA L 1B DCX D 78 MOV A,BA6 ANA M 2B DCX H 79 MOV A,C

DEPT OF ECE 54


E6 ANI 8-BIT 3B DCX SP 7A MOV A,DCD CALL 16-BIT F3 DI 7B MOV A,EDC CC 16-BIT FB EI 7C MOV A,HFC CM 16-BIT 76 HLT 7D MOV A,L2F CMA DB IN 8-BIT 7E MOV A,M3F CMC 3C INR A 47 MOV B,ABF CMP A . 04 INR B 40 MOV B,BB8 CMP B 0C INR C 41 MOV B,CB9 CMP C 14 INR D 42 MOV B,DBA CMP D 1C INR E 43 MOV B,EBB CMP E 24 INR H 44 MOV B,H

HEX MNEMONIC HEX MNEMONIC HEX MNEMONIC

45 MOV B,L 6A MOV L,D D5 PUSH D46 MOV B,M 6B MOV L,E E5 PUSH H4F MOV C,A 6C MOV L,H F5 PUSH PSW48 MOV C,B 6D MOV L,L 17 RAL 49 MOV C,C 6E MOV L,M 1F RAR 4A MOV C,D 77 MOV M,A D8 RC 4B MOV C,E 70 MOV M,B C9 RET 4C MOV C,H 71 MOV M,C 20 RIM 4D MOV C,L 72 MOV M,D . 07 RLC 4E MOV C,M 73 MOV M,E F8 RM 57 MOV D,A 74 MOV M,H D0 RNC 50 MOV D,B 75 MOV M,L C0 RNZ 51 MOV D,C 3E MVI A,8-BIT F0 RP 52 MOV D,D . 06 MVI B,8-BIT E8 RPE 53 MOV D,E 0E MVI C,8-BIT E0 RPO 54 MOV D,H 16 MVI D,8-BIT 0F RRC 55 MOV D,L 1E MVI E,8-BIT C7 RST 056 MOV D,M 26 MVI H,8-BIT CF RST 15F MOV E,A 2E MVI L,8-BIT D7 RST 258 MOV E,B 36 MVI M,8-BIT DF RST 359 MOV E,C . 00 NOP E7 RST 45A MOV E,D B7 ORA A EF RST 55B MOV E,E B0 ORA B F7 RST 65C MOV E,H B1 ORA C FF RST 75D MOV E,L B2 ORA D C8 RZ 5E MOV E,M B3 ORA E 9F SBB A67 MOV H,A B4 ORA H 98 SBB B60 MOV H,B B5 ORA L 99 SBB C

DEPT OF ECE 55


61 MOV H,C B6 ORA M 9A SBB D62 MOV H,D F6 ORI 8-BIT 9B SBB E63 MOV H,E D3 OUT 8-BIT 9C SBB H64 MOV H,H E9 PCHL 9D SBB L65 MOV H,L C1 POP B 9E SBB M66 MOV H,M D1 POP D DE SBI 8-BIT6F MOV L,A E1 POP H 22 SHLD 16-BIT68 MOV L,B F1 POP PSW 30 SIM 69 MOV L,C C5 PUSH B F9 SPHL

HEX MNEMONIC

32 STA 16-BIT. 02 STAX B12 STAX D37 STC 97 SUB A90 SUB B91 SUB C92 SUB D93 SUB E94 SUB H95 SUB L96 SUB MD6 SUI 8-BITEB XCHG AF XRA AA8 XRA BA9 XRA CAA XRA DAB XRA EAC XRA HAD XRA LAE XRA MEE XRI 8-BITE3 XTHL

DEPT OF ECE 56


8051 OPCODES

HEX CODE

NUMBER OF

BYTES

MNEMONIC

OPERANDSHEX COD

E

NUMBER OF

BYTES

MNEMONIC

OPERANDS

11 2 ACALL code addr 3C 1 ADDC A,R4

31 2 ACALL code addr 3D 1 ADDC A,R5

51 2 ACALL code addr 3E 1 ADDC A,R6

71 2 ACALL code addr 3F 1 ADDC A,R7

91 2 ACALL code addr . 01 2 AJMP code addr

B1 2 ACALL code addr 21 2 AJMP code addr

D1 2 ACALL code addr 41 2 AJMP code addr

F1 2 ACALL code addr 61 2 AJMP code addr

24 2 ADD A,#DATA 81 2 AJMP code addr

25 2 ADDA,data addr A1 2

AJMPcode addr

26 1 ADD a,@R0 C1 2 AJMP code addr

27 1 ADD A,@R1 E1 2 AJMP code addr

28 1 ADD A,R0 52 2 ANL data addr,A

29 1 ADD A,R1 53 3ANL data addr,#

data

2A 1 ADD A,R2 54 2 ANL A,# data

2B 1 ADD A,R3 55 2 ANL A,data addr

2C 1 ADD A,R4 56 1 ANL A,@R0

2D 1 ADD A,R5 57 1 ANL A,@R1

2E 1 ADD A,R6 58 1 ANL A,R0

2F 1 ADD A,R7 59 1 ANL A,R1

34 2 ADDC A,#Data 5A 1 ANL A,R2

35 2 ADDC A,data 5B 1 ANL A,R3

DEPT OF ECE 57


addr

36 1 ADDC A,@R0 5C 1 ANL A,R4

37 1 ADDC A,@R1 5D 1 ANL A,R5

38 1 ADDC A,R0 5E 1 ANL A,R6

39 1 ADDC A,R1 5F 1 ANL A,R7

3A 1 ADDC A,R2 82 2 ANL C,bit addr

3B 1 ADDC A,R3 B0 2 ANL C,/bit addr

HEX COD

E

NUMBER OF BYTES

MNEMONIC OPERANDS HEX

CODE

NUMBER OF

BYTES

MNEMONIC OPERANDS

B4 3 CJNE A,# data,Code addr DA 2 DJNZ R2,code addr

B5 3 CJNEA, data addr, Code addr

DB 2 DJNZ R3,code addr

B6 3 CJNE. @R0,# data,code addr

DC 2 DJNZ R4,code addr

B7 3 CJNE. @R1,# data,code addr

DD 2 DJNZ R5,code addr

B8 3 CJNER0, # data, code addr

DE 2 DJNZ R6,code addr

B9 3 CJNER1, # data, code addr

DF 2 DJNZ R7,code addr

BA 3 CJNER2, # data, code addr

. 04 1 INC A

BB 3 CJNER3, # data, code addr

. 05 2 INC data addr

BC 3 CJNER4, # data, code addr

. 06 1 INC . @R0

BD 3 CJNER5, # data, code addr

. 07 1 INC . @R1

BE 3 CJNER6, # data, code addr

. 08 1 INC R0

BF 3 CJNER7, # data, code addr

. 09 1 INC R1

C2 2 CLR bit addr 0A 1 INC R2

C3 1 CLR C 0B 1 INC R3

E4 1 CLR A 0C 1 INC R4

B2 2 CPL bit addr 0D 1 INC R5

B3 1 CPL C 0E 1 INC R6

F4 1 CPL A 0F 1 INC R7

D4 1 DA A A3 1 INC DPTR

14 1 DEC A 20 3 JB bit addr,code addr

15 2 DEC data addr 10 3 JBC bit addr,code addr

16 1 DEC . @R0 40 2 JC code addr

17 1 DEC . @R1 73 1 JMP . @A + DPTR

18 1 DEC R0 30 3 JNB bit addr,code addr

19 1 DEC R1 50 2 JNC code addr

1A 1 DEC R2 70 2 JNZ code addr

DEPT OF ECE 58


1B 1 DEC R3 60 2 JZ code addr

1C 1 DEC R4 12 3 LCALL code addr

1D 1 DEC R5 . 02 3 LJMP code addr

1E 1 DEC R6 74 2 MOV A,#data

1F 1 DEC R7 75 3 MOV data addr,# data

84 1 DIV AB 76 2 MOV . @R0,# data

D5 3 DJNZ data addr, code addr 77 2 MOV . @R1,# data

D8 2 DJNZ R0,code addr 78 2 MOV R0,# data

D9 2 DJNZ R1,code addr 79 2 MOV R1,# data

HEX COD

E

NUMBER OF

BYTES

MNEMONIC

OPERANDSHEX COD

E

NUMBER OF

BYTES

MNEMONIC

OPERANDS

7A 2 MOV R2,# data F9 1 MOV R1,A

7B 2 MOV R3,# data FA 1 MOV R2,A

7C 2 MOV R4,# data FB 1 MOV R3,A

7D 2 MOV R5,# data FC 1 MOV R4,A

7E 2 MOV R6,# data FD 1 MOV R5,A

7F 2 MOV R7,# data FE 1 MOV R6,A

85 3 MOVdata addr,data addr

FF 1 MOV R7,A

86 2 MOV data addr,@R0 A6 2 MOV. @R0,data addr

87 2 MOV data addr,@R1 A7 2 MOV. @R1,data addr

88 2 MOV data addr,R0 A8 2 MOV R0, data addr

89 2 MOV data addr,R1 A9 2 MOV R1,data addr

8A 2 MOV data addr,R2 AA 2 MOV R2,data addr

8B 2 MOV data addr,R3 AB 2 MOV R3,data addr

8C 2 MOV data addr,R4 AC 2 MOV R4,data addr

8D 2 MOV data addr,R5 AD 2 MOV R5,data addr

8E 2 MOV data addr,R6 AE 2 MOV R6,data addr

8F 2 MOV data addr,R7 AF 2 MOV R7,data addr

90 3 MOV DPTR,#data 83 1 MOVC A,@A + PC

92 2 MOV bit addr,C 93 1 MOVC A,@A+DPTR

A2 2 MOV C,bit addr E0 1 MOVX A,@DPTR

E5 2 MOV A,data addr E2 1 MOVX A,@R0

E6 1 MOV A,@R0 E3 1 MOVX A,@R1

E7 1 MOV A,@R1 F0 1 MOVX . @DPTR,A

E8 1 MOV A,R0 F2 1 MOVX . @R0,A

E9 1 MOV A,R1 F3 1 MOVX . @R1,A

EA 1 MOV A,R2 A4 1 MUL AB

DEPT OF ECE 59


EB 1 MOV A,R3 . 00 1 NOP

EC 1 MOV A,R4 42 2 ORL data addr,A

ED 1 MOV A,R5 43 3 ORLdata addr,#data

EE 1 MOV A,R6 44 2 ORL A,#data

EF 1 MOV A,R7 45 2 ORL A,Data addr

F5 2 MOV data addr,A 46 1 ORL A,@R0

F6 1 MOV . @R0,A 47 1 ORL A,@R1

F7 1 MOV . @R1,A 48 1 ORL A,R0

F8 1 MOV R0,A 49 1 ORL A,R1

HEX COD

E

NUMBER OF

BYTES

MNEMONIC

OPERANDSHEX COD

E

NUMBER OF

BYTES

MNEMONIC

OPERANDS

4A 1 ORL A,R2 C8 1 XCH A,R0

4B 1 ORL A,R3 C9 1 XCH A,R1

4C 1 ORL A,R4 CA 1 XCH A,R2

4D 1 ORL A,R5 CB 1 XCH A,R3

4E 1 ORL A,R6 CC 1 XCH A,R4

4F 1 ORL A,R7 CD 1 XCH A,R5

72 2 ORL C,bit addr CE 1 XCH A,R6

A0 2 ORL C,/bit addr CF 1 XCH A,R7

D0 2 POP data addr D6 1 XCHD A,@R0

C0 2 PUSH data addr D7 1 XCHD A,@R1

22 1 RET 62 2 XRL data addr,A

32 1 RETI 63 3 XRLdata addr,# data

23 1 RL A 64 2 XRL A,# data

33 1 RLC A 65 2 XRL A,data addr

. 03 1 RR A 66 1 XRL A,@R0

13 1 RRC A 67 1 XRL A,@R1

D2 2 SETB bit addr 68 1 XRL A,R0

D3 1 SETB C 69 1 XRL A,R1

80 2 SJMP code addr 6A 1 XRL A,R2

94 2 SUBB A,# data 6B 1 XRL A,R3

95 2 SUBB A,data addr 6C 1 XRL A,R4

96 1 SUBB A,@R0 6D 1 XRL A,R5

97 1 SUBB A,@R1 6E 1 XRL A,R6

98 1 SUBB A,R0 6F 1 XRL A,R7

99 1 SUBB A,R1 A5 RESERVED

9A 1 SUBB A,R2

9B 1 SUBB A,R3

DEPT OF ECE 60


9C 1 SUBB A,R4

9D 1 SUBB A,R5

9E 1 SUBB A,R6

9F 1 SUBB A,R7

C4 1 SWAP A

C5 2 XCH A,data addr

C6 1 XCH A,@R0

C7 1 XCH A,@R1

DEPT OF ECE 61

Documents

8085 Programming[1]