5V/12V eFuse with Overvoltage Protection and Blocking … · TPS2592Ax TPS2592Bx SLVSC11A – JUNE 2013– REVISED JUNE 2013 5V/12V eFuse with Over Voltage Protection and Blocking

TPS2592AxTPS2592Bx

www.ti.com SLVSC11A –JUNE 2013–REVISED JUNE 2013

5V/12V eFuse with Over Voltage Protection and Blocking FET ControlCheck for Samples: TPS2592Ax, TPS2592Bx

1FEATURES DESCRIPTIONThe TPS2592xx family of eFuses are highly• 12V Protection – TPS2592Axintegrated circuit protection and power management

• 5V Protection – TPS2592Bx solutions in a tiny package. With few external• Integrated 28mΩ Pass MOSFET components and multiple protection modes, they are

a robust defense against overloads, shorts circuits,• Absolute Maximum Voltage of 20Vvoltage surges, excessive inrush current, and reverse• Programmable Current Limit (±15% Accuracy) current. Only one external resistor is required for

• Blocking FET Driver setting the current limit level, which has a typicalaccuracy of ±15%. Over voltage events are limited by• Fixed Over Voltage Settinginternal clamping circuits to a safe fixed maximum,• Programmable OUT Slew Rate, UVLOwith no external components required. TPS2592Ax

• Built-in Thermal Shutdown devices provide over voltage protection (OVP) for12V systems and TPS2592Bx devices for 5V• UL Recognition Pendingsystems. In cases with particular voltage ramp• Safe during Single Point Failure Testrequirements, a dV/dT pin is provided that can be(UL60950)programmed with a single capacitor to ensure proper

• Small Foot Print – 10L (3mm x 3mm) VSON output ramp rates. Many systems, such as SSDs,must not allow holdup capacitance energy to dump

APPLICATIONS back through the FET body diode onto a drooping orshorted bus. The BFET pin is for such systems. An• HDD and SSD Drivesexternal NFET can be connected “back to back” with

• Set Top Boxes the TPS2592xx output and the gate driven by BFET.When the TPS2592xx is disabled, then current flow is• Servers / AUX Suppliesstopped in both directions. TPS2592xL parts will latch• Fan Controloff after a fault and TPS2592xA parts will attempt to

• PCI/PCIe Cards restart after the thermal shutoff resets.• Switches/Routers

Transient: Output Short CircuitApplication Schematic

PRODUCT INFORMATIONPART NUMBER UVLO OVERVOLTAGE CLAMP (TYP) FAULT RESPONSE STATUS

TPS2592AA 4.3 V 15.0 V Auto Retry Active

TPS2592BA 4.3 V 6.1 V Auto Retry Preview

TPS2592AL 4.3 V 15.0 V Latched Preview

TPS2592BL 4.3 V 6.1 V Latched Active

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 2013, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

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TPS2592AxTPS2592BxSLVSC11A –JUNE 2013–REVISED JUNE 2013 www.ti.com

ORDERING INFORMATION (1)

PART NUMBER PART MARKING PACKAGE

TPS2592ALDRC 2592AL 10-pin DRC

TPS2592AADRC 2592AA 10-pin DRC

TPS2592BLDRC 2592BL 10-pin DRC

TPS2592BADRC 2592BA 10-pin DRC

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com.

ABSOLUTE MAXIMUM RATINGSover operating free-air temperature range (unless otherwise noted) (1)

VALUE (2)

UNITMIN MAX

VIN –0.3 20Supply voltage range (3) V

VIN (10ms Transient) 22

Output voltage OUT –0.3 VIN + 0.3 V

ILIM –0.3 7 V

EN/UVLO –0.3 7 V

dV/dT –0.3 7 V

BFET –0.3 30 V

Human body model (4) ±2000 VElectrostatic discharge

Charged-device model (5) ±500 V

Continuous power dissipation See Thermal Characteristics

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditionsis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential voltages, are with respect to network ground terminal.(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B(4) Tested in accordance with JEDEC Standard 22, Test Method C101-A(5) Tested in accordance with JEDEC Standard 22, Test Method A115-A

THERMAL CHARACTERISTICS (1)

TPS2592xxTHERMAL METRIC UNIT

DRC (10) PINS

θJA Junction-to-ambient thermal resistance 45.9

θJCtop Junction-to-case (top) thermal resistance 53

θJB Junction-to-board thermal resistance 21.2°C/W

ψJT Junction-to-top characterization parameter 1.2

ψJB Junction-to-board characterization parameter 21.4

θJCbot Junction-to-case (bottom) thermal resistance 5.9

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated

Product Folder Links: TPS2592Ax TPS2592Bx



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TPS2592AxTPS2592Bx


RECOMMENDED OPERATING CONDITIONSover operating free-air temperature range (unless otherwise noted)

MIN TYP MAX UNIT

VIN TPS2592Ax 4.5 12 13.8

VIN TPS2592Bx 4.5 5 5.5

Input voltage range BFET 0 VIN+6 V

dV/dT, EN/UVLO 0 6

ILIM 0 3.3

Resistance ILIM 40.2 100 162 kΩOUT 0.1 1 1000 µF

External capacitancedV/dT 1 1000 nF

Operating junction temperature range, TJ –40 25 125 °C

Operating Ambient temperature range, TA –40 25 85 °C

ELECTRICAL CHARACTERISTICS–40°C ≤ TJ ≤ 125°C, VIN = 12V for TPS2592Ax, VIN = 5V for TPS2592Bx, VEN/UVLO = 2V, RILIM = 100kΩ, CdVdT = OPEN. Allvoltages referenced to GND (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIN (INPUT SUPPLY)

VUVR UVLO threshold, rising 4.15 4.3 4.45 V

VUVhyst UVLO hysteresis 5.4%

Enabled: EN/UVLO = 2V, TPS2592AX 0.2 0.42 0.65 mAIQON

Supply current Enabled: EN/UVLO = 2V, TPS2592Bx 0.4 0.62 0.80 mA

IQOFF EN/UVLO = 0V 0.1 0.25 mA

VIN > 16.5V, IOUT = 10mA, TPS2592Ax 13.8 15 16.5

TPS2592Bx, VIN > 6.75V, IOUT = 10 mA,5.5 6.1 6.75

VOVC Over-voltage clamp –40 ≤ TJ ≤ 85 V

TPS2592Bx, VIN > 6.75V, IOUT = 10 mA,5.25 6.1 6.75

–40 ≤ TJ ≤ 125EN/UVLO (ENABLE/UVLO INPUT)

VENR EN Threshold voltage, rising 1.37 1.4 1.44 V

VENF EN Threshold voltage, falling 1.32 1.35 1.39 V

IEN EN Input leakage current 0 V ≤ VEN ≤ 5V –100 0 100 nA

TOFFdly Turn Off delay EN↓ to BFET↓, CBFET = 0 0.4 µs

dV/dT (OUTPUT RAMP CONTROL)

TPS2592Ax, EN/UVLO → H to OUT = 11.7V, CdVdT = 0 0.7 1 1.3

TPS2592Bx, EN/UVLO → H to OUT = 4.9V, CdVdT = 0 0.28 0.4 0.52

TPS2592Ax, EN/UVLO → H to OUT = 11.7V,TdVdT Output ramp time ms12CdVdT = 1 nF

TPS2592Bx, EN/UVLO → H to OUT = 4.9V,5

CdVdT = 1 nF

IdVdT dV/dT Charging current VdVdT = 0 V 220 nA

RdVdT_disch dV/dT Discharging resistance EN/UVLO = 0 V, IdVdT = 10 mA sinking 50 73 100 Ω

VdVdTmax dV/dT Max capacitor voltage 5.5 V

GAINdVdT dV/dT to OUT gain ΔVdVdT 4.85 V/V

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ELECTRICAL CHARACTERISTICS (continued)–40°C ≤ TJ ≤ 125°C, VIN = 12V for TPS2592Ax, VIN = 5V for TPS2592Bx, VEN/UVLO = 2V, RILIM = 100kΩ, CdVdT = OPEN. Allvoltages referenced to GND (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ILIM (CURRENT LIMIT PROGRAMMING)

IILIM ILIM Bias current 10 µA

RILIM = 45.3 kΩ, VVIN-OUT = 1 V 1.79 2.10 2.42

IOL RILIM = 100 kΩ, VVIN-OUT = 1 V 3.46 3.75 4.03 A

RILIM = 150 kΩ, VVIN-OUT = 1 V 4.4 5.2 6Overload current limit

RILIM = 0 Ω, Shorted Resistor Current Limit (Single PointIOL-R-Short 0.7 AFailure Test: UL60950)

RILIM = OPEN, Open Resistor Current Limit (Single PointIOL-R-Open 0.55 AFailure Test: UL60950)

RILIM = 45.3 kΩ, VVIN-OUT = 5 V, TPS2592Bx 1.72 2.05 2.38

RILIM = 45.3 kΩ, VVIN-OUT = 12 V, TPS2592Ax 1.66 1.98 2.29

RILIM = 100 kΩ, VVIN-OUT = 5 V, TPS2592Bx 3.14 3.56 3.98ISCL Short-circuit current limit A

RILIM = 100 kΩ, VVIN-OUT = 12 V, TPS2592Ax 2.90 3.32 3.75

RILIM = 150 kΩ, VVIN-OUT = 5 V, TPS2592Bx 4.12 4.86 5.60

RILIM = 150 kΩ, VVIN-OUT = 12 V, TPS2592Ax 3.75 4.42 5.10

Fast-Trip comparator level w.r.t.RATIOFASTRIP IFASTRIP : IOL 160%overload current limit

TFastOffDly Fast-Trip comparator delay IOUT > IFASTRIP 3 µs

VOpenILIM ILIM Open resistor detect threshold VILIM Rising, RILIM = OPEN 3.1 V

OUT (PASS FET OUTPUT)

TON Turn-on delay EN/UVLO → H to IVIN = 100mA, 1A resistive load at OUT 220 µs

TJ = 25°C 21 28 33RDSon FET ON resistance mΩ

TJ = 125°C (1) 39 46

IOUT-OFF-LKG VEN/UVLO = 0 V, VOUT = 0 V (Sourcing) –5 0 1OUT Bias current in off state µA

IOUT-OFF-SINK VEN/UVLO = 0V, VOUT = 300 mV (Sinking) 10 15 20

BFET (BLOCKING FET GATE DRIVER)

IBFET BFET Charging current VBFET = VOUT 2 µA

VBFETmax BFET Clamp voltage VVIN+6.4 V

RBFETdisch BFET Discharging resistance VEN/UVLO = 0 V, IBFET = 100 A 15 26 36 Ω

EN/UVLO → H to VBFET = 12 V, CBFET = 1 nF 4.2TBFET-ON BFET Turn-on duration ms

EN/UVLO → H to VBFET = 12 V, CBFET = 10 nF 42

EN/UVLO → L to VBFET = 1 V, CBFET = 1 nF 0.4TBFET-OFF BFET Turn-off duration µs

EN/UVLO → L to VBFET = 1 V, CBFET = 10 nF 1.4

TSD (THERMAL SHUT DOWN)

TSHDN TSD Threshold, rising (1) 160 °C

TSHDNhyst TSD Hysteresis (1) 10 °C

TPS2592xL LATCHEDThermal fault: latched or autoretry AUTO-TPS2592xA RETRY

(1) The limits for these parameters are specified based on characterization data, and are not tested during production.





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14.5

15

15.5

16

-50 0 50 100 150

VO

VC (

V)

Temperature (C)

10 mA

100 mA

500 mA

C005

5.4

5.6

5.8

6

6.2

6.4

6.6

-50 0 50 100 150

VO

VC

(v)

Temperature (oC)

10 mA

0

0.1

0.2

0.3

0.4

0.5

0.6

0 5 10 15 20

I VIN

-ON (

mA

)

VIN (V)

125 °C85 °C25 °C-40 °C

C003

0

0.2

0.4

0.6

0.8

1

0 5 10 15 20

I VIN

-ON (

mA

)

VIN (V)

125 °C85 °C25 °C-40 °C

C004

4

4.05

4.1

4.15

4.2

4.25

4.3

4.35

-50 0 50 100 150

VU

VLO

(R

isin

g, F

allin

g) (

V)

Temperature (C) C001

0

0.05

0.1

0.15

0.2

0.25

0 5 10 15 20

I VIN

-OF

F (

mA

)

VIN (V)

125 °C85 °C25 °C-40 °C

C002

TPS2592AxTPS2592Bx


TYPICAL CHARACTERISTICSTJ = 25°C, VVIN = 12 V for TPS2592Ax, VVIN = 5 V for TPS2592Bx, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN=0.1 µF, COUT=1µF,

CdVdT = OPEN (unless stated otherwise)

Figure 1. VUVLO vs TEMPERATURE Figure 2. IVIN-OFF vs VIN ACROSS TEMPERATURE

Figure 3. IVIN-ON vs VIN ACROSS TEMPERATURE Figure 4. IVIN-ON vs VIN ACROSS TEMPERATURE(TPS2592Ax) (TPS2592Bx)

Figure 5. VOVC vs TEMPERATURE ACROSS IOUT Figure 6. VOVC vs TEMPERATURE(TPS2592Ax) (TPS2592Bx)





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1.02

1.03

1.04

1.05

1.06

1.07

-50 0 50 100 150

TdV

dT (

nA)


0.415

0.42

0.425

0.43

0.435

0.44

0.445

0.45

-50 0 50 100 150

TdV

dT (

nA)


205

210

215

220

225

230

-50 0 50 100 150

I dV

dT (

nA)


150

170

190

210

230

250

-50 0 50 100 150

TO

N(P

S)

Temperature (oC)


TYPICAL CHARACTERISTICS (continued)TJ = 25°C, VVIN = 12 V for TPS2592Ax, VVIN = 5 V for TPS2592Bx, VEN/UVLO = 2 V, RILIM = 100 kΩ, CVIN=0.1 µF, COUT=1µF,CdVdT = OPEN (unless stated otherwise)

Figure 7. TRANSIENT: OVER-VOLTAGE CLAMP: Figure 8. TRANSIENT: OVER-VOLTAGE CLAMP:TPS2592Ax TPS2592Bx

Figure 9. TON vs TEMPERATURE Figure 10. IdVdT vs TEMPERATURE

Figure 11. TdVdT vs TEMPERATURE (TPS2592Ax) Figure 12. TdVdT vs TEMPERATURE (TPS2592Bx)





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0.1

1

10

100

0 1 2 3 4 5

I EN

(nA

)

VEN (V)

125C 85C 25C -40C

1.34

1.35

1.36

1.37

1.38

1.39

1.4

1.41

-50 0 50 100 150

VE

N-V

IH V

EN

-VIL

(V

)

Tiemperature (oC)

Rising

Falling

0

50

100

150

0 2 4 6 8 10

TdV

dT (

mS

)

CdVdT (nF)

125 °C85 °C25 °C-40 °C

C013

0

10

20

30

40

50

60

0 2 4 6 8 10

TdV

dT (

mS

)

CdVdT (nF)

125 °C85 °C25 °C-40 °C

C014

TPS2592AxTPS2592Bx



Figure 13. TdVdT vs CdVdT (TPS2592Ax) Figure 14. TdVdT vs CdVdT (TPS2592Bx)

Figure 15. VEN_VIH, VEN_VIL vs TEMPERATURE Figure 16. IEN (Leakage Current) vs VEN

Figure 17. TRANSIENT: OUTPUT RAMP (CdVdT = OPEN): Figure 18. TRANSIENT: OUTPUT RAMP (CdVdT = 1 nF):TPS2592Ax TPS2592Ax





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Figure 19. TRANSIENT: OUTPUT RAMP (CdVdT = OPEN): Figure 20. Transient Output Ramp (CdVdT = 1 nF, COUT=10TPS2592Bx µF, ROUT= 2.5 Ω) : TPS2592Bx

Figure 21. TRANSIENT: TURN OFF DELAY (EN ↓) Figure 22. TURN OFF DELAY TO BFET (EN↓)

Figure 23. TURN OFF DELAY TO BFET (VIN↓) Figure 24. TRANSIENT: TURN OFF DELAY TO BFET (VIN↓)





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1

1.2

1.4

1.6

1.8

2

2.2

0 0.5 1 1.5 2

I VO

UT

(A

)

VVIN-VOUT (V)

125C 85C 25C -40C

RILIM = 45.3 k:

-16

-14

-12

-10

-8

-6

-4

-2

0

2

-50 0 50 100 150

I OL,

I SC

(%

Nor

mal

ized

)

Temperature (oC)

IOL-150k

ISC-150K-92B_

ISC-150K-92A_

1

2

3

4

5

6

0 0.5 1 1.5 2

I VO

UT

(A

)

VVIN-VOUT (V)

125C 85C 25C -40C

RILIM = 150 k:

1

1.5

2

2.5

3

3.5

4

0 0.5 1 1.5 2

I VO

UT

(A

)

VVIN-VOUT (V)

125C 85C 25C -40C

RILIM = 100 k:

0

0.005

0.01

0.015

0.02

-40 10 60 110

VO

UT

-OF

F (

V)

Temperature (oC)

20

25

30

35

40

45

-50 0 50 100 150

RD

SO

N (

m:

)

Temperature (oC)

TPS2592AxTPS2592Bx



Figure 25. VOUT-OFF vs TEMPERATURE Figure 26. RDSON vs TEMPERATURE

Figure 27. IOUT vs VVIN-OUT ACROSS TEMPERATURE Figure 28. IOUT vs VVIN-OUT ACROSS TEMPERATURE(150kΩ) (100kΩ)

Figure 29. IOUT vs VVIN-OUT ACROSS TEMPERATURE Figure 30. IOL, ISC vs TEMPERATURE(45.3kΩ) (150kΩ)





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3.05

3.06

3.07

3.08

3.09

3.1

-50 0 50 100 150

ILIM

Ope

n D

etec

t Thr

esho

ld (

V)

Temperature (oC)

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

-50 0 50 100 150

I OL-

R-S

HO

RT

(A

)

Temperature (oC)

0.5

0.51

0.52

0.53

0.54

0.55

0.56

0.57

0.58

-50 0 50 100 150

I OL-

R-O

PE

N (

A)

Temperature (oC)

-12

-10

-8

-6

-4

-2

0

2

-50 0 50 100 150

I OL,

I SC

(%

Nor

mal

ized

)

Temperature (oC)

IOL-100K

ISC-100K-92B_

ISC-100K-92A_

-6

-5

-4

-3

-2

-1

0

1

-50 0 50 100 150

I OL,

I SC

(%

Nor

mal

ized

)

Temperature (oC)

IOL-45.3k

ISC-45.3K-92B_

ISC-45.3K-92A_



Figure 31. IOL, ISC vs TEMPERATURE (100kΩ) Figure 32. IOL, ISC vs TEMPERATURE (45.3kΩ)

Figure 33. IOL-R-Short vs TEMPERATURE (RILIM = 0) Figure 34. IOL-R-Open vs TEMPERATURE (RILIM = OPEN)

Figure 35. VOpenILIM vs TEMPERATURE Figure 36. TRANSIENT: OUTPUT SHORT CIRCUIT





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TPS2592AxTPS2592Bx



Figure 37. SHORT CIRCUIT (Zoom): FAST-TRIP Figure 38. TRANSIENT: RECOVERY FROM SHORT CIRCUITCOMPARATOR

Figure 39. TRANSIENT: WAKE UP TO SHORT CIRCUIT Figure 40. TRANSIENT: OVERLOAD CURRENT LIMIT:(ILOAD stepped from 50% to 120%, back to 50%)

Figure 41. TRANSIENT: THERMAL FAULT AUTO-RETRY Figure 42. TRANSIENT: THERMAL FAULT LATCHED(TPS2592xA) (TPS2592xL)





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GND

dV/dT

VIN

EN/UVLO

ILIM

BFET

OUT

OUT

OUT

VIN

VIN

1

5 6

10

3,

4,

5

VIN

2

EN/

UVLO +1.4V

1.35V

4.3V

4.08V

+ UVLO

EN

TSD

220nA

70pF

6V

SWEN

4.8x

80W

10

ILIM

+

VIN

+

+

ILIMIT

1.6*ILIMIT

10 Am

6V

GATE

CONTROL

Charge

Pump

Over

Voltage

Thermal

ShutDown

6,

7,

8

28mW

BFET

9

SWEN

22W

2 Am

SWEN

Current

Sense

1

dV/dT

EP

GND

OUT

Fast Trip

Comp


FUNCTIONAL BLOCK DIAGRAM

DRC PACKAGE(TOP VIEW)

PIN DESCRIPTIONSPIN

DESCRIPTIONNAME NO.

SUPPLY PINS

VIN 3-5 Input Supply Voltage

GND Power Pad GND

CONTROL PINS

dV/dT 1 Tie a capacitor from this pin to GND to control the ramp rate of OUT at device turn-on.

EN/UVLO This is a dual function control pin. When used as an ENABLE pin and pulled down, it shuts off the internal passMOSFET and pulls BFET to GND. When pulled high, it enables the device and BFET.2As an UVLO pin, it can be used to program different UVLO trip point via external resistor divider.

Connect this pin to the gate of a blocking NFET. See detailed pin description and application note in thisBFET 9 datasheet.

ILIM 10 A resistor from this pin to GND will set the overload and short circuit limit.

LOAD PINS

OUT 6-8 Output of the device





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( )6dVdT EXTT 1 0 VIN C 70 pF= ´ ´ +

OUTdVDesired output slew rate

dT=

( )OUT

dVdT EXT INT

dVdT

dV

dTI C C

GAIN

æ öç ÷è ø= + ´

TPS2592AxTPS2592Bx


DEVICE OPERATION

The TPS2592xx is a hot-swap controller with integrated power switch that is used to managecurrent/voltage/start-up voltage ramp to a connected load. The device starts its operation by monitoring the VINbus. When VIN exceeds the undervoltage threshold (VUVLO), the device samples the EN/UVLO pin. A high levelon this pin will enable the internal MOSFET and also start charging the gate of external blocking FET (ifconnected) via the BFET pin. As VIN rises, the internal MOSFET of the device and external FET (if connected)will start conducting and allow current to flow from VIN to OUT. When EN/UVLO is held low (i.e., below VENF),the internal MOSFET is turned off and BFET pin is discharged, thereby blocking the flow of current from VIN toOUT. User also has the ability to modify the output voltage ramp time by connecting a capacitor between dV/dTpin and GND.

Having successfully completed its start-up sequence, the device now actively monitors its load current and inputvoltage, ensuring that the adjustable overload current limit IOL is not exceeded and input voltage spikes are safelyclamped to VOVC level at the output. This keeps the output device safe from harmful voltage and currenttransients. The device also has built-in thermal sensor. In the event device temperature (TJ) exceeds TSHDN ,typically 160°C, the thermal shutdown circuitry will shut down the internal MOSFET thereby disconnecting theload from the supply. In the TPS2592xL, the output will remain disconnected (MOSFET open) until power todevice is recycled or EN/UVLO is toggled (pulled low and then high). The TPS2592xA device will remain offduring a cooling period until device temperature falls below TSHDN – 10°C, after which it will attempt to restart.This ON and OFF cycle will continue until fault is cleared.

DETAILED PIN DESCRIPTION

GND: This is the most negative voltage in the circuit and is used as a reference for all voltage measurementsunless otherwise specified.

VIN: Input voltage to the TPS2592xx. A ceramic bypass capacitor close to the device from VIN to GND isrecommended to alleviate bus transients. The recommended operating voltage range is 4.5V – 13.8V forTPS2592Ax and 4.5V – 5.5V for TPS2592Bx. The device can continuously sustain a voltage of 20V on VIN pin.However, above the recommended maximum bus voltage, the device will be in over-voltage protection (OVP)mode, limiting the output voltage to VOVC. The power dissipation in OVP mode is PD_OVP = (VVIN - VOVC)*IOUT,which can potentially heat up the device and cause thermal shutdown.

dV/dT: Connect a capacitor from this pin to GND to control the slew rate of the output voltage at power-on. Thispin can be left floating to obtain a predetermined slew rate (minimum TdVdT) on the output. Equation governingslew rate at start-up is shown below:

(1)

Where:IdVdT = 220 nA (TYP)CINT = 70pF (TYP)GAINdVdT = 4.85

The total ramp time (TdVdT) for 0 to VIN can be calculated using the following equation:

(2)

For details on how to select an appropriate charging time/rate, refer to the applications section: "INRUSHCURRENT AND POWER DISSIPATION DURING START-UP".

BFET: Connect this pin to an external NFET that can be used to disconnect input supply from rest of the systemin the event of power failure at VIN. BFET pin is controlled by either UVLO event or EN/UVLO (see table below).BFET can source charging current of 2µA (TYP) and sink (discharge) current from the gate of the external FETvia a 26Ω internal discharge resistor to initiate fast turn-off, typically <1 µs.





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Power (W)

0 6010 20 30 40 50

0

-14

-2

-4

-6

-8

-10

-12

Fo

ldb

ack (

I-

I)/

I(%

)S

CO

LO

L

( )5

OL ILIMI 0.7 3 10 R-= + ´ ´


EN/UVLO > VENR VIN>VUVR BFET Mode

H H Charge

X L Discharge

L X Discharge

EN/UVLO: As an input pin, it controls both the ON/OFF state of the internal MOSFET and that of the externalblocking FET. In its high state, the internal MOSFET is enabled and charging begins for the gate of external FET.A low on this pin will turn off the internal MOSFET and pull the gate of the external FET to GND via the built-indischarge resistor. High and Low levels are specified in the parametric table of the datasheet. The EN/UVLO pinis also used to clear a thermal shutdown latch in the TPS2592xL by toggling this pin (H→L).

The internal de-glitch delay on EN/UVLO falling edge is intentionally kept low (1us typical) for quick detection ofpower failure. When used with a resistor divider from supply to EN/UVLO to GND, power-fail detection onEN/UVLO helps in quick turn-off of the BFET driver, thereby stopping the flow of reverse current (see typicalapplication diagram, Figure 47). For applications where a higher de-glitch delay on EN/UVLO is desired, or whenthe supply is particularly noisy, it is recommended to use an external bypass capacitor from EN/UVLO to GND

ILIM: The device continuously monitors the load current and keeps it limited to the value programmed by RILIM.After start-up event and during normal operation, current limit is set to IOL (over-load current limit).

(3)

When power dissipation in the internal MOSFET [PD = (VVIN -VOUT) × IOUT] exceeds 10W, there is a 2% – 12%thermal foldback in the current limit value so that IOL drops to ISC. In each of the two modes, MOSFET gatevoltage is regulated to throttle short-circuit and overload current flowing to the load. Eventually, the device shutsdown due to over temperature.

Figure 43. Thermal Foldback in Current Limit

During a transient short circuit event, the current through the device increases very rapidly. The current-limitamplifier cannot respond very quickly to this event due to its limited bandwidth. Therefore, the TPS2592incorporates a fast-trip comparator, which shuts down the pass device very quickly when IOUT > IFASTRIP, andterminates the rapid short-circuit peak current. The trip threshold is set to 60% higher than the programmed over-load current limit (IFASTRIP = 1.6 x IOL). After the transient short-circuit peak current has been terminated by thefast-trip comparator, the current limit amplifier smoothly regulates the output current to IOL (see figure below).





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TPS2592AxTPS2592Bx


Figure 44. Fast-Trip Current Figure 45. Fast-Trip and Current Limit AmplifierResponse for Short Circuit





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TYPICAL APPLICATIONS

Figure 46. Simple e-Fuse (Current-Limiter): Application with Output Ramp-Rate Control

Figure 47. Reverse Current Protection (e.g., SSD) Application with Blocking FET CHOLD-UP(TPS2592 UVLO is used as power fail comparator)

Figure 48. Reverse Current Protection Application with External Blocking Controller(TPS2413 is used as reverse current comparator)





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Tdvdt

VINTdvdt VIN

dvdt L dvdt

0

Vt tW V (1 ) dt

T R T

æ ö= ´ - ´ ´ç ÷

è øò

( ) VINLOAD

L dvdt

V tI t

R T

æ ö= ´ç ÷

è ø

DS VINdvdt

tV (t) V 1

T

æ ö= ´ -ç ÷

è ø

INRUSH VIN INRUSHP 0.5 V I= ´ ´

VININRUSH OUT

dvdt

VdvI C I C

dt T= ´ => = ´

TPS2592AxTPS2592Bx


APPLICATION INFORMATION

INRUSH CURRENT AND POWER DISSIPATION DURING START-UP

A successful design needs to keep the junction temperature of TPS2592 well below the absolute-maximumrating during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order ofmagnitude greater than the static stresses, so it is important to determine the right start-up time and in-rushcurrent limit required with system capacitance to avoid thermal shutdown during start-up.

During start-up, as the output capacitor charges, the voltage difference across the internal FET decreases, andthe power dissipated decreases as well. Typical ramp-up of output voltage VOUT with inrush current limit is shownin Figure 49 and variation of power dissipation with ramp-up time is plotted in Figure 50. The average powerdissipated in the device during start-up is equal to area of triangular plot as highlighted.

Figure 49. Start-Up Waveform Figure 50. PDISS During Start-Up

For the TPS2592, the inrush current is determined as:

(4)

Power dissipation during start-up will be:

(5)

The above calculation assumes that load does not draw any current until the output voltage has reached its finalvalue.

If the load draws current during the turn-on sequence, there will be additional power dissipated during the start-up phase. Considering a resistive load RL, load current ramps up proportionally with increase in output voltageduring Tdvdt time. Typical ramp-up of output voltage VOUT and Load current is shown in Figure 51 and variation ofpower dissipation with ramp-up time is plotted in Figure 52. The additional power dissipation during start-upphase is represented and calculated as follows:

(6)

(7)

Average energy loss due in FET during charging time due to resistive load is given by:

(8)





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VINdvdt _ min OUT

LIM

VT C

I= ´

STARTUP INRUSH LOADI I I (t)= +

STARTUP INRUSH DISS _LOADP P P= +

2VIN

DISS _LOADL

V1P

6 R

æ ö= ´ç ÷

è ø


Figure 51. Start-up Waveform with Load (2.5W) Figure 52. PDISS During Due to Load Current

Linearizing the parabolic equation and representing as triangle, the average power loss is:

(9)

Total power dissipated in the device during startup is:

(10)

Total current during startup is given by:

(11)

If ISTARTUP > ILIM, the device limits the current to ILIM and the minimum charging time is determined by:

(12)

Power dissipation for a selected start-up time should not exceed the limits shown in below plots as shaded area.Typical curves for no load and load are shown in Figure 53 and Figure 54.

Figure 53. IINRUSH SOA Variation with COUT and Tdvdt Figure 54. IINRUSH SOA Variation with COUT and Tdvdt(NO Load) (with Load)





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STARTUPP (5.22 2.00) 7.22 W= + =

( )DISS _LOAD

12 121P 2.00 W

6 12

æ ö´æ ö= ´ =ç ÷ç ÷ ç ÷è ø è ø

INRUSHP 0.5 12 0.87 5.22 W= ´ ´ =

( )( 6)INRUSH ( 3)

12I 470 10 0.87A

6.48 10

--

æ ö= ´ ´ =ç ÷

´è ø

( )6dvdtT 1 0 12 470pF 70pF 6.48 ms= ´ ´ + =

STARTUPP (16.584 2.00) 18.84 W= + =

( )DISS _LOAD

12 121P 2.00 W

6 3

æ ö´æ ö= ´ =ç ÷ç ÷ ç ÷è ø è ø

INRUSHP 0.5 12 2.764 16.584 W= ´ ´ =

( )6

INRUSH 3

12I 470 10 2.764 A

2.04 10

--

æ ö= ´ ´ =ç ÷

´è ø

( )6dvdtT 1 0 12 100pF 70pF 2.04 ms= ´ ´ + =

TPS2592AxTPS2592Bx


Example:VVIN = 12V, COUT = 470uF, and Load: RL = 12ΩAs a first choice, let CEXT = CdVdT = 3.3nF:

(13)

(14)

(15)

(16)

(17)

The power dissipated is well above the shaded area of power dissipation graph; to have safe operating powerarea, increase the capacitance

As a second choice, let CEXT = CdVdT = 0.47 nF:

(18)

(19)

(20)

(21)

(22)

The power dissipated is well below the shaded area of the power dissipation graph. The following table illustratesthe acceptability for different CdVdT capacitances.

Capacitance CdVdT (nF) 0.10 0.47 3.30 27.0

Charging Time Tdvdt (ms) 2.0 6.5 40.5 325

Power Dissipation (W) 18.84 7.22 2.84 2.10

Limits Not OK OK OK Not OK





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REVISION HISTORY

Changes from Original (June 2013) to Revision A Page

• Changed from Product Preview to Production Data ............................................................................................................. 1





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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TPS2592AADRCR ACTIVE SON DRC 10 3000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2592AA

TPS2592AADRCT ACTIVE SON DRC 10 250 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2592AA

TPS2592BLDRCR ACTIVE SON DRC 10 3000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2592BL

TPS2592BLDRCT ACTIVE SON DRC 10 250 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2592BL

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

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PACKAGE OPTION ADDENDUM

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Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

TPS2592AADRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

TPS2592AADRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

TPS2592BLDRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

TPS2592BLDRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS2592AADRCR SON DRC 10 3000 367.0 367.0 35.0

TPS2592AADRCT SON DRC 10 250 210.0 185.0 35.0

TPS2592BLDRCR SON DRC 10 3000 367.0 367.0 35.0

TPS2592BLDRCT SON DRC 10 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

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Documents

5V/12V eFuse with Overvoltage Protection and Blocking … · TPS2592Ax TPS2592Bx SLVSC11A – JUNE 2013– REVISED JUNE 2013 5V/12V eFuse with Over Voltage Protection and Blocking