5.5 GHz 802.11a 0.18mm CMOS pre-power amplifiercore with on-chip linearisation

B. Toner, R. Dharmalinggam and V.F. Fusco

Abstract: This paper details the development of a 0.18mm CMOS based amplifier core for the802.11a standard. The amplifier core operates at 5.5GHz and includes an adaptive biasing schemeto linearise the amplifier under high input power. Measurement results confirm that thislinearisation scheme extends the 1dB compression point by 4dB over an unlinearised amplifiercore. The supply voltage and bias current for the linearised amplifier are 1.8V and 5.5mArespectively, delivering 2dBm into a 50O load when operated at the 1dB compression point of�3.3dBm. All the components of the linearisation scheme are implemented on-chip enablingmaintenance of a single chip transceiver solution.

1 Introduction

Over recent years, advances have been made towards thedevelopment of integrated transceiver solutions for wirelessapplications. The use of CMOS in these circuits hasincreased with the advance of technology, enabling thepractical implementation of RF circuits. As new networkingstandards emerge, such as 802.11a [1], additional demandsare placed on the transceiver. The operating bands for thisstandard are between 5.15GHz and 5.825GHz, which ismore than twice the operating frequency of current CMOSbased integrated transceiver solutions [2–4]. In addition tothis, the use of orthogonal frequency division multiplexing(OFDM) used by 802.11a requires linear transmitterperformance [5].

The amplifier is usually class-A to ensure linearity, butthis comes at the cost of lower efficiency. In addition, theamplifier may be operated ‘backed-off ’ to avoid compres-sion under high input power, which again lowers theefficiency of the amplifier in the attempt to maintainlinearity. Steps can be taken in the design of the amplifier tohelp resolve the compromise that is made between efficiencyand linearity. In this paper, envelope tracking based controlof the bias settings of the amplifier is the approach taken.For this method, under low power conditions, the biascurrent or voltage to the amplifier is reduced in order todecrease power consumption and improve efficiency. Sincethe method can also be implemented on-chip, it is suitablefor portable applications [6, 7]. The concept behind thisapproach is not new [8] and has already been implementedusing other technologies [9–11]. However, many of theseexamples are not solely on-chip in so far as they requireadditional RF hardware. An on-chip implementation of avariable bias heterojunction bipolar transistor (HBT) based

amplifier has been fabricated by Shinjo [11]. In this paper,we believe we give the first on-chip solution using RFMOSFET devices.

A linearised 5.5GHz CMOS amplifier is designed,measured and compared with an unlinearised version ofthe amplifier. An improvement of 4dB has been achieved atthe 1dB compression point. The design work uses thebipolar simulation (BSIM) 3v3 model [12] with fabricationof both amplifiers using the 0.18mm Taiwan SemiconductorManufacturing Company Ltd. (TSMC) process [13].Measurements on the amplifiers are performed using auniversal measurement system [14] developed at QueensUniversity, Belfast, which is capable of fully characterisingtest transistors and circuits under linear and non-linearoperating conditions.

2 Linearised amplifier operation

For a class-A amplifier, the bias current required to avoidcompression is equal to the AC peak current swing. Frombasic AC model considerations, neglecting parasitics, this isequal to gmVgs where gm is the transconductance of thetransistor and Vgs the gate-source voltage. Plotting the ACpeak current against the input power gives the biascharacteristic for the amplifier required to maintain linearoperation until other limits of operation are reached, e.g.entering the triode region where compression will occur onthe opposite side of the current waveform. Minimisation ofthe bias current is required for efficient amplifier operationwith the reduction in transconductance setting the lowerlimit for the operating point. To achieve this operatingcondition, the configuration in Fig. 1 is used. This consistsof the main power amplifier circuit, a power detector circuit,and a voltage controlled current source (VCCS). At low

power amplifier

VCCS power

detector

input power output power

Fig. 1 Linearised amplifier configuration

B. Toner and V.F. Fusco are with the High Frequency Electronics Laboratories,The Department of Electrical and Electronic Engineering, The QueensUniversity of Belfast, Ashby Building, Stranmillis Road, Belfast BT9 5AH,Ireland

R. Dharmalinggam is with the Parthus (NI) plc, MacNeice House, 75–77Malone Road, Belfast, Ireland

r IEE, 2004

IEE Proceedings online no. 20040252

doi:10.1049/ip-map:20040252

Paper first received 7th November 2002 and in revised form 19th August 2003

26 IEE Proc.-Microw. Antennas Propag., Vol. 151, No. 1, February 2004

power levels the amplifier will perform normally, with thepower detector and VCCS having no effect. Under highpower conditions, the power detector will provide a DCvoltage to the VCCS which is proportional to the inputpower level. As a result, the VCCS will feed additional DCbias current to the main amplifier causing an upward shiftin the load line. This will act to prevent clipping of thecurrent waveform and therefore maintain linear operationof the amplifier core.

Each block of the linearised amplifier core will bedescribed in turn to enable the full amplifier schematic to beconstructed.

2.1 Power detectorThe power detector circuit given in Fig. 2 is based around apeak detect circuit. When biased at the threshold voltage,the MOS transistor acts as a halfwave rectifier charging thecapacitor. On the negative halfcycle, the capacitor dis-charges through the current source, which is also based onan MOS transistor. For the circuit shown, the bias currentthrough the device, assuming negligible ripple in the outputvoltage Vout, can be determined as follows:

IC ¼ bWLðVgs � VTÞ2 ð1Þ

where IC¼ bias current, W¼ device width, L¼ devicelength, Vgs¼ gate–source voltage, VT¼ threshold voltage,b¼ mCox/2, and Cox¼ capacitance per unit area of oxidelayer, and m¼ electron mobility.

The instantaneous bias voltages on the transistorterminals are Vg¼Vin, Vs¼Vout. The gate–source voltageof (1) is therefore given by

Vgs ¼ Vin � Vout ð2ÞSince the transistor of the power detector is placed inparallel with the main power amplifier, it is advantageous tokeep the size of the transistor small. This maximises theinput impedance and also reduces the current consumptionof the amplifier. Restriction on the minimum size of thedevice is enforced by the need for a suitably hightransconductance to provide enough current to the

capacitor to enable operation of the circuit. The timeconstant of the power detector is set by the value of thecurrent source and the value of the capacitance. This timeconstant must be sufficiently large to give negligible rippleon the output voltage, but at the same time be able tofollow the envelope of the input data. For the operatingfrequency of 5.5GHz, the design variables IC and C werechosen to be 50mA and 500 fF, respectively, from theequation governing this behaviour, (3), to give an outputvoltage ripple in the order of 10mV.

DV :C ¼ IC:Dt ð3Þ

For the circuit, Vout, min must be larger than the deviceoffset voltage, i.e. Vin�Vgs, to allow the transistor to operatein the saturation region. Vout, max is also limited by the linearrange of the voltage controlled current source in thefollowing stage. A PMOS transistor was used to enable thegate to be biased with the same voltage as the main poweramplifier, easing circuit implementation. The selected sizefor the transistor was 5mm/0.18mm. The BSIM simulatedpower characteristic for the power detector is shown inFig. 3.

2.2 Voltage controlled current source(VCCS)The voltage controlled current source is used to provide theadditional bias current to the amplifier under high inputpower. The design of this component is similar to that of anoperational transconductance amplifier [15], as shown inFig. 4. Any difference in the power detector output voltageVIN1 and the control voltage VIN2 will yield a proportionaloutput current. The ratio of the difference in the outputcurrent to the difference in the input voltage, i.e. thetransconductance, is proportional to the transconductanceof T1 and T2 [15]:

gm ¼ gm1 ¼ gm2 ð4ÞTherefore,

DIout ¼ gmDV ð5Þwhere the differential voltage is equal to the differencebetween the two input voltages:

DV ¼ VIN1 � VIN2 ð6ÞTherefore, for linear operation of the circuit, the followingconditions must be obeyed, where VOD is the overdrivevoltage of transistors T1 and T2, i.e. Vgs�Vt.

DVmaxoVOD;T1;T2 ð7Þ

Vin

Vout

CIC

Vdd

Fig. 2 Power detector topology

1

1.05

1.1

1.15

1.2

1.25

1.3

−30 −25 −20 −15 −10 −5 0

available power, dBm

outp

ut v

olta

ge, V

Fig. 3 Simulated power detector output voltage

IEE Proc.-Microw. Antennas Propag., Vol. 151, No. 1, February 2004 27

Since the current provided by the VCCS is very small, it isscaled up by a factor of 10 using a current mirror beforeinput into the amplifier bias circuit.

2.3 Power amplifier coreThe power amplifier core design is based on a single stagecascode circuit (Fig. 5). The supply voltage for the amplifieris 1.8V with a bias current of 5mA. For a Class-A design,the peak current swing would also be 5mA, enabling a peakoutput power of �2dBm without compression [16]. Withadditional bias current added at high power, this compres-sion power level should be surpassed in the case of thelinearised amplifier since the maximum current swing willequal the bias current. Biasing to the amplifier is providedby a wide swing current mirror [15] to ensure T2 and T3

operate in the saturation region even with very low outputvoltages, as would be encountered with a power amplifier;the amplifier is unmatched.

3 Measurement results

Figure 6 shows the chip photograph. Ground signal ground(GSG) probes are used for the single ended RF input andoutput connection with DC needle probes used to bias theamplifier. For S-parameter measurement, the system in [14]was calibrated between 5GHz and 6GHz to the on-waferplane using the line reflect match (LRM) [17] method. Theamplifier was biased with a 1.8V supply voltage and a50mA source to produce a total amplifier bias current of5.55mA. The measured S-parameter results are shown inFigs. 7 and 8, taking into account the extrinsic parasiticeffects of the on-wafer pads. Measured Z-parameters arealso shown across the frequency band of interest, whichindicates the required conjugate matching network impe-dance for maximum amplifier gain. At 5.5GHz, theunmatched small-signal gain of the amplifier is 6.7dB(Table 1), which compares well with the simulated value of6.1dB. Since the amplifier core is unmatched, the transducergain of the amplifier should also be equal to this value. TheS12 of the amplifier is around �30dB, providing excellentisolation between the output and input ports owing to thecascoded design of the amplifier. Power sweeps wereconducted from �26.2dBm to �0.2dBm in 2dBm stepswith the source and load being terminated in 50O. The

IB

VIN1V IN2

T1 T2

T4T3

VDD

IOUT

Fig. 4 Voltage controlled current source (VCCS)

IBIAS IIn IOUT

T3

T4

T5

T1

T2RBIAS

C

PIN

VOUT

s

s

s

s

s

Fig. 5 Power amplifier topology

Fig. 6 Chip photograph, 919mm� 732mm

freq (5.000GHz to 6.000GHz)

5.2 5.4 5.6 5.85.0 6.0

50

100

150

0

200

frequency, GHz

Rea

l (Z

11, Z

22)

S11, Z11 S22, Z22

−200

−150

−100

−250

−50

Imag

(Z

11, Z

22)

5.2 5.4 5.6 5.85.0 6.0frequency, GHz

Fig. 7 Measured S11, S22

28 IEE Proc.-Microw. Antennas Propag., Vol. 151, No. 1, February 2004

amplifiers were supplied with 1.8V to provide a total biascurrent of 5.5mA to the amplifiers. For the linearisedamplifier, the value of the control voltage was set to 1.29Vto ensure equal current consumption for both amplifiers.The measured power results for both amplifier cores can beseen in the plots of Figs. 9 and 10. As can be seen fromFig. 9, the effect of linearisation is to extend the linearregion of the amplifier to provide a higher output powerbefore entering saturation. At low power levels, the outputpower of the amplifiers are identical, providing a gain ofabout 6.4dB. Fig. 10 allows a clearer view of the 1dBcompression point. For the unlinearised amplifier thecompression point is �7.3dBm, and for the linearisedamplifier �3.3dBm. This represents an improvement of 4dB to increase the output power by over 100%. To evaluatethe increased output power with the increased powerconsumption, the power added efficiencies of the twoamplifiers can be compared (Fig. 11). From the plot ofFig. 11, the two amplifiers have similar characteristics interms of power level. However, if we consider bothamplifiers to be operating at their respective 1dB compres-sion points, the advantage of the linearisation is highlighted.For the unlinearised amplifier operating at �7.3dBm inputpower, the power added efficiency is 5.5 %; but for thelinearised amplifier operating at �3.3dBm, the efficiency is

9.3%. This represents a relative improvement factor of 1.69.Taking the main figures of merit from the measured andsimulated results allows compilation of the amplifier

5.2 5.4 5.6 5.85.0 6.0

1

2

3

4

5

6

7

0

8

frequency, GHz

frequency, GHz

S21

,dB

5.2 5.4 5.6 5.85.0 6.0

−35

−30

−25

−20

−15

−10

−5

−40

0

S12

,dB

Fig. 8 Measured S21, S12

Table 1 Amplifier specification

Simulated Measured

Unlinearised Linearised Unlinearised Linearised

S21 @5.5GHz 6.3dB 6.3dB 6.7dB 6.7dB

S12 @5.5GHz �35.18dB �35.18dB �30dB �30dB

Z11 @5.5GHz 11.7-j89 11.7-j89 8.5-j98 8.5-j98

Z22 @5.5GHz 140-j310 140-j310 109-j222 109-j222

1dB compression point �6.06dBm �3.28dBm �7.3dBm �3.3dBm

PAE @ compression point 6.4 % 8.8 % 5.5 % 9.3 %

Ibias @ compression point 6.4mA 9.4mA 6.2mA 9.2mA

00

5

−30 −25

−25

−20

−20

−15

−15

−10

−10

−5

−5

available power, dBm

outp

ut p

ower

, dB

m

Unlinearised Linearised

Fig. 9 Measured power characteristic

0

1

2

3

4

5

6

7

8

−30 −25 −20 −15 −10 −5 0

available power, dBm

gain

, dB

0

2

4

6

8

10

12

bias

cur

rent

, mA

Unlinearised Linearised

Fig. 10 Measured gain, bias current

0123456789

10111213

pow

er a

dded

effi

cien

cy, %

0−30 −25 −20 −15 −10 −5

available power, dBm

Unlinearised Linearised

Fig. 11 Measured power added efficiency

IEE Proc.-Microw. Antennas Propag., Vol. 151, No. 1, February 2004 29

specification (Table 1). As can be seen, the BSIM simulationresults are accurate, which justifies the use of this model inCMOS radio frequency integrated circuit (RFIC) design.

4 Conclusions

In this work, a 5.5GHz amplifier core with on-chiplinearisation has been implemented using a 0.18mm CMOSprocess for use as an 802.11 pre-power amplifier. Theamplifier offers improved linearity and efficiency overtraditional fixed bias approaches. In this case, the compres-sion point was extended by 4dB and the power addedefficiency increased by a factor of 1.69. For this amplifier noon-chip matching was used, which resulted in a reducedunmatched gain of 6.7dB. These figures highlight theadvantages of using variable bias in the power amplifier,and since all components are on-chip there is no additionalRF hardware required to implement this scheme. It isparticularly suitable for modulation schemes with high peakto average power ratios (PAPR), such as with the OFDMscheme implemented with 802.11. In addition to thedevelopment of an envelope tracking amplifier in CMOS,it also highlights the suitability of the technology for use atthis higher operating frequency. Since the operatingfrequency range of 802.11a is from 5.15GHz to5.825GHz, this amplifier is ideally suited to cover thefrequency band. However, with a minimum power outputof 50mW for the 802.11a specification, this amplifierobviously would not meet this target and so anotheramplifier stage would be required, possibly using anotherprocess technology better suited to the design of the poweramplifier.

5 Acknowledgments

The authors would like to express their thanks to MOSISfor fabrication of the amplifiers in this paper, and to MrMark Norton for his help in the design.

6 References

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13 Taiwan Semiconductor Manufacturing Company Ltd.,www.tsmc.com. accessed 30 July 2003

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30 IEE Proc.-Microw. Antennas Propag., Vol. 151, No. 1, February 2004