5. Field - Effect Transistors5. Field - Effect Transistors TLT-8016 Basic Analog Circuits 2005/2006 4 Operation in the Triode Region When vGS increases it repels the holes and attracts

5. Field - Effect Transistors TLT-8016 Basic Analog Circuits 2005/2006 1

5. Field - Effect Transistors


5.1 NMOS TransistorsOverview

Figure 5.2 Circuit symbol for an enhancement-mode n-channel MOSFET.

Figure 5.1 n-Channel enhancement MOSFET showing channel length L and channel width W.

Terminals:Source;Drain;Gate;Body (Substrate)

NMOS transistor = enhancement mode MOSFET


Operation in the Cutoff Region

Figure 5.3 For vGS < Vto the pn junction between drain and body is reverse biased and iD = 0.

toGSD Vvi ≤= for0 (5.1)


Operation in the Triode Region

When vGS increases it repels the holes and attracts the electrons near the surface below the gate.When vGS > Vto (threshold voltage) the number of the electrons at the surface is more than the number of the holes – the type of the conductivity is changed from p to n. An n-type channel appears below the gate.When vDS < vGS - Vto the transistor operates in triode region and behaves like voltage-controlled resistor.

( )[ ]22 DSDStoGSD vvVvKi −−= (5.2)

Figure 5.4 For vGS >Vto a channel of n-type material is induced in the region under the gate. As vGS increases, the channel becomes thicker.

For small values of vDS ,iD is proportional to vDS. The device behaves as a resistor whose value depends on vGS.

2KP

LWK

= (5.3)


Operation in the Saturation Region

Figure 5.5 As vDS increases, the channel pinches down at the drain end and iD increases more slowly.

Finally for vDS> vGS -Vto, iD becomes constant.

Figure 5.6 Characteristic curves for an NMOS transistor.

In Figure 5.6 – output characteristics of NMOS transistor.There is no input characteristic for the NMOS transistor.

Boundary between the Triode and the Saturation Region Condition for saturation region: vDS ≥ vGS - Vto

2DSD Kvi =( )2

toGSD VvKi −= (5.7)(5.4)


Channel - Length Modulation

( )[ ]( )DSDSDStoGSD vvvVvKi λ+−−= 12 2

When vDS increases the channel becomes shorter due to extension of depletion region surrounding the drain. It has remarkable effect when the channel is short.In the triode region:

Figure 5.11 Drain characteristics of NMOS transistor width channel-length modulation (PSpice simulation).

(5.10)

In the saturation region:

( ) ( )DStoGSD vVvKi λ+−= 12 (5.11)

λ - channel-length modulation parameter.


Exercise 5.1.Consider an NMOS transistor having Vto = 2V. What is the region of operation (triode, saturation, or cutoff) if (a) vGS = 1V and vDS = 5V? (b) vGS = 3V and vDS = 0.5V? (c) vGS = 3V and vDS = 6V? (d) vGS = 5V and vDS = 6V?

Solution:(a) vGS = 1V < Vto - cutoff;

(b) vGS = 3V > Vto - triode or saturation;vGS - Vto = 3-2 = 1V > vDS – triode region;

(c) vGS = 3V > Vto - triode or saturation;vGS - Vto = 3-2 = 1V < vDS – saturation region;

(d) vGS = 5V > Vto - triode or saturation;vGS - Vto = 5-2 = 3V < vDS – saturation region.

Gate Protection

Figure 5.12 Diodes protect the oxide layer from destruction by static electric charge.


5.3 Bias CircuitsDesign of the Fixed - Plus Self - Bias Circuit

The Fixed - Plus Self - Bias Circuit

Distribution of VDD and selection of the Q-point

D

DDDDDDQD I

VRVIR4

4/ =⇒≅

2/VV DDDSQ ≅

DQ

DDSDDDQS I

VRVIR4

4/ =⇒≅

From the output characteristic - vGS

DQSGSG iRvV += (5.17)

21

2

RRRVV DDG +

= (5.16)Figure 5.16 Fixed- plus self-bias circuit.

Choice of R1 or R2 (hundreds of kΩ or MΩ) and solving (5.16) for the other resistor.


Example 5.4 NMOS Bias Circuit DesignDesign a fixed-plus self-bias circuit for a common-source NMOS amplifier. Nominally, the transistor has KP = 50µA/V2, W = 80µm, L = 2µm, λ = 0 and Vto = 2V. The circuit is to have VDD = 20V and IDQ = 2mA.

Solution:

R1 RD

+VDD

R2 RS

ID

VGS

VGVS

VDFixed-plus self-bias circuit with voltages and currents.

26

6

6

mA/V121050

1021080

2=

×

××

=

=

−

−

−KPL

WK

( )Ω=

×=== − k5.2

1025

3D

DDSD I

RIRR

The nearest 5%-tolerance standard values are RD = RS = 2.4kΩ

From the equation for the drain current

( )2toGSQDQ VVKI −=

we find for VGSQ

V414.31011022 3

3

=××

+=+= −

−

KI

VV DQtoGSQ

V414.8414.35 =+=+= GSQSDG VRIV

We choose R2 = 1MΩ. From the equation

21

2

RRRVV DDG +

=

we find for R1

MΩ377.1414.8

414.820101 621 =

−×=

−=

G

GDD

VVVRR

We choose V54204 ==== DDSDDD VRIRI The 5%-tolerance standard value is R1 = 1.3MΩ


5.4 Small - Signal Equivalent Circuits

( ) ( ) ( )tvVVKti gstoGSQd −= 2All voltages and currents = dc component + variable (small-signal) component

( ) ( )tiIti dDQD +=iD – complete drain current; IDQ – its dc part the drain current in the quiescent point); id – the variable part. Usually

id << IDQ

(5.20)

( ) ( )tvVtv GSGSQGS += (5.21)

( )2toGSD VvKi −=

( ) ( )[ ]2togsGSQdDQ VtvVKtiI −+=+

(5.25)

( )toGSQm VVKg −= 2 (5.26)

( ) ( )tvgti gsmd = (5.27)

gm – transconductance of the NMOS transistor

( ) 0=tig(5.28)

(5.22)

( ) ( )( ) ( ) ( )tKvtvVVK

VVKtiI

gsgstoGSQ

toGSQdDQ

2

2

2 +−+

−=+ (5.23)

( )2toGSQDQ VVKI −= (5.24) Figure 5.22 Small-signal equivalent circuit for FETs.


Dependence of Transconductance on Q-point and Device Parameters

More Complex Equivalent Circuits

( )toGSQm VVKg −= 2 (5.26)

d

dsgsmd r

vvgi += (5.32)From (5.24)

rd – drain resistance. It accounts for the slope of the output characteristics due to channel-length modulation.

( ) ( )K

IVVVVKI DQ

toGSQtoGSQDQ =−⇒−= 2

(5.29)DQm KIg 2=

(5.30)DQm IL/WKPg 2=

Figure 5.23 FET small-signal equivalent circuit that accounts for the dependence of iD on vDS.


Transconductance and Drain Resistance as Partial Derivatives

intpoQDS

D

d vi

r−

∂∂

=1 (5.37)

0=

=dsvgs

dm v

ig (5.33)

DSQDS VvGS

Dm v

ig=

≅∆∆ (5.34)

intpoQGS

Dm v

ig−

∂∂

= (5.35)

GSQGS VvDS

D

d vi

r=

≅∆∆1

(5.36)Figure 5.24 Determination of gm and rd. See Example 5.5.


Example 5.5 Determination of gm and rd from the Characteristic CurvesDetermine the gm and rd for the MOSFET having the characteristics illustrated in Figure 5.24 at a Q-point defined by VGSQ=3.5V and VDSQ= 10 V.

Solution:

Drain current at the Q-point: IDQ= 7.4mA.

VVvGS

Dm

DSQDSvig

10==

=∆∆

mS6V1

mA634

7.47.10==

−−

=∆∆

=GS

Dm v

ig

GSQGS VvDS

D

d vi

r=

=∆∆1

( )( ) S1013.0

V414mA7.60.81 3−×=

−−

≅∆∆

=DS

D

d vi

r

Figure 5.24 Determination of gm and rd. See Example 5.5.


5.5 The Common - Source Amplifier

Figure 5.25 Common-source amplifier.

R1, R2, RD and RS – from fixed-plus self bias circuit;C1 and C2 – coupling capacitors;CS – bypass capacitor.


The Small Equivalent Circuit

Figure 5.26 Small-signal equivalent circuit for the common-source amplifier.

Voltage Gain Input Resistance

LDd

'L R/R/r/

R111

1++

= (5.38)

21 R||RRivR G

in

inin === (5.42)

( ) 'Lgsmo Rvgv −= (5.39)

gsin vv = (5.40)

'Lm

in

ov Rg

vvA −== (5.41)


Output Resistance

Figure 5.27 Circuit used to find Ro.

dDo r/R/

R11

1+

= (5.43)


Example 5.6 Gain and Impedance of the Common -Source Amplifier

Consider the common - source amplifier illustrated in Figure 5.28. The NMOS transistor has KP=50 µA/V2, Vto=2 V, λ=0, L=10 µm, and W=400 µm. Find the midband voltage gain, input resistance, and output resistance of the amplifier. The quiescent point is VGSQ = 2.886V, VDSQ =14.2V and IDQ = 0.784mA.

Solution:

mS77.1/2 == DQm ILWKPg

Because λ=0 rd = ∞.

( ) ( ) Ω=×+×+∞

=

++=

319710101107.411

1/1/1/1

1

33

'

LDdL RRr

R

66.531971077.1 3' −=××−=−= −Lmv RgA

( ) ( ) Ω=×+×

== kRRRin 75010311011

1|| 6621

( ) Ω=∞+×

=+

= krR

RdD

o 7.41107.41

1/1/1

13

Figure 5.28 Common-source amplifier.


5.6 The Source Follower

Figure 5.33 Source follower.

Voltage gain Av < 1High input impedance = R1||R2Small output impedance ~ 1/gm Used as output buffer when small output impedance is needed.


5.7 JFETs, Depletion - Mode MOSFETs, and P - Channel DevicesThe n - channel Junction FET

Figure 5.39 The nonconductive depletion region becomes thicker with increased reverse bias. (Note: The two gate regions of each FET

are connected to each other.)

Figure 5.38 n-Channel JFET.When VGS < Vto (Vto is negative) pinch-off occurs and the transistor is not conducting and is in cut-off region of operation.


Characteristic Curves for n - channel Junction FET

Figure 5.42 n-Channel FET for vGS = 0.Figure 5.41 Drain current versus drain-to-source voltage

for zero gate-to-source voltage.

When vDS > vGS - Vto pinch-off occurs at the drain area and drain current is approximately constant. The device is operating in saturation region.


Breakdown

Figure 5.43 Typical drain characteristics of an n-channel JFET.

Figure 5.44 If vDG exceeds the breakdown voltage VB, drain current increases rapidly.


Depletion MOSFETs

Figure 5.46 n-Channel depletion MOSFET.

Figure 5.47 Drain current versus vGSin the saturation region for n-channel devices.


p - Channel FETs

Figure 5.48 p-Channel FET circuit symbols. These are the same as the circuit symbols for n-channel devices, except for the directions of the arrowheads.

Figure 5.49 Drain current versus vGS for several types of FETs. iD is referenced into the drain terminal for n-channel devices and out of the drain for p-channel devices.


Table 5.1 FET Summary

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5. Field - Effect Transistors5. Field - Effect Transistors TLT-8016 Basic Analog Circuits 2005/2006 4 Operation in the Triode Region When vGS increases it repels the holes and attracts