4GB, 8GB, 16GB, 32GB: e·MMC - 4donline.ihs.com · e·MMC™ Memory MTFC4GGQDM, MTFC4GGQDI, MTFC8GKQDI, MTFC16GKQDI, MTFC32GKQDH Features • MultiMediaCard (MMC) controller and NAND

e·MMC™ MemoryMTFC4GGQDM, MTFC4GGQDI, MTFC8GKQDI,MTFC16GKQDI, MTFC32GKQDH

Features• MultiMediaCard (MMC) controller and NAND Flash• 153-ball FBGA or 169-ball FBGA (6/6 RoHS-compli-

ant)• VCC: 2.7–3.6V• VCCQ (dual voltage): 1.65–1.95V, 2.7–3.6V• Storage temperature range: –40˚C to +85˚C• Typical current consumption

– Standby current: 70µA (4GB, 8GB); 90µA (16GB);130µA (32GB)

– Active current (RMS): 70mA (4GB, 8GB); 90mA(16GB, 32GB)

MMC-Specific Features

• JEDEC/MMC standard version 4.41-compliant(JEDEC Standard No. 84-A441) – SPI mode, high-priority interrupt (HPI), background operation,enhanced reliable WRITE, and double data rate(DDR) function not supported– Advanced 11-signal interface– x1, x4, and x8 I/Os, selectable by host– MMC mode operation– Command classes: class 0 (basic); class 2 (block

read); class 4 (block write); class 5 (erase);class 6 (write protection); class 7 (lock card)

– MMCplus™ and MMCmobile™ protocols– Temporary write protection– 52 MHz clock speed (MAX)– Boot operation (high-speed boot)– Sleep mode– Reliable WRITE– Replay-protected memory block (RPMB)– Secure erase and trim– Hardware reset signal– Multiple partitions with enhanced attribute– Permanent and power-on write protection– Backward-compatible with previous MMC modes

• ECC and block management implemented• Deviations from the JEDEC specification are descri-

bed in the last section of this data sheet.

Figure 1: Micron e·MMC Device

MMC controllerMMCpower

NAND Flashpower

MMCinterface

NAND Flash

Options • Density: 4GB, 8GB, 16GB, 32GB • Temperature range

– Industrial temperature: –40˚C to +85˚C IT

4GB, 8GB, 16GB, 32GB: e·MMCFeatures

PDF: 09005aef838eabbaemmc_rev_q_v4_41_153b_169b_j534q567r.pdf - Rev. C 7/10 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2009 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.

Part Numbering InformationMicron®e·MMC memory devices are available in different configurations and densities.

Figure 2: e·MMC Part Numbering

MT FC xx x x xx - xx

Micron Technology

Product FamilyFC = NAND Flash + controller

NAND Flash Density

NAND Flash Component

Controller Revision

Production Status

Operating Temperature Range

Package Codes

ReservedBlank

Device MarkingDue to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead,an abbreviated device mark consisting of a 5-digit alphanumeric code is used. The abbreviated device marks arecross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site: www.micron.com/decoder.To view the location of the abbreviated mark on the device, refer to customer service note CSN-11, “Product Mark/Label,” at www.micron.com/csn.

Valid Part Number CombinationsVerify valid part numbers by using Micron’s part catalog search at www.micron.com. To compare features andspecifications by device type, visit www.micron.com/products. Contact the factory for devices not found.

4GB, 8GB, 16GB, 32GB: e·MMCFeatures



http://www.micron.com/decoder

http://www.micron.com/csn

http://www.micron.com

http://www.micron.com/products

ContentsGeneral Description ....................................................................................................................................... 13Signal Descriptions ........................................................................................................................................ 14153-Ball Signal Assignments ........................................................................................................................... 15169-Ball Signal Assignments ........................................................................................................................... 16153-Ball DM Package Dimensions ................................................................................................................... 18169-Ball DH Package Dimensions ................................................................................................................... 19169-Ball DI Package Dimensions ..................................................................................................................... 20Architecture ................................................................................................................................................... 21

MMC Protocol Independent of NAND Flash Technology .............................................................................. 21Defect and Error Management .................................................................................................................... 22MMC Controller Registers ........................................................................................................................... 22

OC Register .................................................................................................................................................... 23CID Register ................................................................................................................................................... 24CID Register Fields ......................................................................................................................................... 24

MID Field (bits[127:120]) ............................................................................................................................ 24CBX Field (bits[113:112]) ............................................................................................................................. 24OID Field (bits[111:104]) ............................................................................................................................. 24PNM Field (bits[103:56]) ............................................................................................................................. 25PRV Field (bits[55:48]) ................................................................................................................................ 25PSN Field (bits[47:16]) ................................................................................................................................ 25MDT Field (bits[15:8]) ................................................................................................................................. 25CRC Field (bits[7:1]) ................................................................................................................................... 25

CSD Register (MLC e·MMC) ............................................................................................................................ 26CSD Register Fields ........................................................................................................................................ 27

CSD_STRUCTURE Field (bits[127:126]) ....................................................................................................... 27SPEC_VERS Field (bits[125:122]) ................................................................................................................. 28TAAC Field (bits[119:112]) ........................................................................................................................... 28NSAC Field (bits[111:104]) .......................................................................................................................... 29TRAN_SPEED Field (bits[103:96]) ................................................................................................................ 29CCC Field (bits[95:84]) ................................................................................................................................ 30READ_BL_LEN Field (bits[83:80]) ................................................................................................................ 30READ_BL_PARTIAL Field (bit 79) ................................................................................................................ 31WRITE_BLK_MISALIGN Field (bit 78) .......................................................................................................... 31READ_BLK_MISALIGN Field (bit 77) ........................................................................................................... 31DSR_IMP Field (bit 76) ............................................................................................................................... 31C_SIZE Field (bits[73:62]) ............................................................................................................................ 32VDD_R_CURR_MIN Field (bits[61:59]), VDD_W_CURR_MIN Field (bits[55:53]) ............................................ 32VDD_R_CURR_MAX Field (bits[58:56]), VDD_W_CURR_MAX Field (bits[52:50]) ........................................... 33C_SIZE_MULT Field (bits[49:47]) ................................................................................................................ 33ERASE_GRP_SIZE Field (bits[46:42]) ............................................................................................................ 34ERASE_GRP_MULT Field (bits[41:37]) ......................................................................................................... 34WP_GRP_SIZE Field (bits[36:32]) ................................................................................................................. 34WP_GRP_ENABLE Field (bit 31) .................................................................................................................. 34DEFAULT_ECC Field (bits[30:29]) ............................................................................................................... 34R2W_FACTOR Field (bits[28:26]) ................................................................................................................. 34WRITE_BL_LEN Field (bits[25:22]) .............................................................................................................. 35WRITE_BL_PARTIAL Field (bit 21) ............................................................................................................... 35CONTENT_PROT_APP Field (bit 16) ............................................................................................................ 35FILE_FORMAT_GRP Field (bit 15) ............................................................................................................... 35COPY Field (bit 14) ..................................................................................................................................... 35

4GB, 8GB, 16GB, 32GB: e·MMC



PERM_WRITE_PROTECT Field (bit 13) ........................................................................................................ 35TMP_WRITE_PROTECT Field (bit 12) .......................................................................................................... 36FILE_FORMAT Field (bits[11:10]) ................................................................................................................ 36ECC Field (bits[9:8]) .................................................................................................................................... 36CRC Field (bits[7:1]) ................................................................................................................................... 36

ECSD Register (MLC e·MMC) .......................................................................................................................... 37ECSD Register Fields – Properties Segment ...................................................................................................... 41

S_CMD_SET Field (byte 504) ....................................................................................................................... 41HPI_FEATURES Field (byte 503) .................................................................................................................. 41BKOPS_SUPPORT Field (byte 502) .............................................................................................................. 41BKOPS_STATUS Field (byte 246) ................................................................................................................. 42CORRECTLY_PRG_SECTORS_NUM Field (bytes[245:242]) ........................................................................... 42INI_TIMEOUT_PA Field (byte 241) .............................................................................................................. 43TRIM_MULT Field (byte 232) ...................................................................................................................... 43SEC_FEATURE_SUPPORT Field (byte 231) .................................................................................................. 43SEC_ERASE_MULT Field (byte 230) ............................................................................................................ 44SEC_TRIM_MULT Field (byte 229) .............................................................................................................. 45BOOT_INFO Field (byte 228) ....................................................................................................................... 45BOOT_SIZE_MULT Field (byte 226) ............................................................................................................ 46ACC_SIZE Field (byte 225) .......................................................................................................................... 46HC_ERASE_GRP_SIZE Field (byte 224) ........................................................................................................ 47ERASE_TIMEOUT_MULT Field (byte 223) ................................................................................................... 47REL_WR_SEC_C Field (byte 222) ................................................................................................................. 48HC_WP_GRP_SIZE Field (byte 221) ............................................................................................................. 48S_C_VCC Field (byte 220), S_C_VCCQ Field (byte 219) ................................................................................. 49S_A_TIMEOUT Field (byte 217) ................................................................................................................... 49SEC_COUNT Field (bytes[215:212]) ............................................................................................................. 50MIN_PERF_DDR_R/W_b_ff Fields (bytes[235:234]), MIN_PERF_R/W_b_ff Fields (bytes[210:205]) ................. 50Device Performance Measurement ............................................................................................................. 51PWR_CL_DDR_ff_vvv Fields (bytes[239:238]), PWR_CL_ff_vvv Fields (bytes[203:200]) ................................... 52PARTITION_SWITCH_TIME Field (byte 199) ............................................................................................... 53OUT_OF_INTERRUPT_TIME Field (byte 198) .............................................................................................. 54CARD_TYPE Field (byte 196) ....................................................................................................................... 54CSD_STRUCTURE Field (byte 194) .............................................................................................................. 54EXT_CSD_REV Field (byte 192) ................................................................................................................... 55

ECSD Register Fields – Modes Segment ........................................................................................................... 56CMD_SET Field (byte 191) .......................................................................................................................... 56CMD_SET_REV Field (byte 189) .................................................................................................................. 56POWER_CLASS Field (byte 187) .................................................................................................................. 56HS_TIMING Field (byte 185) ....................................................................................................................... 56BUS_WIDTH Field (byte 183) ...................................................................................................................... 57ERASED_MEM_CONT Field (byte 181) ........................................................................................................ 57PARTITION_CONFIG Field (byte 179) ......................................................................................................... 57BOOT_CONFIG_PROT Field (byte 178) ....................................................................................................... 58BOOT_BUS_WIDTH Field (byte 177) ........................................................................................................... 59ERASE_GROUP_DEF Field (byte 175) .......................................................................................................... 60BOOT_WP Field (byte 173) .......................................................................................................................... 60USER_WP Field (byte 171) .......................................................................................................................... 61FW_CONFIG Field (byte 169) ...................................................................................................................... 62RPMB_SIZE_MULT Field (byte 168) ............................................................................................................ 63WR_REL_SET Field (byte 167) ..................................................................................................................... 63WR_REL_PARAM Field (byte 166) ................................................................................................................ 64




BKOPS_START Field (byte 164) ................................................................................................................... 65BKOPS_EN Field (byte 163) ......................................................................................................................... 65RST_n_FUNCTION Field (byte 162) ............................................................................................................. 65HPI_MGMT Field (byte 161) ....................................................................................................................... 66PARTITIONING_SUPPORT Field (byte 160) ................................................................................................. 66MAX_ENH_SIZE_MULT Field (bytes[159:157]) ............................................................................................ 67PARTITIONS_ATTRIBUTE Field (byte 156) .................................................................................................. 67PARTITION_SETTING_COMPLETED Field (byte 155) .................................................................................. 68GP_SIZE_MULT Field (bytes[154:143]) ........................................................................................................ 68ENH_SIZE_MULT Field (bytes[142:140]) ..................................................................................................... 69ENH_START_ADDR Field (bytes[139:136]) .................................................................................................. 69SEC_BAD_BLK_MGMNT Field (byte 134) .................................................................................................... 70

RCA Register .................................................................................................................................................. 71DS Register .................................................................................................................................................... 71Bus Protocol – Message Types ......................................................................................................................... 72Bus Protocol – Command Token ..................................................................................................................... 73

Command Types ........................................................................................................................................ 74Command Classes ...................................................................................................................................... 74Command Descriptions .............................................................................................................................. 74

Bus Protocol – Response Token ....................................................................................................................... 83R1 Response Token .................................................................................................................................... 84R1b Response Token .................................................................................................................................. 85R2 Response Token .................................................................................................................................... 88R3 Response Token .................................................................................................................................... 88

Bus Protocol – Data Packet ............................................................................................................................. 89Bus Protocol – CRC ......................................................................................................................................... 91

CRC7 ......................................................................................................................................................... 91CRC16 ........................................................................................................................................................ 92

Bus Protocol – CRC Status Token .................................................................................................................... 93CRC Status Token ....................................................................................................................................... 93

Bus Protocol – Clock Control ........................................................................................................................... 94Host Restrictions ........................................................................................................................................ 94Bus Transactions ........................................................................................................................................ 94

Bus Protocol – Bus Error Conditions ................................................................................................................ 95COM_CRC_ERROR Bit ................................................................................................................................ 95ILLEGAL_COMMAND Error Bit ................................................................................................................... 95ADDRESS_OUT_OF_RANGE Error .............................................................................................................. 95

MMC Mode Bus Operations ............................................................................................................................ 96NO RESPONSE Operation ........................................................................................................................... 96NO DATA Operation Without a Busy Indicator ............................................................................................ 96NO DATA Operation With a Busy Indicator .................................................................................................. 97DATA TRANSFER Operation ....................................................................................................................... 98

Partition Management ................................................................................................................................... 100Memory Partition Organization ................................................................................................................. 100Partition Command Restrictions ................................................................................................................ 101Configuring Partitions ............................................................................................................................... 102Accessing Partitions .................................................................................................................................. 105

Operating Modes ........................................................................................................................................... 106Boot Mode .................................................................................................................................................... 107

Device Reset to Pre-Idle State ..................................................................................................................... 107Boot Partitions .......................................................................................................................................... 108Boot Mode Operation ................................................................................................................................ 109




Alternative Boot Mode Operation ............................................................................................................... 111Accessing Boot Partitions ........................................................................................................................... 114Boot Bus Width and Access Configuration .................................................................................................. 114Boot Partition Write Protection .................................................................................................................. 115

Card Identification Mode ............................................................................................................................... 116Device Reset .............................................................................................................................................. 117Idle State to Ready State ............................................................................................................................ 117Ready State to Identification State .............................................................................................................. 118Identification State to Standby State ........................................................................................................... 119

Data Transfer Mode – Overview ..................................................................................................................... 120Data Transfer Mode – Command Sets and Extended Settings .......................................................................... 122

High-Speed Mode Selection ....................................................................................................................... 123Power Class Selection ................................................................................................................................ 124Bus Width Selection .................................................................................................................................. 124Bus Testing Procedure ............................................................................................................................... 125

Data Transfer Mode – Data READ Operation .................................................................................................. 127Block Read ................................................................................................................................................ 127

Data Transfer Mode – Data WRITE Operation ................................................................................................. 129Block Write ............................................................................................................................................... 129

Data Transfer Mode – ERASE Operation ......................................................................................................... 133Data Transfer Mode – SECURE ERASE Operation ........................................................................................... 136Data Transfer Mode – TRIM Operation ........................................................................................................... 137Data Transfer Mode – SECURE TRIM Operation ............................................................................................. 138Data Transfer Mode – Write-Protect Management .......................................................................................... 140Data Transfer Mode – LOCK/UNLOCK Operations ......................................................................................... 142

LOCK/UNLOCK Command Sequences ...................................................................................................... 144Data Transfer Mode – SLEEP/AWAKE Operations ........................................................................................... 147Data Transfer Mode – RPMB .......................................................................................................................... 148

RPMB Access Data Frame .......................................................................................................................... 148RPMB Memory Map .................................................................................................................................. 150MAC Calculation for RPMB ........................................................................................................................ 151Accesses to the RPMB ................................................................................................................................ 152

Data Transfer Mode – Background Operation ................................................................................................. 159Data Transfer Mode – High-Priority Interrupt ................................................................................................. 160Data Transfer Mode – R/W Blocks, Erase Groups, and WPGs ........................................................................... 162Inactive Mode ............................................................................................................................................... 163DC Electrical Specifications – Bus (MLC e·MMC) ............................................................................................ 164

Bus Topology ............................................................................................................................................ 164Bus Operating Conditions .......................................................................................................................... 165Bus Signal Line Load ................................................................................................................................. 165Bus Signal Levels ....................................................................................................................................... 166

DC Electrical Specifications – Device Power (MLC e·MMC) ............................................................................. 167DC Electrical Specifications – Power-On Sequence ......................................................................................... 169DC Electrical Specifications – RST_n Signal During Power-On Period .............................................................. 171DC Electrical Specifications – Power Cycling .................................................................................................. 172AC Electrical Specifications ............................................................................................................................ 173Timeout Conditions ...................................................................................................................................... 176Bus and Device Interface Timing .................................................................................................................... 177Command Timing Symbols and Definitions ................................................................................................... 178BOOT Operation Timing ................................................................................................................................ 179Command/Response Timing ......................................................................................................................... 183

SEND_OP_COND (CMD1) and ALL_SEND_CID (CMD2) Timing ................................................................. 183




SET_RCA (CMD3) Timing .......................................................................................................................... 183Data Transfer Mode Timing ....................................................................................................................... 184R1b Response Timing ................................................................................................................................ 184Last Device Response to Next Host Command Timing ................................................................................ 185Last Host Command to Next Host Command Timing .................................................................................. 185

Data Read Timing .......................................................................................................................................... 186READ_SINGLE_BLOCK (CMD17) Timing ................................................................................................... 186READ_MULTIPLE_BLOCK (CMD18) Timing .............................................................................................. 186

Data Write Timing ......................................................................................................................................... 188WRITE_BLOCK (CMD24) Timing ............................................................................................................... 188WRITE_MULTIPLE_BLOCK (CMD25) Timing ............................................................................................. 189STOP_TRANSMISSION (CMD12) Timing ................................................................................................... 190ERASE (CMD38), SET_WRITE_PROT (CMD28), CLR_WRITE_PROT (CMD29) Timing .................................. 194Reselecting a Busy Device .......................................................................................................................... 194BUSTEST_W (CMD19) and BUSTEST_R (CMD14) Timing ........................................................................... 195

Hardware Reset Timing ................................................................................................................................. 196Hardware Reset Waveform ........................................................................................................................ 196Hardware Reset Noise Filtering Timing ...................................................................................................... 196

Optional Features Not Supported by the Device ............................................................................................. 197Device Deviations From JEDEC v4.41 Specification (Errata) ............................................................................ 198

Bus Test (CMD14/CMD19) at Low Frequency (<400 kHz) ............................................................................ 198Power Cycle Required for RST_n Signal Enabled ......................................................................................... 198Cell Type of ERASE_GROUP_DEF .............................................................................................................. 198No Erase Commands Supported in Boot Partitions ..................................................................................... 198Limit to the Number of Step 1s in a SECURE TRIM Command Sequence (511 Max) ..................................... 198RST_n Signal ............................................................................................................................................. 198ECSD Values for Bytes[159:157] in ECSD Register (MLC e·MMC) ................................................................. 199Boot Acknowledge Time (for MTFC8GKQxx and MTFC4GGQxx) ................................................................. 199CMD Line Kept LOW for BOOT Operation After Hardware Reset (RST_n) Asserted ....................................... 199BUS_WIDTH and HS_TIMING Bits Not Reset by CMD0 .............................................................................. 199CMD24 Interrupted by CMD12 .................................................................................................................. 199Issuing ERASE Command to RPMB Partition Prohibited ............................................................................. 199SEC_BAD_BLK_MGMT (ECSD[134]) Not Supported ................................................................................... 199

Revision History ............................................................................................................................................ 200Rev. C, Production – 7/10 ........................................................................................................................... 200Rev. B, Production – 6/10 ........................................................................................................................... 200Rev. A, Production – 4/10 ........................................................................................................................... 200




List of TablesTable 1: Signal Descriptions .......................................................................................................................... 14Table 2: OC Register Settings ......................................................................................................................... 23Table 3: CID Register Field Parameters .......................................................................................................... 24Table 4: CBX Field Device Types .................................................................................................................... 24Table 5: CSD Register Field Parameters (MLC e·MMC) .................................................................................... 26Table 6: CSD_STRUCTURE Field Values ........................................................................................................ 27Table 7: SPEC_VERS Field Values ................................................................................................................... 28Table 8: TAAC Field Bit Position Codes .......................................................................................................... 28Table 9: TRAN_SPEED Field Bit Position Codes .............................................................................................. 29Table 10: CCC Field Bit Codes ........................................................................................................................ 30Table 11: READ_BL_LEN Field Block Length Codes ........................................................................................ 30Table 12: DSR_IMP Field Codes ..................................................................................................................... 31Table 13: VDD_R_CURR_MIN, VDD_W_CURR_MIN Field Values ................................................................... 32Table 14: VDD_R_CURR_MAX, VDD_W_CURR_MAX Field Values .................................................................. 33Table 15: C_SIZE_MULT Field Values ............................................................................................................ 33Table 16: R2W_FACTOR Field Values ............................................................................................................. 34Table 17: FILE_FORMAT Field Definitions ..................................................................................................... 36Table 18: ECC Field Formats .......................................................................................................................... 36Table 19: ECSD Register Field Parameters (MLC e·MMC) ................................................................................ 37Table 20: S_CMD_SET Field Values ................................................................................................................ 41Table 21: HPI_FEATURES Field Byte Format .................................................................................................. 41Table 22: HPI_FEATURES Field Bit Descriptions ............................................................................................ 41Table 23: BKOPS_SUPPORT Field Byte Format ............................................................................................... 41Table 24: BKOPS_SUPPORT Field Bit Descriptions ......................................................................................... 42Table 25: BKOPS_STATUS Field Byte Format ................................................................................................. 42Table 26: BKOPS_STATUS Field Bit Descriptions ............................................................................................ 42Table 27: Number of Sectors Correctly Programmed ...................................................................................... 42Table 28: INI_TIMEOUT_PA Field Initialization Maximum Timeout Values ..................................................... 43Table 29: TRIM_MULT Field TRIM Timeout Values ........................................................................................ 43Table 30: SEC_FEATURE_SUPPORT Field Byte Format ................................................................................... 44Table 31: SEC_FEATURE_SUPPORT Field Bit Descriptions ............................................................................. 44Table 32: SEC_ERASE_MULT Field SECURE ERASE Timeout Values ............................................................... 44Table 33: SEC_TRIM_MULT Field SECURE TRIM Timeout Values ................................................................... 45Table 34: BOOT_INFO Field Byte Format ....................................................................................................... 45Table 35: BOOT_INFO Field Bit Descriptions ................................................................................................. 45Table 36: BOOT_SIZE_MULT Field Boot Partition Size Values ......................................................................... 46Table 37: ACC_SIZE Field Byte Format ........................................................................................................... 46Table 38: ACC_SIZE Field SUPER_PAGE_SIZE Values ..................................................................................... 46Table 39: HC_ERASE_GRP_SIZE Field Erase Unit Size Values .......................................................................... 47Table 40: ERASE_TIMEOUT_MULT Field Erase Timeout Values ..................................................................... 48Table 41: HC_WP_GRP_SIZE Field Write Protect Group Size ........................................................................... 48Table 42: S_C_VCC and S_C_VCCQ Field Values ............................................................................................. 49Table 43: S_A_TIMEOUT Field Values ............................................................................................................ 49Table 44: Read/Write (R/W) Access Performance Values ................................................................................. 51Table 45: Supported Power Classes ................................................................................................................ 53Table 46: PARTITION_SWITCH Timeout Values ............................................................................................. 53Table 47: OUT_OF_INTERRUPT_TIME Timeout Values .................................................................................. 54Table 48: CARD_TYPE Field Definitions ......................................................................................................... 54Table 49: CSD_STRUCTURE Field Descriptions ............................................................................................. 54Table 50: EXT_CSD_REV Field Descriptions ................................................................................................... 55




Table 51: CMD_SET_REV Field Values ........................................................................................................... 56Table 52: POWER_CLASS Field Descriptions .................................................................................................. 56Table 53: BUS_WIDTH Field Values ............................................................................................................... 57Table 54: ERASED_MEM_CONT Field Values ................................................................................................. 57Table 55: PARTITION_CONFIG Field Byte Format .......................................................................................... 57Table 56: PARTITION_CONFIG Field Bit Descriptions .................................................................................... 58Table 57: BOOT_CONFIG_PROT Field Byte Format ........................................................................................ 58Table 58: BOOT_CONFIG_PROT Field Bit Descriptions .................................................................................. 58Table 59: BOOT_BUS_WIDTH Field Byte Format ........................................................................................... 59Table 60: BOOT_BUS_WIDTH Field Bit Descriptions ...................................................................................... 59Table 61: ERASE_GROUP_DEF Field Byte Format ........................................................................................... 60Table 62: ERASE_GROUP_DEF Field Bit Descriptions ..................................................................................... 60Table 63: BOOT_WP Field Byte Format .......................................................................................................... 60Table 64: BOOT_WP Field Bit Descriptions .................................................................................................... 60Table 65: USER_WP Field Byte Format ........................................................................................................... 61Table 66: USER_WP Field Bit Descriptions ..................................................................................................... 61Table 67: FW_CONFIG Field Byte Format ....................................................................................................... 62Table 68: FW_CONFIG Field Bit Descriptions ................................................................................................. 62Table 69: RPMB_SIZE_MULT Field Values and Descriptions ........................................................................... 63Table 70: WR_REL_SET Field Bit Types .......................................................................................................... 63Table 71: WR_REL_SET Field Bit Descriptions ................................................................................................ 64Table 72: WR_REL_PARAM Field Bit Types ..................................................................................................... 64Table 73: WR_REL_PARAM Field Bit Descriptions .......................................................................................... 65Table 74: BKOPS_EN Field Byte Format ......................................................................................................... 65Table 75: BKOPS_EN Field Bit Descriptions .................................................................................................... 65Table 76: RST_n_FUNCTION Field Byte Format ............................................................................................. 65Table 77: RST_n_FUNCTION Field Bit Descriptions ....................................................................................... 66Table 78: HPI_MGMT Field Byte Format ........................................................................................................ 66Table 79: HPI_MGMT Field Bit Descriptions .................................................................................................. 66Table 80: PARTITIONING_SUPPORT Field Byte Format ................................................................................. 67Table 81: PARTITIONING_SUPPORT Field Bit Descriptions ............................................................................ 67Table 82: MAX_ENH_SIZE_MULT Field Byte Format ...................................................................................... 67Table 83: PARTITIONS_ATTRIBUTE Field Byte Format .................................................................................. 67Table 84: PARTITIONS_ATTRIBUTE Field Bit Descriptions ............................................................................. 68Table 85: PARTITION_SETTING_COMPLETED Field Byte Format .................................................................. 68Table 86: GP_SIZE_MULT Field Byte Format .................................................................................................. 68Table 87: GP_SIZE_MULT Field Byte Descriptions .......................................................................................... 69Table 88: ENH_SIZE_MULT Field Byte Format ............................................................................................... 69Table 89: ENH_START_ADDR Field Byte Format ............................................................................................ 70Table 90: SEC_BAD_BLK_MGMNT Field Byte Format ..................................................................................... 70Table 91: SEC_BAD_BLK_MGMNT Field Bit Descriptions ............................................................................... 70Table 92: Command Token Format ................................................................................................................ 73Table 93: Command Types ............................................................................................................................ 74Table 94: Basic Commands (class 0) ............................................................................................................... 75Table 95: Block-Oriented Read Commands (class 2) ....................................................................................... 76Table 96: Block-Oriented Write Commands (class 4) ....................................................................................... 77Table 97: Erase Commands (class 5) .............................................................................................................. 78Table 98: Block-Oriented Write Protection Commands (class 6) ...................................................................... 79Table 99: Lock Card (class 7) .......................................................................................................................... 80Table 100: Device State Transitions by Command .......................................................................................... 80Table 101: R1/R1b Response Token Format ................................................................................................... 85Table 102: R1/R1b Card Status Field .............................................................................................................. 85




Table 103: R2 Response Token Format ........................................................................................................... 88Table 104: R3 Response Token Format ........................................................................................................... 88Table 105: Operating Modes, Bus Modes, and Device States .......................................................................... 106Table 106: ECSD Register Access Modes ........................................................................................................ 123Table 107: Example of Host Command Token to Enable High-Speed Timing on the Bus ................................. 123Table 108: Example of Host Command Token to Switch from 1-Bit to 8-Bit

I/O Operation ........................................................................................................................................... 124Table 109: Bus Testing Pattern ...................................................................................................................... 125Table 110: 1-Bit Bus Testing Pattern .............................................................................................................. 126Table 111: 4-Bit Bus Testing Pattern .............................................................................................................. 126Table 112: 8-Bit Bus Testing Pattern .............................................................................................................. 126Table 113: ERASE Command Valid Arguments .............................................................................................. 134Table 114: ERASE Command Comparison ..................................................................................................... 134Table 115: ERASE Command Argument Definitions ....................................................................................... 136Table 116: Write Protection Hierarchy (disable bits cleared) .......................................................................... 141Table 117: Write Protection Types (disable bits cleared) ................................................................................. 141Table 118: LOCK/UNLOCK Data Structure .................................................................................................... 143Table 119: LOCK/UNLOCK Data Descriptions ............................................................................................... 143Table 120: RPMB Access Data Frame ............................................................................................................ 148Table 121: RPMB Access Data Frame Field Descriptions ................................................................................ 148Table 122: RPMB Operation Result Field Data Structure ................................................................................ 149Table 123: RPMB Operation Result Field Defined Results ............................................................................... 149Table 124: RPMB Request/Response Message Types ..................................................................................... 150Table 125: RPMB Memory Map .................................................................................................................... 150Table 126: MAC Request Frames ................................................................................................................... 151Table 127: Authentication Key Information Data Packet ................................................................................ 152Table 128: Authentication Key Request Type Information Data Packet ........................................................... 153Table 129: Authentication Key Result Information Data Packet ...................................................................... 153Table 130: Counter Read Request Type Information Data Packet ................................................................... 154Table 131: Counter Value Read Data Packet .................................................................................................. 154Table 132: Authenticated Data Write Data Packet .......................................................................................... 155Table 133: Authenticated Data Write Request Type Information Data Packet .................................................. 156Table 134: Authenticated Data Write Result Information Data Packet ............................................................. 156Table 135: Authenticated Data Read Request Type Information Data Packet .................................................. 157Table 136: Authenticated Data Read Information Data Packet ....................................................................... 157Table 137: Interruptible Commands ............................................................................................................. 160Table 138: Host and Bus Resistance Values (MLC e·MMC) ............................................................................. 165Table 139: Bus Operating Conditions (MLC e·MMC) ...................................................................................... 165Table 140: Open-Drain Mode Bus Signal Levels (MLC e·MMC) ....................................................................... 166Table 141: Push-Pull Mode Bus Signal Levels (MLC e·MMC, VCCQ = 2.7–3.6V) ................................................. 166Table 142: Push-Pull Mode Bus Signal Levels (MLC e·MMC, VCCQ = 1.65–1.95V) .............................................. 166Table 143: Absolute Maximum Ratings (MLC e·MMC) ................................................................................... 167Table 144: Device Power Supply Voltages (MLC e·MMC) ................................................................................ 168Table 145: Timing Values .............................................................................................................................. 173Table 146: Command Set Timing Parameters and Example Equation ............................................................. 173Table 147: Hardware Reset Timing Parameters .............................................................................................. 173Table 148: Interface Timing (high-speed interface) ........................................................................................ 174Table 149: Interface Timing (standard interface) ........................................................................................... 175Table 150: Command Timing Symbols and Definitions ................................................................................. 178




List of FiguresFigure 1: Micron e·MMC Device ....................................................................................................................... 1Figure 2: e·MMC Part Numbering .................................................................................................................... 2Figure 3: 153-Ball FBGA (top view, ball down) ................................................................................................ 15Figure 4: 169-Ball FBGA (top view, ball down) ................................................................................................ 16Figure 5: 153-Ball FBGA (package code DM) ................................................................................................... 18Figure 6: 169-Ball FBGA (package code DH) ................................................................................................... 19Figure 7: 169-Ball FBGA (package code DI) ..................................................................................................... 20Figure 8: e·MMC Functional Block Diagram ................................................................................................... 21Figure 9: Typical Bus Protocol ....................................................................................................................... 72Figure 10: Command Token Format .............................................................................................................. 73Figure 11: Response Token Format ................................................................................................................ 83Figure 12: Data Packet Transfer ..................................................................................................................... 89Figure 13: Data Packet Format: 1-Bit Bus (only DAT0 used) ............................................................................. 89Figure 14: Data Packet Format: 4-Bit Bus (DAT[3:0] used) ............................................................................... 89Figure 15: Data Packet Format: 8-Bit Bus (DAT[7:0] used) ............................................................................... 90Figure 16: CRC7 Generator/Checker .............................................................................................................. 91Figure 17: CRC16 Generator/Checker ............................................................................................................ 92Figure 18: CRC Status .................................................................................................................................... 93Figure 19: MMC Mode NO RESPONSE Operation ........................................................................................... 96Figure 20: MMC Mode NO DATA Operation Without a Busy Indicator ............................................................ 97Figure 21: MMC Mode NO DATA Operation With a Busy Indicator .................................................................. 97Figure 22: MMC Mode Multiple-Block Read Operation ................................................................................... 98Figure 23: MMC Mode Multiple-Block Write Operation .................................................................................. 99Figure 24: e·MMC Memory Partitions Prior to PARTITION Operation ............................................................. 100Figure 25: Example of Partitions and User Data Area Configuration ............................................................... 101Figure 26: General-Purpose and Enhanced User Data Area Parameter-Setting Flow Chart .............................. 104Figure 27: Write Protect Condition Transition Due to Assertion of RST_n Signal ............................................. 107Figure 28: Boot Partitions ............................................................................................................................. 108Figure 29: Boot Mode Operation Timing ....................................................................................................... 110Figure 30: Alternative Boot Mode Timing ...................................................................................................... 112Figure 31: Boot Mode State Diagram ............................................................................................................. 113Figure 32: Card Identification Mode State Diagram ....................................................................................... 116Figure 33: Data Transfer Mode State Diagram ............................................................................................... 120Figure 34: Relationships Between Write Blocks, Erase Groups, and WPGs ....................................................... 162Figure 35: Bus Circuitry Diagram (MLC e·MMC) ............................................................................................ 164Figure 36: Bus Signal Levels (MLC e·MMC) .................................................................................................... 166Figure 37: Device Power Diagram (MLC e·MMC) ........................................................................................... 167Figure 38: Power-On Sequence ..................................................................................................................... 169Figure 39: RST_n Signal During Power-On Period .......................................................................................... 171Figure 40: Power Cycle ................................................................................................................................. 172Figure 41: Bus and Device Interface Timing .................................................................................................. 177Figure 42: BOOT Operation Timing with Termination Between Consecutive Data Blocks ................................ 179Figure 43: BOOT Operation Timing with Termination During Transfer .......................................................... 180Figure 44: Alternative BOOT Operation Timing with Termination Between Consecutive Data Blocks .............. 181Figure 45: Alternative BOOT Operation Timing with Termination During Transfer ......................................... 182Figure 46: Bus Mode Change Timing (push-pull to open drain) ...................................................................... 182Figure 47: SEND_OP_COND (CMD1) and ALL_SEND_CID (CMD2) Timing .................................................... 183Figure 48: SET_RCA (CMD3) Timing ............................................................................................................. 183Figure 49: Data Transfer Mode Timing .......................................................................................................... 184Figure 50: R1b Response Timing ................................................................................................................... 184




Figure 51: Timing Response End to Next Command Start (data transfer mode) ............................................... 185Figure 52: Command Sequences Timing (all modes) ..................................................................................... 185Figure 53: READ_SINGLE_BLOCK (CMD17) Timing ...................................................................................... 186Figure 54: READ_MULTIPLE_BLOCK (CMD18) Timing ................................................................................. 187Figure 55: STOP_TRANSMISSION (CMD12) Timing ...................................................................................... 187Figure 56: WRITE_BLOCK (CMD24) Timing .................................................................................................. 188Figure 57: WRITE_MULTIPLE_BLOCK (CMD25) Timing ................................................................................ 189Figure 58: STOP_TRANSMISSION (CMD12) Timing During Data Transfer From the Host ............................... 190Figure 59: STOP_TRANSMISSION (CMD12) Timing During CRC Status Transmission to the Host ................... 191Figure 60: STOP_TRANSMISSION (CMD12) Timing After Last Data Block While Device is Programming ......... 192Figure 61: STOP_TRANSMISSION (CMD12) Timing After Last Data Block When Device is Idle ........................ 193Figure 62: BUSTEST_W (CMD19) and BUSTEST_R (CMD14) Timing (example of 4-bit bus test) ...................... 195Figure 63: Hardware Reset Waveform ........................................................................................................... 196Figure 64: Hardware Reset Noise Filtering Timing ......................................................................................... 196Figure 65: Scenario 1: e·MMC Device Fails to Reset ........................................................................................ 198Figure 66: Scenario 2: e·MMC Device Resets .................................................................................................. 199




General DescriptionMicron e·MMC is a communication and mass data storage device that includes a Multi-MediaCard (MMC) interface, a NAND Flash component, and a controller on an ad-vanced 11-signal bus, which is compliant with the MMC system specification. Its lowcost, small size, Flash technology independence, and high data throughput makee·MMC ideal for smart phones, digital cameras, PDAs, MP3 players, and other portableapplications.

The nonvolatile e·MMC draws no power to maintain stored data, delivers high perform-ance across a wide range of operating temperatures, and resists shock and vibrationdisruption.

4GB, 8GB, 16GB, 32GB: e·MMCGeneral Description



Signal Descriptions

Table 1: Signal Descriptions

Symbol Type Description

CLK Input Clock: Each cycle of the clock directs a transfer on the command line and on the data line(s). Thefrequency can vary between the minimum and the maximum clock frequency.

CMD I/O Command: This signal is a bidirectional command channel used for command and response trans-fers. The CMD signal has two bus modes: open-drain mode and push-pull mode (see OperatingModes). Commands are sent from the MMC host to the device, and responses are sent from thedevice to the host.

DAT[7:0] I/O Data I/O: These are bidirectional data signals. The DAT signals operate in push-pull mode. By de-fault, after power-on or assertion of the RST_n signal, only DAT0 is used for data transfer. TheMMC controller can configure a wider data bus for data transfer either using DAT[3:0] (4-bitmode) or DAT[7:0] (8-bit mode). e·MMC includes internal pull-up resistors for data lines DAT[7:1].Immediately after entering the 4-bit mode, the device disconnects the internal pull-up resistors onthe DAT[3:1] lines. Upon entering the 8-bit mode, the device disconnects the internal pull-ups onthe DAT[7:1] lines.

RST_n Input Reset: The RST_n signal is used by the host for resetting the device, moving the device to the pre-idle state. By default, the RST_n signal is temporarily disabled in the device. The host must set ECSDregister byte 162, bits[1:0] to 0x1 to enable this functionality before the host can use it.

VCC Supply VCC: NAND interface (I/F) I/O and NAND Flash power supply.

VCCQ Supply VCCQ: e·MMC controller core and e·MMC I/F I/O power supply.

VSS1 Supply VSS: NAND I/F I/O and NAND Flash ground connection.

VSSQ1 Supply VSSQ: e·MMC controller core and e·MMC I/F ground connection.

VDDI Internal voltage node: At least a 0.1μF capacitor is required to connect VDDI to ground. A 1μF capac-itor is recommended. Do not tie to supply voltage or ground.

NC – No connect: No internal connection is present.

RFU – Reserved for future use: No internal connection is present. Leave it floating externally.

Note: 1. VSS and VSSQ are connected internally.

4GB, 8GB, 16GB, 32GB: e·MMCSignal Descriptions



153-Ball Signal Assignments

Figure 3: 153-Ball FBGA (top view, ball down)

RFU

DAT7

VCCQ

VCC

RFU

CLK

NC

VSSQ

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

A

B

C

D

E

F

G

H

J

K

L

M

N

P

NC

DAT3

VDDI

NC

NC

NC

NC

NC

NC

NC

NC

NC

VSSQ

NC

DAT0

DAT4

NC

NC

NC

NC

RFU

NC

NC

NC

NC

NC

NC

VCCQ

DAT1

DAT5

VSSQ

NC

VCCQ

VCCQ

VSSQ

DAT2

DAT6

RFU

RFU

VCC

VSS

RFU

RFU

RST_n

CMD

VSSQ

VCCQ

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

RFU

NC

NC

VSS

RFU

NC

NC

RFU

NC

NC

NC

RFU

VSS

NC

NC

NC

NC

NC

NC

RFU

VCC

NC

NC

NC

NC

NC

NC

RFU

RFU

RFU

VSS

VCC

RFU

NC

NC

RFU

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

1 2 3 4 5 6 7 8 9 10 11 12 13 14

Notes: 1. Some test pads on the device are not shown. They are not solder balls and are for Mi-cron internal use only.

2. Some previous versions of the JEDEC product or mechanical specification had definedreserved for future use (RFU) balls as no connect (NC) balls. NC balls assigned in the pre-vious specifications could have been connected to ground on the system board. Toenable new feature introduction, some of these balls are assigned as RFU in the v4.4mechanical specification. Any new PCB footprint implementations should use the newball assignments and leave the RFU balls floating on the system board.

4GB, 8GB, 16GB, 32GB: e·MMC153-Ball Signal Assignments



169-Ball Signal Assignments

Figure 4: 169-Ball FBGA (top view, ball down)

NC NC NC NC

NC NC NC NC

RFU

DAT7

VCCQ

VCC

RFU

CLK

NC

VSSQ

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

A

B

C

D

E

F

G

H

J

K

L

M

N

P

NC

DAT3

VDDI

NC

NC

NC

NC

NC

NC

NC

NC

NC

VSSQ

NC

DAT0

DAT4

NC

NC

NC

NC

RFU

NC

NC

NC

NC

NC

NC

VCCQ

DAT1

DAT5

VSSQ

NC

VCCQ

VCCQ

VSSQ

DAT2

DAT6

RFU

RFU

VCC

VSS

RFU

RFU

RST_n

CMD

VSSQ

VCCQ

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

RFU

NC

NC

VSS

RFU

NC

NC

RFU

NC

NC

NC

RFU

VSS

NC

NC

NC

NC

NC

NC

RFU

VCC

NC

NC

NC

NC

NC

NC

RFU

RFU

RFU

VSS

VCC

RFU

NC

NC

RFU

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

1 2 3 4 5 6 7 8 9 10 11 12 13 14

NC

NC NC

NC

NC

NC NC

NC

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

AG

AH

1

Notes: 1. Empty balls do not denote actual solder balls; they are position indicators only.




2. Some test pads on the device are not shown. They are not solder balls and are for Mi-cron internal use only.

3. Some previous versions of the JEDEC product or mechanical specification had definedreserved for future use (RFU) balls as no connect (NC) balls. NC balls assigned in the pre-vious specifications could have been connected to ground on the system board. Toenable new feature introduction, some of these balls are assigned as RFU in the v4.4mechanical specification. Any new PCB footprint implementations should use the newball assignments and leave the RFU balls floating on the system board.




153-Ball DM Package Dimensions

Figure 5: 153-Ball FBGA (package code DM)

Index

1.2 MAX

0.17 MIN

Index

0.5 TYP

Test pads

0.91 ±0.1

Seatingplane

A

0.08 A

153X Ø0.3

0.5 TYP

6.5 CTR

6.5CTR

13 ±0.1

11.5 ±0.1

14 12 10 8 6 4 213 11 9 7 5 3 1

ABCDEFGHJKLMNP

Solder ball material:LF35.Dimensions apply tosolder balls post-reflowon Ø0.27 SMD ball pads.

Notes: 1. Dimensions are in millimeters.2. Test pads are for Micron internal use only; these are not solder balls.

4GB, 8GB, 16GB, 32GB: e·MMC153-Ball DM Package Dimensions



169-Ball DH Package Dimensions

Figure 6: 169-Ball FBGA (package code DH)

Ball A1 IDBall A1 ID

0.08 A A

1.05 ±0.1

169X Ø0.3Solder ballmaterial: LF35.Dimensions applyto solder ballspost-reflow onØ0.27 SMD ballpads.

13.5 CTR

6.255.25

18 ±0.1

0.5TYP

0.5 TYP

6.5 CTR

12 ±0.1

1.4 MAX

0.17 MIN

Seatingplane

14 12 10 8 6 4 213 11 9 7 5 3 1

ABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAH


4GB, 8GB, 16GB, 32GB: e·MMC169-Ball DH Package Dimensions



169-Ball DI Package Dimensions

Figure 7: 169-Ball FBGA (package code DI)

IndexIndex

0.08 A A

0.91 ±0.1

169X Ø0.3Solder ballmaterial: LF35.Dimensionsapply to solder ballspost-reflow on Ø0.27SMD ball pads.

6.255.25

16 ±0.1

0.5TYP

13.5CTR

0.5 TYP

6.5 CTR

12 ±0.1

1.2 MAX

0.17 MIN

36X Ø0.325on pitch

Ni/Au platedtest pads

Seatingplane

14 12 10 8 6 4 213 11 9 7 5 3 1

ABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAH


4GB, 8GB, 16GB, 32GB: e·MMC169-Ball DI Package Dimensions



Architecture

Figure 8: e·MMC Functional Block Diagram

RST_n

CMD

CLK

VDDI

VCC

VCCQ

DAT[7:0]

VSS1

VSSQ1

MMCcontroller

e·MMC

NAND Flash

Registers

OCR CSD RCA

CID ECSD DSR

Note: 1. These are internally connected.

MMC Protocol Independent of NAND Flash TechnologyThe MMC specification defines the communication protocol between a host and a de-vice. The protocol is independent of the NAND Flash features included in the device.The device has an intelligent on-board controller that manages the MMC communica-tion protocol.

The controller also handles block management functions such as logical block alloca-tion and wear leveling. These management functions require complex algorithms anddepend entirely on NAND Flash technology (generation or memory cell type).

The device handles these management functions internally, making them invisible tothe host processor.

4GB, 8GB, 16GB, 32GB: e·MMCArchitecture



Defect and Error ManagementMicron e·MMC incorporates advanced technology for defect and error management. Ifa defective block is identified, the device completely replaces the defective block withone of the spare blocks. This process is invisible to the host and does not affect dataspace allocated for the user.

The device also includes a built-in error correction code (ECC) algorithm to ensure thatdata integrity is maintained.

To make the best use of these advanced technologies and ensure proper data loadingand storage over the life of the device, the host must exercise the following precautions:

• Check the status after WRITE, READ, and ERASE operations.

• Avoid power-down during WRITE and ERASE operations.

MMC Controller RegistersThe MMC controller includes six registers: the operating conditions (OC) register, thecard identification (CID) register, the card-specific data (CSD) register, the extended card-specific data (ECSD) register, the relative card address (RCA) register, and the driverstage (DS) register. These can be accessed only by corresponding commands. The OC,CID, and CSD registers carry the device- and content-specific information, while the DSand RCA registers are configuration registers used for storing actual configuration pa-rameters. The ECSD register carries both device-specific information and actual config-uration parameters.

4GB, 8GB, 16GB, 32GB: e·MMCArchitecture



OC RegisterThe 32-bit operating conditions (OC) register always shows the fixed data (shown be-low). This does not reflect any e·MMC voltage ranges. In addition, this register includesa status bit. This status bit is set if the device power-on sequence has completed. TheOC register will be implemented in all e·MMC devices.

Table 2: OC Register Settings

OC Bits Voltage Window OC Value

[6:0] Reserved 000 0000b

7 1.70–1.95V 1b

[14:8] 2.0–2.7V 000 0000b

[23:15] 2.7–3.6V 1 1111 1111b

[28:24] Reserved 0 0000b

[30:29] Access mode00b (byte mode)

10b (sector mode)

00b (1GB, 2GB)10b (>2GB)

31 Device power-on status bit (busy)1

Note: 1. Bit 31 is set to LOW if the device has not completed the power-on routine.

4GB, 8GB, 16GB, 32GB: e·MMCOC Register



CID RegisterThe card identification (CID) register is 128 bits wide. It contains the device identifica-tion information used during the card identification phase as required by e·MMCprotocol. Each device is created with a unique identification number.

Table 3: CID Register Field Parameters

Name Field Width CID Bits CID Value

Manufacturer ID MID 8 [127:120] 0x13

Reserved – 6 [119:114] –Card/BGA CBX 2 [113:112] –OEM/application ID OID 8 [111:104] –Product name PNM 48 [103:56] –Product revision PRV 8 [55:48] –Product serial number PSN 32 [47:16] –Manufacturing date MDT 8 [15:8] –CRC7 checksum CRC 7 [7:1] –Not used; always 1 – 1 0 –

CID Register Fields

MID Field (bits[127:120])The MID field in the CID register is an 8-bit binary number that identifies the devicemanufacturer. The MID number is controlled, defined, and allocated to each devicemanufacturer by JEDEC.

CBX Field (bits[113:112])The CBX field in the CID register indicates the device type.

Table 4: CBX Field Device Types

CBX Bytes Description

[113:112] Type

00 Card (removable)

01 BGA/MCP

10 PoP

11 Reserved

OID Field (bits[111:104])The OID field in the CID register is an 8-bit binary number that identifies the deviceOEM and the device contents when used as distribution media on ROM or NAND Flashdevices. The OID number is controlled, defined, and allocated to a device manufacturerby JEDEC.

4GB, 8GB, 16GB, 32GB: e·MMCCID Register



PNM Field (bits[103:56])The PNM field in the CID register is the controller revision code string. The string is 6ASCII characters long. Refer to the controller revision code in Part Numbering Informa-tion.

PRV Field (bits[55:48])The PRV field in the CID register is the product revision, which is composed of 2 binarycoded decimal (BCD) digits, 4 bits each, representing an n.m revision number. The n isthe most significant nibble, and m is the least significant nibble. For example, the PRVbinary value field for product revision 6.2 is 0110 0010.

PSN Field (bits[47:16])The PSN field in the CID register is a 32-bit unsigned binary integer.

MDT Field (bits[15:8])The MDT field in the CID register is the manufacturing date, which is composed of 2hexadecimal digits, 4 bits each, representing a 2-digit date code m/y. The most signifi-cant nibble, the m field, is the month code (1 = January). The y field is the year code(0 = 1997). For example, the binary value of the MDT field for production date April2000 is 0100 0011.

CRC Field (bits[7:1])The CRC7 field in the CID register is a 7-bit checksum.

4GB, 8GB, 16GB, 32GB: e·MMCCID Register Fields



CSD Register (MLC e·MMC)The card-specific data (CSD) register provides information about accessing the devicecontents. The CSD register defines the data format, error correction type, maximum da-ta access time, and data transfer speed, as well as whether the DS register can be used.The programmable part of the register (entries marked with W or E in the following ta-ble) can be changed by the PROGRAM_CSD (CMD27) command.

Table 5: CSD Register Field Parameters (MLC e·MMC)

Name Field WidthCell

Type1CSDBits

CSDValue

ValueDescription

CSD structure CSD_STRUCTURE 2 R [127:126] 2h CSD1.2

System specification version SPEC_VERS 4 R [125:122] 4h Version 4.41

Reserved2 – 2 – [121:120] – –Data read access time 1 TAAC 8 R [119:112] 2Fh 20ms

Data read access time 2 in CLK cycles(NSAC × 100)

NSAC 8 R [111:104] 01h 100

Maximum bus clock frequency TRAN_SPEED 8 R [103:96] 32h 26 MHz

Card command classes CCC 12 R [95:84] 0F5h 0, 2, 4, 5, 6, 7

Maximum read data block length READ_BL_LEN 4 R [83:80] 9h 512 bytes

Partial blocks for reads supported READ_BL_PARTIAL 1 R 79 0b No

Write block misalignment WRITE_BLK_MISALIGN 1 R 78 0b No

Read block misalignment READ_BLK_MISALIGN 1 R 77 0b No

DS register implemented DSR_IMP 1 R 76 0b No

Reserved – 2 – [75:74] – –Device size: C_SIZE 12 R [73:62] FFFh 4095

Maximum read current at VDD,min VDD_R_CURR_MIN 3 R [61:59] 6h 60mA

Maximum read current at VDD,max VDD_R_CURR_MAX 3 R [58:56] 6h 80mA

Maximum write current at VDD,min VDD_W_CURR_MIN 3 R [55:53] 6h 60mA

Maximum write current at VDD,max VDD_W_CURR_MAX 3 R [52:50] 6h 80mA

Device size multiplier C_SIZE_MULT 3 R [49:47] 7h 512

Erase group size ERASE_GRP_SIZE 5 R [46:42] 1Fh 32

Erase group size multiplier ERASE_GRP_MULT 5 R [41:37] 1Fh 32

Write protect group size WP_GRP_SIZE 5 R [36:32] 07h 8

Write protect group enable WP_GRP_ENABLE 1 R 31 1b Yes

Manufacturer default ECC DEFAULT_ECC 2 R [30:29] 0h None

Write-speed factor R2W_FACTOR 3 R [28:26] 4h 16

Maximum write data block length WRITE_BL_LEN 4 R [25:22] 9h 512 byte

Partial blocks for writes supported WRITE_BL_PARTIAL 1 R 21 0b No

Reserved – 4 – [20:17] – –Content protection application CONTENT_PROT_APP 1 R 16 0b Not supported

File-format group FILE_FORMAT_GRP 1 R/W 15 0b HDD-likefile system

4GB, 8GB, 16GB, 32GB: e·MMCCSD Register (MLC e·MMC)



Table 5: CSD Register Field Parameters (MLC e·MMC) (Continued)

Name Field WidthCell

Type1CSDBits

CSDValue

ValueDescription

Copy flag (OTP) COPY 1 R/W 14 1b Copy

Permanent write protection PERM_WRITE_PROTECT 1 R/W 13 0b No

Temporary write protection TMP_WRITE_PROTECT 1 R/W/E 12 0b No

File format FILE_FORMAT 2 R/W [11:10] 0h HDD-likefile system

ECC ECC 2 R/W/E [9:8] 0h None

CRC CRC 7 R/W/E [7:1]

Not used; always 1 – 1 – 0 1b 1

Notes: 1. R = Read-only

R/W = One-time programmable and readable

R/W/E = Multiple writable with value kept after a power cycle, assertion of the RST_nsignal, and any CMD0 reset, and readable

TBD = To be determined

2. Reserved bits should be read as 0.

CSD Register FieldsField descriptions detail CSD fields and data types. All bit strings are interpreted as binary-coded numbers starting with the left bit first, unless stated otherwise.

CSD_STRUCTURE Field (bits[127:126])The CSD_STRUCTURE field in the CSD register describes the version of the CSD structure.

Table 6: CSD_STRUCTURE Field Values

CSD_STRUCTURE CSD Structure Version Valid for System Specification Version

0 CSD version 1.0 Versions 1.0–1.2

1 CSD version 1.1 Versions 1.4–2.2

2 CSD version 1.2 Versions 3.1, 3.2, 3.31, 4.0, 4.1, 4.2, 4.3, 4.4,4.41

3 Version is coded in the CSD_STRUCTURE byte in the ECSD register

4GB, 8GB, 16GB, 32GB: e·MMCCSD Register Fields



SPEC_VERS Field (bits[125:122])The SPEC_VERS field in the CSD register defines the e·MMC system specification ver-sion supported by the device.

Table 7: SPEC_VERS Field Values

SPEC_VERS System Specification Version Number

0 Versions 1.0–1.2

1 Versions 1.4

2 Versions 2.0–2.2

3 Versions 3.1, 3.2, 3.31

4 Versions 4.0, 4.1, 4.2, 4.3, 4.4, 4.41

[15:5] Reserved

TAAC Field (bits[119:112])The TAAC field in the CSD register defines the asynchronous part of the data access time.

Table 8: TAAC Field Bit Position Codes

TAAC Bit Position Code

[2:0] Time unit 0 = 1ns1 = 10ns2 = 100ns3 = 1μs4 = 10μs5 = 100μs6 = 1ms7 = 10ms

[6:3] Multiplier factor 0 = Reserved1 = 1.02 = 1.23 = 1.34 = 1.55 = 2.06 = 2.57 = 3.08 = 3.59 = 4.0A = 4.5B = 5.0C = 5.5D = 6.0E = 7.0F = 8.0

7 Reserved




NSAC Field (bits[111:104])The NSAC field in the CSD register defines the typical case for the clock dependency ofthe data access time. The unit for the NSAC field is 100 clock cycles. Therefore, the max-imum value for the clock-dependent part of the data access time is 25,500 clock cycles.The total access time is calculated based on both the TAAC and NSAC fields. The accesstime must be computed by the host for the actual clock rate. The read access timeshould be interpreted as a typical delay for the first data bit of a data block or stream.

TRAN_SPEED Field (bits[103:96])The TRAN_SPEED field in the CSD register defines the maximum bus clock frequency.The following table shows the clock frequency when the device is not in high-speedmode. For devices supporting specification version 4.0 and higher, the value is 20 MHz(0x2A).

Table 9: TRAN_SPEED Field Bit Position Codes

TRANS_SPEED Bit Code

[2:0] Frequency unit 0 = 100 KHz1 = 1 MHz2 = 10 MHz3 = 100 MHz[7:4] = Reserved

[6:3] Multiplier factor 0 = Reserved1 = 1.02 = 1.23 = 1.34 = 1.55 = 2.06 = 2.67 = 3.08 = 3.59 = 4.0A = 4.5B = 5.2C = 5.5D = 6.0E = 7.0F = 8.0

7 Reserved




CCC Field (bits[95:84])The e·MMC command set is divided into subsets or command classes. The card com-mand class (CCC) field in the CSD register defines which e·MMC command classes aresupported by the device. A value of 1 in a CCC bit means that the corresponding com-mand class is supported. For command class definitions, see Command Classes.

Table 10: CCC Field Bit Codes

CCC Bit Supported Card Command Class

0 Class 0

2 Class 2

4 Class 4

5 Class 5

6 Class 6

7 Class 7

10 Class 10

11 Class 11

READ_BL_LEN Field (bits[83:80])The READ_BL_LEN field in the CSD register indicates the supported maximum read da-ta block length. The data block length is computed as 2READ_BL_LEN and is most likely inthe range of 1, 2, 4,… 2048 bytes. Support for 512-byte read access is mandatory for alldevices, and the devices must be in 512-byte block length mode by default after power-on or a software reset.

Table 11: READ_BL_LEN Field Block Length Codes

READ_BL_LEN Block Length

0 20 = 1 byte

1 21 = 2 bytes

···

···

11 211 = 2048 bytes

[15:12] Reserved




READ_BL_PARTIAL Field (bit 79)The READ_BL_PARTIAL field in the CSD register determines whether partial block sizescan be used in block read commands.

For densities up to 2GB in byte access mode:

• READ_BL_PARTIAL = 0 means that the READ_BL_LEN block size can be used for block-oriented data transfers.

• READ_BL_PARTIAL = 1 means that smaller blocks can also be used. The minimumblock size is equal to the minimum addressable unit (1 byte).

For densities greater than 2GB in sector access mode:

• READ_BL_PARTIAL = 0 means that only the 512 bytes and the READ_BL_LEN blocksize can be used for block-oriented data transfers.

• READ_BL_PARTIAL = 1 means that smaller blocks than indicated in READ_BL_LENcan also be used. The minimum block size is equal to the minimum addressable unit(1 sector or 512 bytes).

WRITE_BLK_MISALIGN Field (bit 78)The WRITE_BLK_MISALIGN field in the CSD register determines whether the datablock to be written by one command can be spread over more than one physical blockof the memory device. The size of the memory block is defined in WRITE_BL_LEN.

• WRITE_BLK_MISALIGN = 0 means that crossing physical block boundaries is invalid.

• WRITE_BLK_MISALIGN = 1 means that crossing physical block boundaries is suppor-ted.

READ_BLK_MISALIGN Field (bit 77)The READ_BLK_MISALIGN field in the CSD register determines whether the data blockto be read by one command can be spread over more than one physical block of thememory device. The size of the memory block is defined in READ_BL_LEN.

• READ_BLK_MISALIGN = 0 means that crossing physical block boundaries is invalid.

• READ_BLK_MISALIGN = 1 means that crossing physical block boundaries is supported.

DSR_IMP Field (bit 76)The DSR_IMP field in the CSD register determines whether the configurable driverstage is integrated on the device. If DSR_IMP is set to 1, a driver stage register must alsobe implemented.

Table 12: DSR_IMP Field Codes

DSR_IMP DS Register Type

0 DS register is not implemented

1 DS register implemented




C_SIZE Field (bits[73:62])The C_SIZE field computes the device memory capacity for device densities up to 2GB.See SEC_COUNT Field (bytes[215:212]) (page 50) for densities higher than 2GB. Fordensities higher than 2GB, this register should be set to the maximum possible value(0xFFF). The memory capacity of the device is computed from the entries C_SIZE,C_SIZE_MULT, and READ_BL_LEN as follows:

Memory capacity = BLOCKNR × BLOCK_LEN

where

BLOCKNR = (C_SIZE + 1) × MULT

MULT = 2 C_SIZE_MU LT + 2, (C_SIZE_MU LT < 8)

BLOCK_LEN = 2 READ_BL_LEN , (READ_BL_LEN < 12)

Therefore, the maximum capacity that can be coded is 4096 × 512 × 2048 = 4GB.

Example: A 4MB device with BLOCK_LEN = 512 can be coded by C_SIZE_MULT = 0 andC_SIZE = 2047.

VDD_R_CURR_MIN Field (bits[61:59]), VDD_W_CURR_MIN Field (bits[55:53])The values in these fields in the CSD register are valid when the device is not in high-speed mode. When the device is in high-speed mode, the current consumption isdetermined by the host from the power classes defined in the PWR_CL_ff_vvv fields inthe ECSD register.

The maximum values for read and write currents at the minimum power supply are co-ded in the following table.

Table 13: VDD_R_CURR_MIN, VDD_W_CURR_MIN Field Values

VDD_R_CURR_MINVDD_W_CURR_MIN

Codes for Maximum Read/Write CurrentConsumption Values

2:0 0 = 0.5mA1 = 1mA2 = 5mA3 = 10mA4 = 25mA5 = 35mA6 = 60mA7 = 100mA




VDD_R_CURR_MAX Field (bits[58:56]), VDD_W_CURR_MAX Field (bits[52:50])The values in these fields in the CSD register are valid when the device is not in high-speed mode. When the device is in high-speed mode, the current consumption isdetermined by the host from the power classes defined in the PWR_CL_ff_vvv fields inthe ECSD register.

The maximum values for read and write currents at the maximum power supply arecoded in the following table.

Table 14: VDD_R_CURR_MAX, VDD_W_CURR_MAX Field Values

VDD_R_CURR_MAXVDD_W_CURR_MAX

Codes for Maximum Read/Write CurrentConsumption Values

[2:0] 0 = 1mA1 = 5mA2 = 10mA3 = 25mA4 = 35mA5 = 45mA6 = 80mA7 = 200mA

C_SIZE_MULT Field (bits[49:47])The C_SIZE_MULT field in the CSD register is used for coding the factor MULT for com-puting the total device size. The MULT is defined as 2(C_SIZE_MULT + 2). For devicedensities greater than 2GB, this field should be set to the maximum possible value (0x7).

Table 15: C_SIZE_MULT Field Values

C_SIZE_MULT Codes MULT Computations

0 22 = 4 bytes

1 23 = 8 bytes

2 24 = 16 bytes

3 25 = 32 bytes

4 26 = 64 bytes

5 27 = 128 bytes

6 28 = 256 bytes

7 29 = 512 bytes




ERASE_GRP_SIZE Field (bits[46:42])The ERASE_GRP_SIZE field in the CSD register contains a 5-bit binary coded value usedto compute the size of the erasable unit of the device. The size of the erasable unit, orthe erase group, is determined by the ERASE_GRP_SIZE and the ERASE_GRP_MULT en-tries in the CSD register. The size of the erasable unit is computed as follows:

Size of erasable unit = (ERASE_GRP_SIZE + 1) × (ERASE_GRP_MULT + 1)

This size is defined as the minimum number of write blocks that can be erased with asingle ERASE command.

ERASE_GRP_MULT Field (bits[41:37])The ERASE_GRP_MULT field in the CSD register is a 5-bit binary coded value used tocalculate the size of the erasable unit of the device.

WP_GRP_SIZE Field (bits[36:32])The WP_GRP_SIZE field in the CSD register is the size of a write-protected group. Thisregister contains a 5-bit binary coded value defining the number of erase groups thatcan be write protected. The actual size is computed by increasing the number of erasegroups by one. A value of 0 means 1 erase group; a value of 31 means 32 erase groups.

WP_GRP_ENABLE Field (bit 31)The WP_GRP_ENABLE field in the CSD register indicates whether group write protec-tion is enabled. A value of 0 indicates that no group write protection is enabled.

DEFAULT_ECC Field (bits[30:29])The DEFAULT_ECC field in the CSD register is set by the device manufacturer. Thisfield defines the error correction code that is recommended for use. The field definitionis the same as for the ECC field.

R2W_FACTOR Field (bits[28:26])The R2W_FACTOR field in the CSD register defines the typical block programming timeas a multiple of the read access time.

Table 16: R2W_FACTOR Field Values

R2W_FACTOR Multiples of Read Access Time

0 1

1 2

2 4

3 8

4 16

5 32

6 64

7 128




WRITE_BL_LEN Field (bits[25:22])The WRITE_BL_LEN field in the CSD register indicates the supported maximum writedata block length. Support for 512-byte write access is mandatory for all devices, anddevices must be in 512-byte block length mode by default after power-on or a softwarereset. See READ_BL_LEN Field (bits[83:80]) (page 30) for field coding.

WRITE_BL_PARTIAL Field (bit 21)The WRITE_BL_PARTIAL field in the CSD register defines whether partial block sizescan be used in block write commands.

For densities up to 2GB in byte access mode:

• WRITE_BL_PARTIAL = 0 means that the WRITE_BL_LEN block size can be used forblock oriented data transfers.

• WRITE_BL_PARTIAL = 1 means that smaller blocks can also be used. The minimumblock size is 1 byte.

For densities greater than 2GB in sector access mode:

• WRITE_BL_PARTIAL = 0 means that only the 512 bytes and the WRITE_BL_LEN blocksize can be used for block oriented data transfers.

• WRITE_BL_PARTIAL = 1 means that smaller blocks can also be used. The minimumblock size is equal to the minimum addressable unit (1 sector of 512 bytes).

CONTENT_PROT_APP Field (bit 16)The CONTENT_PROT_APP field in the CSD register indicates whether the content pro-tection application is supported. Devices that implement the content protection appli-cation preset this bit to 1.

FILE_FORMAT_GRP Field (bit 15)The FILE_FORMAT_GRP field in the CSD register indicates the selected group of fileformats. This field is read-only for ROM. Use of this field is shown in Table 17(page 36).

COPY Field (bit 14)The COPY field in the CSD register indicates whether the content is original (0) or acopy (1). The COPY bit for one-time programmable (OTP) and multiple-time program-mable (MTP) devices is set to 1. This setting identifies the device content as a copy. TheCOPY bit is a one-time programmable bit.

PERM_WRITE_PROTECT Field (bit 13)The PERM_WRITE_PROTECT field in the CSD register permanently protects the entiredevice contents (boot, RPMB, and all user area partitions) against overwriting or eras-ing. (All data write and erase commands for this device are permanently disabled). Thedefault value is 0 (the device is not permanently write protected.

Setting permanent write protection for the entire device takes precedence over any oth-er write protection mechanism currently enabled on the device. The ability to perma-nently protect the device by setting PERM_WRITE_PROTECT to 1 can be disabled bysetting CD_PERM_WP_DIS (ECSD register byte 171, bit 6). If CD_PERM_WP_DIS is set




to 1 and the host attempts to set PERM_WRITE_PROTECT, the operation fails, and errorbit 19 is set in the status register.

TMP_WRITE_PROTECT Field (bit 12)The TMP_WRITE_PROTECT field in the CSD register temporarily protects the contentsof the entire device from being overwritten or erased. All write and erase commands forthe device are temporarily disabled. This bit can be set and reset. The default value is 0(the device is not write protected).

Temporary write protection only applies to write protection groups on the device whereanother write protection mechanism (password, permanent, or power-on) has not al-ready been enabled.

FILE_FORMAT Field (bits[11:10])The FILE_FORMAT field in the CSD register indicates the file format of the device. Thisfield is read-only for ROM. File formats are defined in the following table.

Table 17: FILE_FORMAT Field Definitions

FILE_FORMAT_GRP FILE_FORMAT Type

0 0 HDD-like file systems with partition table

0 1 DOS FAT file system with boot sector and no parti-tion table

0 2 Universal file format

0 3 Others/unknown

1 0, 1, 2, 3 Reserved

ECC Field (bits[9:8])The ECC field in the CSD register defines the error correction code used for storing dataon the device. This field is used by the host or application to decode user data. The fol-lowing table defines the ECC field formats. Micron e·MMC supports internal ECC, sothe host is not required to set this bit.

Table 18: ECC Field Formats

ECC ECC Type Maximum Number of Correctable Bits

0 None (default) None

1 BCH (542, 512) 3

2–3 Reserved –

CRC Field (bits[7:1])The CRC field in the CSD register stores the checksum for the CSD contents. For anyCSD modification, the host must recalculate the checksum. The default checksum valueis the initial CSD contents.




ECSD Register (MLC e·MMC)The 512-byte extended card-specific data (ECSD) register defines device properties andselected modes. The most significant 320 bytes are the properties segment. This seg-ment defines device capabilities and cannot be modified by the host. The lower 192bytes are the modes segment. The modes segment defines the configuration in whichthe device is working. The host can change the properties of modes segments using theSWITCH command.

Table 19: ECSD Register Field Parameters (MLC e·MMC)

Name FieldSize

(Bytes)Cell

Type1ECSDBytes ECSD Value

Properties Segment

Reserved2 – 7 – [511:505] –Supported command sets S_CMD_SET 1 R 504 1h

HPI features HPI_FEATURES 1 R 503 0h

Background operations support BKOPS_SUPPORT 1 R 502 0h

Reserved2 – 255 – [501:247] –Background operations status BKOPS_STATUS 1 R 246 –Number of correctly programmed sectors CORRECTLY_PRG_

SECTORS_NUM4 R [245:242] –

First initialization time after partitioning(first CMD1 to device ready)

INI_TIMEOUT_AP 1 R 241 14h

Reserved2 – 1 – 240 –Power class for 52 MHz, DDR at 3.6V PWR_CL_DDR_52_360 1 R 239 0h

Power class for 52 MHz, DDR at 1.95V PWR_CL_DDR_52_195 1 R 238 0h

Reserved2 – 2 – [237:236] –Minimum write performance for 8-bit at 52 MHzin DDR mode

MIN_PERF_DDR_W_8_52 1 R 235 0h

Minimum read performance for 8-bit at 52 MHzin DDR mode

MIN_PERF_DDR_R_8_52 1 R 234 0h

Reserved2 – 1 – 233 –TRIM multiplier TRIM_MULT 1 R 232 1h

Secure feature support SEC_FEATURE_SUPPORT 1 R 231 15h

SECURE ERASE multiplier SEC_ERASE_MULT 1 R 230 1h

SECURE TRIM multiplier SEC_TRIM_MULT 1 R 229 1h

Boot information BOOT_INFO 1 R 228 5h

Reserved2 – 1 – 227 –Boot partition size BOOT_SIZE_MULT 1 R 226 10h

Access size 4GB ACC_SIZE 1 R 225 6h

8GB 6h

16GB 6h

32GB 6h

4GB, 8GB, 16GB, 32GB: e·MMCECSD Register (MLC e·MMC)



Table 19: ECSD Register Field Parameters (MLC e·MMC) (Continued)

Name FieldSize

(Bytes)Cell


High-capacity erase unit size 4GB HC_ERASE_GP_SIZE 1 R 224 8h

8GB 8h

16GB 8h

32GB 8h

High-capacity erase timeout ERASE_TIMEOUT_MULT 1 R 223 1h

Reliable write-sector count REL_WR_SEC_C 1 R 222 8h

High-capacity write protect

group size

4GB HC_WP_GRP_SIZE 1 R 221 8h

8GB 8h

16GB 8h

32GB 8h

Sleep current (VCC) 4GB S_C_VCC 1 R 220 7h

8GB 7h

16GB 7h

32GB 8h

Sleep current (VCCQ) S_C_VCCQ 1 R 219 06h

Reserved – 1 – 218 –Sleep/awake timeout S_A_TIMEOUT 1 R 217 0Fh

Reserved2 – 1 – 216 –Sector count 4GB SEC_COUNT 4 R [215:212] 740000h

8GB E90000h

16GB 1D20000h

32GB 3B80000h

Reserved2 – 1 – 211 –Minimum write performance for 8-bit at 52 MHz MIN_PERF_W_8_52 1 R 210 08h

Minimum read performance for 8-bit at 52 MHz MIN_PERF_R_8_52 1 R 209 08h

Minimum write performance for 8-bit at 26 MHzand 4-bit at 52 MHz

MIN_PERF_W_8_26_4_52 1 R 208 08h

Minimum read performance for 8-bit at 26 MHzand 4-bit at 52 MHz

MIN_PERF_R_8_26_4_52 1 R 207 08h

Minimum write performance for 4-bit at 26 MHz MIN_PERF_W_4_26 1 R 206 08h

Minimum read performance for 4-bit at 26 MHz MIN_PERF_R_4_26 1 R 205 08h

Reserved2 – 1 – 204 –Power class for 26 MHz at 3.6V PWR_CL_26_360 1 R 203 00h

Power class for 52 MHz at 3.6V PWR_CL_52_360 1 R 202 00h



Partition switching timing PARTITION_SWITCH_TIME

1 R 199 0h





Name FieldSize

(Bytes)Cell


Out-of-interrupt busy timing OUT_OF_INTERRUPT_TIME

1 R 198 0h

Reserved2 – 1 – 197 –Card type CARD_TYPE 1 R 196 3h

Reserved2 – 1 – 195 –CSD structure version CSD_STRUCTURE 1 R 194 2h

Reserved2 – 1 – 193 –Extended CSD revision EXT_CSD_REV 1 R 192 5h

Modes Segment

Command set CMD_SET 1 R/W/E_P 191 0h

Reserved2 – 1 – 190 –Command set revision CMD_SET_REV 1 R 189 0h

Reserved2 – 1 – 188 –Power class POWER_CLASS 1 R/W/E_P 187 0h

Reserved2 – 1 – 186 –High-speed interface timing HS_TIMING 1 R/W/E_P 185 0h

Reserved2 – 1 – 184 –Bus width mode BUS_WIDTH 1 W/E_P 183 0h

Reserved2 – 1 – 182 –Erased memory content ERASED_MEM_CONT 1 R 181 0h

Reserved2 – 1 – 180 –Partition configuration PARTITION_CONFIG 1 R/W/E,

R/W/E_P179 0h

Boot configuration protection BOOT_CONFIG_PROT 1 R/W,R/W/C_P

178 0h

Boot bus width BOOT_BUS_WIDTH 1 R/W/E 177 0h

Reserved2 – 1 – 176 –High-density erase group definition ERASE_GROUP_DEF 1 R/W/E_P 175 0h

Reserved2 – 1 – 174 –Boot area write protection register BOOT_WP 1 R/W,

R/W/C_P173 0h

Reserved2 – 1 – 172 –User write protection register USER_WP 1 R/W,

R/W/C_P,R/W/E_P

171 0h

Reserved2 – 1 – 170 –Firmware configuration FW_CONFIG 1 R/W 169 0h

RPMB size RPMB_SIZE_MULT 1 R 168 1h





Name FieldSize

(Bytes)Cell


Write reliability setting register WR_REL_SET 1 R/W 167 0h

Write reliability parameter register WR_REL_PARAM 1 R 166 0h

Reserved2 – 1 – 165 –Manually start background operations BKOPS_START 1 W/E_P 164 –Enable background operations handshake BKOPS_EN 1 R/W 163 0h

Hardware reset function RST_n_FUNCTION 1 R/W 162 0h

HPI management HPI_MGMT 1 R/W/E_P 161 0h

Partitioning support PARTITIONING_SUPPORT 1 R 160 3h

Maximum enhanced area size 4GB MAX_ENH_SIZE_MULT 3 R [159:157] 0h

8GB 0h

16GB 0h

32GB 0h

Partitions attribute PARTITIONS_ATTRIBUTE 1 R/W 156 0h

Partitioning setting PARTITION_SETTING_COMPLETED

1 R/W 155 0h

General-purpose partition size GP_SIZE_MULT 12 R/W [154:143] 0h

Enhanced user data area size ENH_SIZE_MULT 3 R/W [142:140] 0h

Enhanced user data start address ENH_START_ADDR 4 R/W [139:136] 0h

Reserved2 – 1 – 135 –Bad block management mode SEC_BAD_BLK_MGMNT 1 R/W 134 0h

Reserved2 – 134 – [133:0] –

Notes: 1. R = Read-only

R/W = One-time programmable and readable

R/W/E = Multiple writable with the value kept after a power cycle, assertion of theRST_n signal, and any CMD0 reset and readable

R/W/C_P = Writable after the value is cleared by a power cycle and assertion of theRST_n signal (the value not cleared by CMD0 reset) and readable

R/W/E_P = Multiple writable with the value reset after a power cycle, assertion of theRST_n signal, and any CMD0 reset and readable

W/E_P = Multiple writable with the value reset after power cycle, assertion of the RST_nsignal, and any CMD0 reset and not readable

TBD = To be determined

2. Reserved bits should be read as 0.




ECSD Register Fields – Properties Segment

S_CMD_SET Field (byte 504)

Table 20: S_CMD_SET Field Values

Bit Supported Command Set

0 Standard MMC

1 Secure MMC

2 Content protection secure MMC

3 Secure MMC 2.0

4 ATA on MMC

[7:5] Reserved

HPI_FEATURES Field (byte 503)The HPI_FEATURES field in the ECSD register indicates whether the HPI feature is sup-ported and which implementation is used by the device.

Table 21: HPI_FEATURES Field Byte Format

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reserved HPI_IMPLEMENTATION HPI_SUPPORT

Table 22: HPI_FEATURES Field Bit Descriptions

Bit Field Value Description

[7:2] Reserved

1 HPI_IMPLEMENTATION 0 HPI mechanism implementation based on CMD13.

1 HPI mechanism implementation based on CMD12.

0 HPI_SUPPORT 0 HPI mechanism not supported (default).

1 HPI mechanism supported.

BKOPS_SUPPORT Field (byte 502)The BKOPS_SUPPORT field in the ECSD register indicates whether the background op-erations feature is supported by the device.

Table 23: BKOPS_SUPPORT Field Byte Format


Reserved SUPPORTED

4GB, 8GB, 16GB, 32GB: e·MMCECSD Register Fields – Properties Segment



Table 24: BKOPS_SUPPORT Field Bit Descriptions


[7:1] Reserved

0 SUPPORTED 0 Background operations are not supported. The fieldsBKOPS_STATUS, BKOPS_EN, BKOPS_START, and card statusbit URGENT_BKOPS are not supported.

1 Background operations are supported. The fields BKOPS_STA-TUS, BKOPS_EN, BKOPS_START, and card status bit UR-GENT_BKOPS are supported.

BKOPS_STATUS Field (byte 246)The BKOPS_STATUS field in the ECSD register indicates the level of background opera-tions urgency.

Table 25: BKOPS_STATUS Field Byte Format


Reserved OUTSTANDING

Table 26: BKOPS_STATUS Field Bit Descriptions


[7:2] Reserved

[1:0] HPI_IMPLEMENTATION 0 No operations required.

1 Operations outstanding (non-critical).

2 Operations outstanding (performance being impacted).

3 Operations outstanding (critical).

CORRECTLY_PRG_SECTORS_NUM Field (bytes[245:242])The CORRECTLY_PRG_SECTORS_NUM field in the ECSD register indicates how many512-byte sectors were successfully programmed by the last WRITE_MULTIPLE_BLOCK(CMD25) command.

Table 27: Number of Sectors Correctly Programmed

ECSD Byte CORRECTLY_PRG_SECTORS_NUM

245 CORRECTLY_PRG_SECTORS_NUM_3







Number of correctly programmed sectors =[CORRECTLY_PRG_SECTORS_NUM_3 × 224 +CORRECTLY_PRG_SECTORS_NUM_2 × 216 +CORRECTLY_PRG_SECTORS_NUM_1 × 28 +CORRECTLY_PRG_SECTORS_NUM_0 × 20]

INI_TIMEOUT_PA Field (byte 241)The INI_TIMEOUT_PA field in the ECSD register indicates the initialization maximumtimeout value during the first power-on after successful partitioning of the device. Allthe initialization timeouts during consecutive power-ons have a maximum timeout of 1second, as in the case of a nonpartitioned device.

Table 28: INI_TIMEOUT_PA Field Initialization Maximum Timeout Values

Value Initialization Maximum Timeout Value

0x00 Not defined

0x01 100ms × 1 = 100ms

···

···

0xFF 100ms × 255 = 25500ms

TRIM_MULT Field (byte 232)The TRIM_MULT field in the ECSD register is used to compute the TRIM function time-out. The timeout value for the TRIM operation inside a logical erase group is computedas follows:

TRIM timeout = 300ms × TRIM_MULT

If the host executes the TRIM operation including write sectors belonging to multipleerase groups, the total timeout value should be a multiple of the number of the erasegroups involved.

Table 29: TRIM_MULT Field TRIM Timeout Values

Value TRIM Timeout Value

0x00 Not defined

0x01 300ms × 1 = 300ms

···

···

0xFF 300ms × 255 = 76500ms

SEC_FEATURE_SUPPORT Field (byte 231)The SEC_FEATURE_SUPPORT field in the ECSD register enables the host to determinewhich secure data management features are supported by the device.




The bits in this field determine whether the ERASE (CMD38) command arguments aresupported and whether the host can manage the way defective portions of the memoryarray are retired by using SEC_BAD_BLK_MGMNT (ECSD register byte 134).

Table 30: SEC_FEATURE_SUPPORT Field Byte Format


Reserved SEC_GB_CL_EN Reserved SEC_BD_BLK_EN Reserved SEC_ER_EN

Table 31: SEC_FEATURE_SUPPORT Field Bit Descriptions


[7:5] Reserved

4 SEC_GB_CL_EN (R) 0x0 Device does not support the SECURE TRIM and TRIM opera-tions.

0x1 Device supports the SECURE TRIM and TRIM operations.

3 Reserved

2 SEC_BD_BLK_EN (R) 0x0 Device does not support the automatic SECURE PURGE opera-tion on retired defective portions of the array.

0x1 Device supports the automatic SECURE PURGE operation onretired defective portions of the array. When set, this bit ena-bles the host to set ECSD register byte 134(SEC_BAD_BLK_MGMNT).

1 Reserved

0 SECURE_ER_EN (R) 0x0 Device does not support SECURE PURGE operations.

0x1 Device supports SECURE PURGE operations. When set, this bitenables the host to set bit 31 of the argument for the ERASE(CMD38) command.

SEC_ERASE_MULT Field (byte 230)The SEC_ERASE_MULT field in the ECSD register is used to compute the SECUREERASE function timeout. The timeout value for the SECURE ERASE operation of onelogical erase group is computed as follows:

Secure erase timeout = 300ms × ERASE_TIMEOUT_MULT × SEC_ERASE_MULT

If the host executes the SECURE ERASE operation, including erase groups, the total time-out value should be a multiple of the number of the erase groups involved.

Table 32: SEC_ERASE_MULT Field SECURE ERASE Timeout Values

Value SECURE ERASE Timeout Value

0x00 Not defined

0x01 300ms × ERASE_TIMEOUT_MULT × 1

···

···




Table 32: SEC_ERASE_MULT Field SECURE ERASE Timeout Values (Contin-ued)

Value SECURE ERASE Timeout Value

0xFF 300ms × ERASE_TIMEOUT × 255

SEC_TRIM_MULT Field (byte 229)The SEC_TRIM_MULT field in the ECSD register is used to compute the SECURE TRIMfunction timeout. The timeout value for the SECURE TRIM operation of one logicalerase group is computed as follows:

Secure trim timeout = 300ms × ERASE_TIMEOUT_MULT × SEC_TRIM_MULT

If the host executes SECURE TRIM operation including write sectors belonging to multi-ple erase groups, the total timeout value should be a multiple of the number of theerase groups involved.

Table 33: SEC_TRIM_MULT Field SECURE TRIM Timeout Values

Value SECURE TRIM Timeout Value

0x00 Not defined

0x01 300ms × ERASE_TIMEOUT_MULT × 1

···

···

0xFF 300ms × ERASE_TIMEOUT × 255

BOOT_INFO Field (byte 228)The BOOT_INFO field in the ECSD register provides information about supported de-vice parameters during a BOOT operation. The only values currently valid for thisregister are 0x0, 0x1, 0x05, and 0x07. A device supporting dual data rate mode duringboot must also have bit 2 set.

Table 34: BOOT_INFO Field Byte Format


Reserved HS_BOOT_MODE DDR_BOOT_MODE ALT_BOOT_MODE

Table 35: BOOT_INFO Field Bit Descriptions


[7:3] Reserved

2 HS_BOOT_MODE 0 Device does not support high speed timing during boot.

1 Device supports high speed timing during boot.

1 DDR_BOOT_MODE 0 Device does not support dual data rate during boot.

1 Device supports dual data rate during boot.




Table 35: BOOT_INFO Field Bit Descriptions (Continued)


0 ALT_BOOT_MODE 0 Device does not support alternative boot method (obsolete).

1 Device supports alternative boot method. Device must be setto 1, because this is mandatory in v4.4 specification.

BOOT_SIZE_MULT Field (byte 226)The BOOT_SIZE_MULT field in the ECSD register is used to compute the size of theboot partition in the device. The boot partition size is computed as follows:

Boot partition size = 128KB × BOOT_SIZE_MULT

Table 36: BOOT_SIZE_MULT Field Boot Partition Size Values

Value Boot Partition Size

0x00 No boot partition available/boot mode not supported

0x01 1 × 128KB = 128KB

0x02 2 × 128KB = 256KB

···

···

0xFE 254 × 128KB = 32,512KB

0xFF 255 × 128KB = 32,640KB

ACC_SIZE Field (byte 225)The ACC_SIZE field in the ECSD register defines one or more programmable boundaryunits that are programmed at the same time. This value can be used by the host:

• As a guide for format clusters

• To prevent format page misalignment

• As a guide for minimum data transfer sizes, computed as follows:

Super page size = 512 bytes × 2(SUPER_PAGE_SIZE–1) : 0 < SUPER_PAGE_SIZE < 9

Table 37: ACC_SIZE Field Byte Format


Reserved SUPER_PAGE_SIZE

Table 38: ACC_SIZE Field SUPER_PAGE_SIZE Values

Value SUPER_PAGE_SIZE

0x0 Not defined

0x1 512 × 1 = 512 bytes




Table 38: ACC_SIZE Field SUPER_PAGE_SIZE Values (Continued)

Value SUPER_PAGE_SIZE

0x2 512 × 2 = 1KB

···

···

0x8 512 × 128 = 64KB

0x9–0xF Reserved

HC_ERASE_GRP_SIZE Field (byte 224)The HC_ERASE_GRP_SIZE field in the ECSD register defines the erase unit size for eraseoperations in a high-capacity memory device. If the host enables bit 0 in ECSD registerbyte 175, the device uses this value to compute the erase unit size as follows:

Erase unit size = 512KB × HC_ERASE_GRP_SIZE

If the ENABLE bit in ERASE_GROUP_DEF is cleared to 0 or HC_WP_GRP_SIZE is set to0x00, the write protect group size definition is the original case.

Table 39: HC_ERASE_GRP_SIZE Field Erase Unit Size Values

Value Erase Unit Size

0x00 No support for high-capacity erase-unit size

0x01 512KB × 1 = 524,288 bytes

0x02 512KB × 2 = 1,024,576 byte

···

···

0xFF 512KB × 255 = 133,693,440 bytes

ERASE_TIMEOUT_MULT Field (byte 223)The ERASE_TIMEOUT_MULT field in the ECSD register computes erase timeout for high-capacity erase operations; it also defines the timeout value for the erase operation ofone erase group. Erase timeout is computed as follows:

Erase timeout = 300ms × ERASE_TIMEOUT_MULT

If the host executes ERASE operations for multiple erase groups, the total timeout valueshould be a multiple of the number of erase groups issued.

If the host enables bit 0 in ECSD register byte 175, the device uses ERASE_TIME-OUT_MULT values for the timeout value.

If ERASE_TIMEOUT_MULT is set to 0x00, the device must support the previous timeoutdefinition.




Table 40: ERASE_TIMEOUT_MULT Field Erase Timeout Values

Value Erase Timeout Value

0x00 No support for high-capacity erase timeout

0x01 300ms × 1 = 300ms

0x02 300ms × 2 = 600ms

···

···

0xFF 300ms × 255 = 76,500ms

REL_WR_SEC_C Field (byte 222)The REL_WR_SEC_C field in the ECSD register indicates the sector count for the reliablewrite feature. Support of sector count of 1 (512 bytes) is required for the reliable writefeature.

In the case where the EN_REL_WR parameter in the WR_REL_PARAM ECSD register isset to 1, this register has no meaning. If HPI_SUPPORT equals 1 and EN_REL_WRequals 0, then the REL_WR_SEC_C register value must be 1. Otherwise, whenEN_REL_WR is set to 0 and HPI_SUPPORT equals 0, then this register may indicate anadditional supported sector count.

In applications where only a single sector write is supported, the field value should be 1.Otherwise, the value should be a multiple of the number of sectors supported.

HC_WP_GRP_SIZE Field (byte 221)The HC_WP_GRP_SIZE field in the ECSD register defines the write protect group sizefor high-capacity memory. If the ENABLE bit in ERASE_GROUP_DEF is set to HIGH, thewrite protect group size is computed as follows:

Write protect group size = 512KB × HC_ERASE_GRP_SIZE × HC_WP_GRP_SIZE

Table 41: HC_WP_GRP_SIZE Field Write Protect Group Size

Value Value definition

0x00 No support for high-capacity write protect group size

0x01 1 high-capacity erase unit size



···

···

0xFF 255 high-capacity erase unit size

If the ENABLE bit in ERASE_GROUP_DEF is cleared to 0 or HC_WP_GRP_SIZE is set to0x00, the write protect group size definition is the original case.




S_C_VCC Field (byte 220), S_C_VCCQ Field (byte 219)The S_C_VCC and S_C_VCCQ fields in the ECSD register define the maximum VCC cur-rent consumption during the sleep state (slp). The maximum current value is computedas follows:

Sleep current = 1µA × 2x : register value = X > 0Sleep current = no value (legacy) : register value = 0

The maximum register value defined is 0x0D, which equals 8.192mA. Values between0x0E and 0xFF are reserved.

Table 42: S_C_VCC and S_C_VCCQ Field Values

Value VCC Current Consumption During Sleep State

0x00 Not defined

0x01 1μA × 21 = 2μA

0x02 1μA × 22 = 4μA

···

···

0x0D 1μA × 213 = 8.192mA

0x0E~0xFF Reserved

S_A_TIMEOUT Field (byte 217)The S_A_TIMEOUT field in the ECSD register defines the maximum timeout value forstate transitions from the standby state (stby) to the sleep state (slp) and from the sleepstate to the standby state. The maximum timeout value is computed as follows:

Sleep/awake timeout = 100ns × (2S_A_TIMEOUT)

The maximum register value defined is 0x17, which equals 838.86ms. Values between0x18 and 0xFF are reserved.

Table 43: S_A_TIMEOUT Field Values

Value Sleep/Standby Timeout Value

0x00 Not defined

0x01 100ns × 21 = 200ns

0x02 100ns × 22 = 400ns

···

···

0x17 100ns × 223 = 838.86ms

0x18–0xFF Reserved




SEC_COUNT Field (bytes[215:212])The SEC_COUNT field in the ECSD register is used to compute the device density. Thedevice density is computed as follows:

Device density = SEC_COUNT × 512 bytes per sector

The maximum density that can be indicated is 4,294,967,295 x 512 bytes.

The addressable sector range for the device is from sector 0 to sector (SEC_COUNT-1).

The least significant byte (LSB) of the sector count value is byte 212.

When the partition configuration is executed by the host, the device recalculates theSEC_COUNT value, which can indicate the size of the user data area after the partition.

MIN_PERF_DDR_R/W_b_ff Fields (bytes[235:234]), MIN_PERF_R/W_b_ff Fields(bytes[210:205])

The MIN_PERF_DDR_R/W_b_ff and MIN_PERF_R/W_b_ff fields in the ECSD registerdefine the minimum performance value for read and write access with varying buswidth and maximum clock frequency modes. Speed classes are defined based on a150 KB/s base value for single data rate (SDR) operation and 300 KB/s base value fordual data rate (DDR) operation, if DDR is supported. The minimum performance of thedevice can then be marked by defined multiples of the base value (for example, 2.4 MB/s for SDR and 4.8MB/s for DDR). Only the following speed classes are defined. Note thatMMCplus and MMCmobile cards always include an 8-bit data bus. The following cate-gories define the configurations in which the device is operated.

Low-bus category classes (26 MHz clock with 4-bit data bus operation):

• 2.4 MB/s (SDR) or 4.8 MB/s (DDR): Class A

• 3.0 MB/s (SDR) or 6.0 MB/s (DDR): Class B

• 4.5 MB/s (SDR) or 9.0 MB/s (DDR): Class C

• 6.0 MB/s (SDR) or 12.0 MB/s (DDR): Class D

• 9.0 MB/s (SDR) or 18.0 MB/s (DDR): Class E

Mid-bus category classes (26 MHz clock with 8-bit data bus operation, or 52 MHz clockwith 4-bit data bus operation):

• 12.0 MB/s (SDR) or 24.0 MB/s (DDR): Class F

• 15.0 MB/s (SDR) or 30.0 MB/s (DDR): Class G

• 18.0 MB/s (SDR) or 36.0 MB/s (DDR): Class H

• 21.0 MB/s (SDR) or 42.0 MB/s (DDR): Class J

High-bus category classes (52 MHz clock with 8-bit data bus operation):

• 24.0 MB/s (SDR) or 48.0 MB/s (DDR): Class K

• 30.0 MB/s (SDR) or 60.0 MB/s (DDR): Class M

• 36.0 MB/s (SDR) or 72.0 MB/s (DDR): Class O

• 42.0 MB/s (SDR) or 84.0 MB/s (DDR): Class R

• 48.0 MB/s (SDR) or 96.0 MB/s (DDR): Class T

The performance values for both read and write accesses are stored in the ECSD regis-ter for reading. Only the defined values and classes can be used.




Device Performance MeasurementThe MMC specification provides a detailed procedure for measuring device performance.

Prior to the performance test, the memory is filled with random data. The test is per-formed by writing or reading a 64KB chunk of data to or from random logical addresses(aligned to physical block boundaries in the device). A predefined multiple block writeor read is used with a block count of 128 (64KB in 512-byte blocks). The performance iscalculated as the average of several 64KB accesses.

The same performance test is done with all applicable clock frequency and bus widthoptions as follows:

• 52 MHz, 8-bit bus in DDR mode (if the device supports a 52 MHz clock frequency andDDR mode)

• 52 MHz, 8-bit bus (if the device supports a 52 MHz clock frequency)

• 52 MHz, 4-bit bus (if the device supports a 52 MHz clock frequency)

• 26 MHz, 8-bit bus

• 26 MHz, 4-bit bus

If the minimum performance of the device exceeds the physical limit of one of the no-ted options, the device must also meet the performance criteria defined in this field.

The supported field values are defined in the following table. Any values not listed inthis table are not supported.

Table 44: Read/Write (R/W) Access Performance Values

Value Access Performance

Single Data Rate Mode

0x00 For devices that do not fall within the 2.4 MB/s minimum value.

0x08 Class A: Equals 2.4 MB/s and is the next supported value (16 x 150 KB/s).

0x0A Class B: Equals 3.0 MB/s and is the next supported value (20 x 150 KB/s).

0x0F Class C: Equals 4.5 MB/s and is the next supported value (30 x 150 KB/s).

0x14 Class D: Equals 6.0 MB/s and is the next supported value (40 x 150 KB/s).

0x1E Class E: Equals 9.0 MB/s and is the next supported value (60 x 150 KB/s).This is the highest class in the low-bus category operation mode. This is also thehighest class for which any MMCplus or MMCmobile card is necessary to sup-port low-bus category operation mode (26 MHz with 4-bit data bus). AnMMCplus or MMCmobile card supporting any higher class than this must sup-port this class also.

0x28 Class F: Equals 12.0 MB/s and is the next supported value (80 x 150 KB/s).

0x32 Class G: Equals 15.0 MB/s and is the next supported value (100 x 150 KB/s).

0x3C Class H: Equals 18.0 MB/s and is the next supported value (120 x 150 KB/s).

0x46 Class J: Equals 21.0 MB/s and is the next supported value (140 x 150 KB/s).This is also the highest class for which any MMCplus or MMCmobile card is nec-essary to support mid-bus category operation mode (26 MHz with 8-bit databus or 52 MHz with 4-bit data bus). An MMCplus or MMCmobile card support-ing any higher class than this must support this class and class E as well.

0x50 Class K: Equals 24.0 MB/s and is the next supported value (160 x 150 KB/s).




Table 44: Read/Write (R/W) Access Performance Values (Continued)

Value Access Performance

0x64 Class M: Equals 30.0 MB/s and is the next supported value (200 x 150 KB/s).

0x78 Class O: Equals 36.0 MB/s and is the next supported value (240 x 150 KB/s).

0x8C Class R: Equals 42.0 MB/s and is the next supported value (280 x 150 KB/s).

0xA0 Class T: Equals 48.0 MB/s and is the next supported value (320 x 150 KB/s).

Dual Data Rate Mode

0x00 For devices that do not fall within the 4.8 MB/s minimum value.

0x08 Class A: Equals 4.8 MB/s and is the next supported value (16 x 300 KB/s).

0x0A Class B: Equals 6.0 MB/s and is the next supported value (20 x 300 KB/s).

0x0F Class C: Equals 9.0 MB/s and is the next supported value (30 x 300 KB/s).

0x14 Class D: Equals 12.0 MB/s and is the next supported value (40 x 300 KB/s).

0x1E Class E: Equals 18.0 MB/s and is the last defined value (60 x 300 KB/s).

0x28 Class F: Equals 24.0 MB/s and is the next supported value (80 x 300 KB/s).

0x32 Class G: Equals 30.0 MB/s and is the next supported value (100 x 300 KB/s).

0x3C Class H: Equals 36.0 MB/s and is the next supported value (120 x 300 KB/s).

0x46 Class J: Equals 42.0 MB/s and is the last defined value (140 x 300 KB/s).

0x50 Class K: Equals 48.0 MB/s and is the next supported value (160 x 300 KB/s).

0x64 Class M: Equals 60.0 MB/s and is the next supported value (200 x 300 KB/s).

0x78 Class O: Equals 72.0 MB/s and is the next supported value (240 x 300 KB/s).

0x8C Class R: Equals 84.0 MB/s and is the next supported value (280 x 300 KB/s).

0xA0 Class T: Equals 96.0 MB/s and is the last defined value (320 x 300 KB/s).

PWR_CL_DDR_ff_vvv Fields (bytes[239:238]), PWR_CL_ff_vvv Fields (bytes[203:200])The PWR_CL_DDR_ff_vvv and PWR_CL_ff_vvv fields in the ECSD register define e-MMC-supported power classes. By default, the device is required to operate at the maximumfrequency, using a 1-bit bus configuration, and is also required to fall within the defaultmaximum current consumption shown in the following table. If 4-bit or 8-bit bus con-figurations require increased current consumption, it must be stated in this field.

The host can determine the power consumption of the device in different bus modes byreading these fields. Bits[7:4] code the current consumption for the 8-bit bus configura-tion. Bits[3:0] code the current consumption for the 4-bit bus configuration.

The PWR_52_vvv fields are not defined for 26 MHz e·MMC devices.




Table 45: Supported Power Classes

Voltage Value Max RMS Current Max Peak Current Notes

3.6V 0 100mA 200mA Default current consump-tion

1 120mA 220mA

2 150mA 250mA

3 180mA 280mA

4 200mA 300mA

5 220mA 320mA

6 250mA 350mA

7 300mA 400mA

8 350mA 450mA

9 400mA 500mA

10 450mA 550mA

15:11 – – Reserved for future use

Maximum root mean square (RMS) current is calculated as an average of RMS currentconsumption over a 100ms period. Maximum peak current is defined as an absolutemaximum value, not to be exceeded. Power class conditions include:

• Maximum bus frequency

• Maximum operating voltage

• Worst-case functional operation

• Worst-case environmental parameters (such as temperature)

These fields define the maximum power consumption for any protocol operation in da-ta transfer mode, the ready state, and the identification state.

PARTITION_SWITCH_TIME Field (byte 199)This field indicates the maximum timeout for the SWITCH (CMD6) command whenswitching partitions by changing PARTITION_ACCESS bits in the PARTITION_CONFIGfield (ECSD byte 179).

Time is expressed in units of 10 milliseconds.

Table 46: PARTITION_SWITCH Timeout Values

Value PARTITION_SWITCH Timeout Value

0x00 Not defined

0x01 10ms × 1 = 10ms

0x02 10ms × 2 = 20ms

···

···

0xFF 10ms × 255 = 2550ms




OUT_OF_INTERRUPT_TIME Field (byte 198)This field indicates the maximum timeout required to close a command interrupted byHPI (the time between the end bit of CMD12 and CMD13 to the release of DAT0 by thedevice.

Time is expressed in units of 10 milliseconds.

Table 47: OUT_OF_INTERRUPT_TIME Timeout Values

Value OUT_OF_INTERRUPT_TIME Timeout Value

0x00 Not defined

0x01 10ms × 1 = 10ms

0x02 10ms × 2 = 20ms

···

···

0xFF 10ms × 255 = 2550ms

CARD_TYPE Field (byte 196)The CARD_TYPE field in the ECSD register defines the card (device) type. Currently, theonly valid values for this field are 0x01, 0x03, 0x07, 0x0B and 0x0F.

For example, a dual voltage 1.2V/1.8V device that supports 52 MHz DDR mode at 1.8Vand not at 1.2V is coded as 0x7.

Dual data rate mode support is optional.

Table 48: CARD_TYPE Field Definitions

Bit Card (Device) Type

0 High-speed e·MMC at 26 MHz

1 High-speed e·MMC at 52 MHz

2 High-speed DDR e·MMC at 52 MHz, 1.8V or 3V I/O

3 High-speed DDR e·MMC at 52 MHz, 1.2V I/O

7:4 Reserved

CSD_STRUCTURE Field (byte 194)The CSD_STRUCTURE field in the ECSD register is a continuation of the CSD_STRUC-TURE field in the CSD register.

Table 49: CSD_STRUCTURE Field Descriptions

Field Value CSD Structure Version Valid for System Specification Version

0 CSD version 1.0 Version 1.0–1.2

1 CSD version 1.1 Version 1.4–2.2

2 CSD version 1.2 Version 3.1, 3.2, 3.31, 4.0, 4.1, 4.2, 4.3, 4.4,4.41




Table 49: CSD_STRUCTURE Field Descriptions (Continued)

Field Value CSD Structure Version Valid for System Specification Version

[255:3] Reserved for future use

EXT_CSD_REV Field (byte 192)The EXT_CSD_REV field in the ECSD register defines the revision of the ECSD register.

Table 50: EXT_CSD_REV Field Descriptions

Field Value Extended CSD Revision

0 Revision 1.0

1 Revision 1.1

2 Revision 1.2 (for MMC v4.2)


4 Revision 1.4 (obsolete)


[255:6] Reserved




ECSD Register Fields – Modes Segment

CMD_SET Field (byte 191)The CMD_SET field in the ECSD register contains the binary code for the command setthat is active in the device. The command set can be changed using the command setaccess type of the SWITCH (CMD6) command. While changing the command set withCMD6, bit index values according to the S_CMD_SET field should be used. For back-ward compatibility, CMD_SET is set to 0x00 (standard e·MMC setting) following power-on. After switching back to the standard e·MMC command set using CMD6, the value ofCMD_SET is 0x01. Micron's device only supports the standard e·MMC command set,therefore, this cannot be changed.

CMD_SET_REV Field (byte 189)The CMD_SET_REV field in the ECSD register contains a binary number representingthe revision of the active command set. The following table shows the standard com-mand set. Even though the CMD_SET_REV field is in the modes segment of the ECSDregister, it is read-only.

Table 51: CMD_SET_REV Field Values

Bits Value

[0] Version 4.0

[255:1] Reserved

POWER_CLASS Field (byte 187)The POWER_CLASS field in the ECSD register contains the 4-bit value of the selectedpower class for the device. The host is responsible for properly writing this field with themaximum power class. The device uses this information to internally to manage thepower budget and deliver optimized performance.

This field is set to 0 after power-on or a software reset.

Table 52: POWER_CLASS Field Descriptions

Bits Description

[3:0] Card power class code1

[7:4] Reserved

Note: 1. See PWR_CL_DDR_ff_vvv Fields (bytes[239:238]), PWR_CL_ff_vvv Fields (bytes[203:200])(page 52) for supported power classes.

HS_TIMING Field (byte 185)The HS_TIMING field in the ECSD register indicates device-interface timing or high-speed interface timing. This field is automatically set to 0 after power-on or a softwarereset for backward-compatible device-interface timing. If the host writes a 1 to thisfield, the device changes its timing to high-speed interface timing.

4GB, 8GB, 16GB, 32GB: e·MMCECSD Register Fields – Modes Segment



BUS_WIDTH Field (byte 183)The BUS_WIDTH field in the ECSD register indicates the width of the device data bus.BUS_WIDTH is set to 0 (1-bit data bus) after a power-on and can be changed by issuinga SWITCH (CMD6) command.

HS_TIMING must be set to 0x1 before setting BUS_WIDTH for dual data rate operation(values 5 or 6).

Table 53: BUS_WIDTH Field Values

Value Bus Mode

0 1-bit data bus

1 4-bit data bus

2 8-bit data bus

[4:3] Reserved

5 4-bit data bus (DDR)

6 8-bit data bus (DDR)

[255:7] Reserved

ERASED_MEM_CONT Field (byte 181)The ERASED_MEM_CONT field in the ECSD register defines the contents of an explicit-ly erased range.

Table 54: ERASED_MEM_CONT Field Values

Value Bus Mode

0 Erased memory content must be 0

1 Erased memory content must be 1

[255:2] Reserved

PARTITION_CONFIG Field (byte 179)The PARTITION_CONFIG field in the ECSD register defines the configuration for a bootoperation.

Table 55: PARTITION_CONFIG Field Byte Format


Reserved BOOT_ACK BOOT_PARTITION_ENABLE PARTITION_ACCESS

R/W/E R/W/E R/W/E_P




Table 56: PARTITION_CONFIG Field Bit Descriptions


7 Reserved

6 BOOT_ACK (R/W/E) 0x0 No boot acknowledge sent (default)

0x1 Boot acknowledge sent during boot operation

[5:3] BOOT_PARTITION_ENABLE(R/W/E): User selects boot datathat will be sent to the host

0x0 Device not boot enabled (default)

0x1 Boot partition 1 enabled for boot

0x2 Boot partition 2 enabled for boot

0x3–0x6 Reserved

0x7 User area enabled for boot

[2:0] PARTITION_ACCESS(R/W/E_P): User selects parti-tions to access

0x0 User data area (default)

0x1 R/W boot partition 1

0x2 R/W boot partition 2

0x3 R/W replay protected memory block (RPMB)

0x4 Access to general-purpose partition 1




BOOT_CONFIG_PROT Field (byte 178)The BOOT_CONFIG field in the ECSD register defines boot configuration protection.

Table 57: BOOT_CONFIG_PROT Field Byte Format


Reserved PERM_BOOT_CONFIG_PROT Reserved PWR_BOOT_CONFIG_PROT

Reserved R/W Reserved R/W/C_P

Table 58: BOOT_CONFIG_PROT Field Bit Descriptions


[7:5] Reserved

4 PERM_BOOT_CONFIG_PROT(R/W)

0x0 PERM_BOOT_CONFIG_PROT is not enabled (default)

0x1 Permanently disable the change of the boot configurationregister bits relating to boot mode operation (BOOT_PARTI-TION_ENABLE, BOOT_ACK, RESET_BOOT_BUSWIDTH,BOOT_MODE, and BOOT_BUS_WIDTH).

[3:1] Reserved




Table 58: BOOT_CONFIG_PROT Field Bit Descriptions (Continued)


0 PWR_BOOT_CONFIG_PROT(R/W/C_P)

0x0 PWR_BOOT_CONFIG_PROT_ is not enabled (default)

0x1 Disable the change of boot configuration register bits relat-ing to boot mode operation (BOOT_PARTITION_ENABLE,BOOT_ACK, RESET_BOOT_BUSWIDTH, BOOT_MODE, andBOOT_BUS_WIDTH) from this point until next power cycle ornext assertion of the RST_n signal (but not the next issue ofCMD0).

If PERM_BOOT_CONFIG_PROT is enabled, whether or not PWR_BOOT_CON-FIG_PROT is enabled, boot mode is permanently locked and cannot be changed.

BOOT_BUS_WIDTH Field (byte 177)The BOOT_CONFIG field in the ECSD register defines the bus width for a boot operation.

Table 59: BOOT_BUS_WIDTH Field Byte Format


Reserved BOOT_MODE RESET_BOOT_BUS_WIDTH BOOT_BUS_WIDTH

Table 60: BOOT_BUS_WIDTH Field Bit Descriptions


[7:5] Reserved

[4:3] BOOT_MODE (R/W/E) 0x0 Use single data rate + backward compatible timings in bootoperation (default)

0x1 Use single data rate + high speed timings in boot operationmode

0x2 Use dual data rate in boot operation

0x3 Reserved

2 RESET_BOOT_BUS_WIDTH(R/W/E)

0x0 Reset bus width to x1, single data rate and backward compat-ible timings after boot operation (default)

0x1 Retain BOOT_BUS_WIDTH and BOOT_MODE values afterboot operation (relevant to push-pull operation mode only)1

[1:0] BOOT_BUS_WIDTH(R/W/E)

0x0 x1 (SDR) or x4 (DDR) bus width in boot operation mode (de-fault)

0x1 x4 (SDR/DDR) bus width in boot operation mode

0x2 x8 (SDR/DDR) bus width in boot operation mode

0x3 Reserved

Note: 1. The value of BOOT_BUS_WIDTH will not be retained in the data transfer mode if thehost issues CMD0 in any state.




ERASE_GROUP_DEF Field (byte 175)The ERASE_GROUP_DEF field in the ECSD register enables the host to select a high-ca-pacity erase unit size timeout value and write protect group size. Bit 0 is set to 0 bydefault at power-on.

Table 61: ERASE_GROUP_DEF Field Byte Format


Reserved ENABLE

Table 62: ERASE_GROUP_DEF Field Bit Descriptions


[7:1] Reserved

0 ENABLE 0x0 Use conventional erase group size and write protect groupsize definition (default).

0x1 Use high capacity erase unit size, high capacity erase timeout,and high capacity write protect group size definition.

BOOT_WP Field (byte 173)The BOOT_WP field in the ECSD register enables the host to apply permanent or power-on write protection to the boot area. This field also enables the host to disable eitherpower-on write protection or permanent write protection, or both. All the bits are set to0 by default.

Table 63: BOOT_WP Field Byte Format


Reserved B_PWR_WP_DIS

Reserved B_PERM_WP_DIS

Reserved B_PERM_WP_EN

Reserved B_PWR_WP_EN

R/W/C_P R/W R/W R/W/C_P

Table 64: BOOT_WP Field Bit Descriptions


7 Reserved

6 B_PWR_WP_DIS (R/W/C_P) 0x0 The host is permitted to set B_PWR_WP_EN (bit 0).

0x1 Disable the use of B_PWR_WP_EN (bit 0). This bit must be 0 ifPWR_WP_EN is set.

5 Reserved

4 B_PERM_WP_DIS (R/W) 0x0 The host is permitted to set B_PERM_WP_EN (bit 2).

0x1 Permanently disables the use of B_PERM_WP_EN (bit 2). Thisbit must be 0 if B_PERM_WP_EN is set. This bit has no impacton the setting of CSD[13].

3 Reserved




Table 64: BOOT_WP Field Bit Descriptions (Continued)


2 B_PERM_WP_EN (R/W) 0x0 Boot region is not permanently write protected.

0x1 Boot region is permanently write protected. This bit must be0 if B_PERM_WP_DIS is set. This bit only indicates if perma-nent protection has been set specifically for the boot region.This bit may be set to 0 if the whole device is permanentlyprotected using CSD register byte 13.

1 Reserved

0 B_PWR_WP_EN (R/W/C_P) 0x0 Boot region is not power-on write protected.

0x1 Enable power-on period write protection to the boot area.This bit must be 0 if B_PWR_WP_DIS (bit 6) is set.

Notes: 1. An attempt to set both the disable and enable bit for a given protection mode (perma-nent or power-on) in a single SWITCH command has no impact.

2. Setting both B_PERM_WP_EN and B_PWR_WP_EN results in the boot area being perma-nently protected.

USER_WP Field (byte 171)The USER_WP field in the ECSD register enables the host to apply permanent or power-on write protection to each write-protect group in all the general partitions and userarea in the device. This field also enables the host to disable the different protectionmodes that apply to the device.

Table 65: USER_WP Field Byte Format


PERM_PSWD_DIS

CD_PERM_WP_DIS

Reserved US_PERM_WP_DIS

US_PWR_WP_DIS

US_PERM_WP_EN

Reserved US_PWR_WP_EN

R/W R/W R/W R/W/C_P R/W/E_P R/W/E_P

Table 66: USER_WP Field Bit Descriptions


7 PERM_PSWD_DIS (R/W) 0x0 Password-protection features are enabled.

0x1 Password-protection features (ERASE [forcing an ERASE],LOCK, UNLOCK, CLR_PWD, SET_PWD) are permanently disa-bled.

6 CD_PERM_WP_DIS (R/W) 0x1 The host is permitted to set PERM_WP_PROTECT (CSD registerbyte 13).

0x1 Disable the use of PERM_WP_PROTECT (CSD register byte 13).

5 Reserved




Table 66: USER_WP Field Bit Descriptions (Continued)


4 US_PERM_WP_DIS (R/W)2 0x0 Permanent write protection can be applied to write protec-tion groups.

0x1 Permanently disable the use of permanent write protectionfor write protection groups within all the general partitionsand the user area from the point in time this bit is set. Settingthis bit does not impact areas that are already protected.

3 US_PWR_WP_DIS (R/W/C_P) 0x0 Power-on write protection can be applied to write protectiongroups.

0x1 Disable the use of power-on period write protection for writeprotection groups within all the general partitions and theuser area from the point in time this bit is set until power isremoved or the RST_n signal is asserted. Setting this bit doesnot impact areas that are already protected.

2 US_PERM_WP_EN (R/W/E_P)2 0x0 Permanent write protection is not applied when CMD28 is is-sued.

0x1 Apply permanent write protection to the protection group in-dicated by CMD28.1 This bit cannot be set ifUS_PERM_WP_DIS is set.

1 Reserved

0 US_PWR_WP_EN (R/W/E_P) 0x0 Power-on write protection is not applied when CMD28 is is-sued.

0x1 Apply power-on period protection to the protection group in-dicated by CMD28.1 This bit cannot be set if US_PWR_WP_DISis set. This bit has no impact if US_PERM_WP_EN is set. Thisfield is set to 0 after a power-on or assertion of the RST_n signal.

Notes: 1. Issuing CMD28 when both US_PERM_WP_EN and US_PWR_WP_EN are set results in thewrite protect group being permanently protected.

2. When US_PERM_WP_DIS and US_PERM_WP_EN are set, the device sets theSWITCH_ERROR bit in the status register and does not change the write protection setting.

FW_CONFIG Field (byte 169)The UPDATE_DISABLE bit in the FW_CONFIG field of the ECSD register disables updat-ing of the e·MMC firmware.

Table 67: FW_CONFIG Field Byte Format


Reserved Update_Disable

Table 68: FW_CONFIG Field Bit Descriptions


[7:1] Reserved




Table 68: FW_CONFIG Field Bit Descriptions (Continued)


0 Update_Disable 0x0 Firmware updates enabled.

0x1 Firmware updates permanently disabled.

RPMB_SIZE_MULT Field (byte 168)The RPMB_SIZE_MULT field in the ECSD register is used to compute the replay-protectmemory block (RPMB) partition size. The RPMB partition size is computed as follows:

RPMB partition size = 128KB × RPMB_SIZE_MULT

Table 69: RPMB_SIZE_MULT Field Values and Descriptions

Value Description

0x00 No RPMB partition available

0x01 1 x 128KB = 128KB

0x02 2 x 128KB = 256KB

···

···

0xFF 255 x 128KB = 32640KB

WR_REL_SET Field (byte 167)The WR_REL_SET field in the ECSD register indicates the reliability setting for each ofthe user and general area partitions in the device. The contents of this field are read-only if the value of HS_CTRL_REL is 0 in the WR_REL_PARAM field of the ECSD register.The default value of these bits is not specified and is determined by the device.

Table 70: WR_REL_SET Field Bit Types

Bit Field Description Type

7:5 Reserved

4 WR_DATA_REL_4 Write data reliability parti-tion 4

R (if HS_CTRL_REL = 0)R/W (if HS_CTRL_REL = 1







0 WR_DATA_REL_USR Write data reliability (userarea)





Table 71: WR_REL_SET Field Bit Descriptions


[7:5] Reserved

4 WR_DATA_REL_4 0x0 In general purpose partition 4, the WRITE operation has beenoptimized for performance and existing data in the partitioncould be at risk if a power failure occurs.

0x1 In general purpose partition 4, the device protects previouslywritten data if a power failure occurs during a WRITE opera-tion.







0 WR_DATA_REL_USR 0x0 In the main user area, WRITE operations have been been opti-mized for performance and existing data could be at risk if apower failure occurs.

0x1 In the main user area, the device protects previously writtendata if a power failure occurs during a WRITE operation.

WR_REL_PARAM Field (byte 166)The WR_REL_PARAM field in the ECSD register indicates whether the device supportsthe MMC v4.41 data reliability definitions.

Table 72: WR_REL_PARAM Field Bit Types

Bit Field Description Type

7:3 Reserved

2 EN_REL_WR Enhanced Reliability Write R

1 Reserved

0 HS_CTRL_REL Host-controlled data reliability R




Table 73: WR_REL_PARAM Field Bit Descriptions


[7:3] Reserved

2 EN_REL_WR (R) 0x0 The device supports the previous definition of reliable write.

0x1 The device supports the enhanced definition of reliable write.

1 Reserved

0 HS_CTRL_REL (R) 0x0 All the WR_DATA_REL parameters in the WR_REL_SET fieldare read-only bits.

0x1 All the WR_DATA_REL parameters in the WR_REL_SET fieldare R/W bits.

BKOPS_START Field (byte 164)Writing any value to the BKOPS_START field in the ECSD register will manually startbackground operations. The device will stay busy until no more background operationsare required.

BKOPS_EN Field (byte 163)The BKOPS_EN field in the ECSD register enables the host to indicate to the devicewhether it expects the device to manually start background operations periodically bywriting to the BKOPS_START field.

Table 74: BKOPS_EN Field Byte Format


Reserved ENABLE

Table 75: BKOPS_EN Field Bit Descriptions


[7:1] Reserved

0 ENABLE 0x0 The host does not support background operations and is notexpected to write to the BKOPS_START field.

0x1 The host is indicating that it will periodically write to theBKOPS_START field to manually start background operations.

RST_n_FUNCTION Field (byte 162)The RST_n_FUNCTION field in the ECSD register enables the host to permanently ena-ble or disable the RST_n signal before it accesses the device. For backward compatibili-ty reasons, the RST_n signal is temporarily disabled in the device by default.

Table 76: RST_n_FUNCTION Field Byte Format


Reserved RST_ENABLE




Table 77: RST_n_FUNCTION Field Bit Descriptions


[7:2] Reserved

[1:0] RST_n_ENABLE (readable andwriteable once)

0x0 RST_n signal is temporarily disabled (default).

0x1 RST_n signal is permanently enabled.

0x2 RST_n signal is permanently disabled.

0x3 Reserved.

By default, RST_n_ENABLE is set to 0x0, which means RST_n is temporarily disabled.The host can change the value to either 0x1 (permanently enabled) or 0x2 (permanentlydisabled). Once the host sets the value, it cannot be changed again.

After the host sets RST_n_ENABLE to 0x2 (permanently disabled), the device will neveraccept the RST_n signal input. During the disable period, the device must ensure thatno RST_n state (HIGH, LOW, or floating) will cause the device to malfunction (that is,high leakage current in the input buffer).

When RST_n_ENABLE is set to 0x1 (permanently enabled), the device accepts theRST_n input permanently. The host cannot change the bits back to the disabled values.Also, when the device is permanently enabled, it must not start resetting internal cir-cuits by triggering off of the field bit change. The internal reset sequence must betriggered by the rising edge of RST_n, and not by the field change.

Since the device does not have any internal pull-up or pull-down resistor on the RST_nterminal, the host must pull RST_n up or down to prevent unnecessary leakage currentin the input circuits when RST_n is enabled.

HPI_MGMT Field (byte 161)The HPI_MGMT field in the ECSD register enables the host to activate the HPI mechanism.

Table 78: HPI_MGMT Field Byte Format


Reserved HPI_EN

Table 79: HPI_MGMT Field Bit Descriptions


[7:1] Reserved

0 HPI_EN 0x0 HPI mechanism is not activated by the host (default).

0x1 HPI mechanism is activated by the host.

PARTITIONING_SUPPORT Field (byte 160)The PARTITIONING_SUPPORT field in the ECSD register defines supported partitionfeatures.




Table 80: PARTITIONING_SUPPORT Field Byte Format


Reserved ENH_ATTRIBUTE_EN PARTITIONING_EN

Table 81: PARTITIONING_SUPPORT Field Bit Descriptions


[7:2] Reserved

1 ENH_ATTRIBUTE_EN 0x0 Device cannot have enhanced technological features in parti-tions and user data area.

0x1 Device can have enhanced technological features in partitionsand user data area.

0 PARTITIONING_EN 0x0 Device does not support partitioning features.

0x1 Device supports partitioning features.

MAX_ENH_SIZE_MULT Field (bytes[159:157])The MAX_ENH_SIZE_MULT field in the ECSD register defines the maximum size ofmemory area that can have the enhanced attribute. Write protect group size refers tothe high-capacity definition. The maximum enhanced memory area is computed as fol-lows:

∑ 4

i = 1

Maximum enhanced area = MAX_ENH_SIZE_MULT × HC_WP_GRP_SIZE × HC_ERASE_GRP_SIZE × 512KB

Enhanced general purpose partition size (i) + Enhanced user data area ≤ Enhanced area (MAX)

Table 82: MAX_ENH_SIZE_MULT Field Byte Format


MAX_ENH_SIZE_MULT_2

MAX_ENH_SIZE_MULT_1

MAX_ENH_SIZE_MULT_0

PARTITIONS_ATTRIBUTE Field (byte 156)The PARTITIONS_ATTRIBUTE field in the ECSD register sets enhanced attributes in gen-eral-purpose partitions.

Table 83: PARTITIONS_ATTRIBUTE Field Byte Format


Reserved ENH_4 ENH_3 ENH_2 ENH_1 ENH_USR




Table 84: PARTITIONS_ATTRIBUTE Field Bit Descriptions


[7:5] Reserved

[4] ENH_4 0x0 Default

0x1 Set enhanced attribute in General-Purpose Partition 4.







[0] ENH_USR 0x0 Default

0x1 Set enhanced attribute in user data area.

PARTITION_SETTING_COMPLETED Field (byte 155)The PARTITION_SETTING_COMPLETED field in the ECSD register indicates whetherthe host has performed any partition configuration of the device. By default, this bit isset to 0, which indicates the host has not performed any partition configuration . Thisbit is set to notify the device that setting the parameter definitions has been completedand the device can start its internal configuration activity. If a sudden power loss oc-curs, and this bit has not been set, the configuration of partitions is not executed andmust be repeated.

Table 85: PARTITION_SETTING_COMPLETED Field Byte Format


Reserved PARTITION_SETTING_COMPLETED

GP_SIZE_MULT Field (bytes[154:143])The GP_SIZE_MULT field in the ECSD register defines the size of the general-purposepartition in terms of high-capacity write protect groups.

Table 86: GP_SIZE_MULT Field Byte Format


GP_SIZE_MULT_X_2

GP_SIZE_MULT_X_1

GP_SIZE_MULT_X_0

The format for the GP_SIZE_MULT field equation is GP_SIZE_MULT_X_Y, where X re-fers to general-purpose partitions 1 through 4 and Y refers to factors 0 through 2. Thesize of the general-purpose partition is computed as follows:




General-purpose partition x size = (GP_SIZE_MULT_X_2 × 216

+ GP_SIZE_MULT_X_1 × 28 + GP_SIZE_MULT_X_0 × 20)× HC_WP_GRP_SIZE × HC_ERASE_GRP_SIZE × 512KB

Table 87: GP_SIZE_MULT Field Byte Descriptions

General-Purpose Partition Number GP_SIZE_MULT_X_Y ECSD Byte Number

GPP1 GP_SIZE_MULT_1_0 143

GP_SIZE_MULT_1_1 144











ENH_SIZE_MULT Field (bytes[142:140])The ENH_SIZE_MULT field in the ECSD register defines the size of the enhanced userdata area in terms of high-capacity write protect groups. The enhanced user data areasize is computed as follows:

Enhanced user data area x size = (ENH_SIZE_MULT_2 × 216 + ENH_SIZE_MULT_1 × 28

+ ENH_SIZE_MULT_0 × 20) × HC_WP_GRP_SIZE× HC_ERASE_GRP_SIZE × 512KB

Table 88: ENH_SIZE_MULT Field Byte Format


ENH_SIZE_MULT_2

ENH_SIZE_MULT_1

ENH_SIZE_MULT_0

ENH_START_ADDR Field (bytes[139:136])The ENH_START_ADDR field in the ECSD register defines the starting address of theenhanced user data area segment in the user data area, expressed in bytes or, in thecase of high-capacity devices, in sectors.




Table 89: ENH_START_ADDR Field Byte Format


ENH_START_ADDR_3

ENH_START_ADDR_2

ENH_START_ADDR_1

ENH_START_ADDR_0

SEC_BAD_BLK_MGMNT Field (byte 134)Bit 0 of the SEC_BAD_BLK_MGMNT field in the ECSD register, when set, enables thedevice to perform a SECURE PURGE of the bits that are not defective in the physicalblock, before the block is retired. In some memory array technologies used for multime-dia cards, portions of the memory array can become defective with use. The devicerecovers the information from the defective portions before it retires the block wherethose defective portions are located.

Table 90: SEC_BAD_BLK_MGMNT Field Byte Format


Reserved SEC_BAD_BLOCK

Table 91: SEC_BAD_BLK_MGMNT Field Bit Descriptions


[7:1] Reserved

0 SEC_BAD_BLK (R/W) 0x0 Feature disabled (default).

0x1 All data must be securely purged from defective memory ar-ray regions before they are retired from use. ECSD registerbyte 231, bit 2 (SEC_BD_BLK_EN) must be set in order to usethis bit.




RCA RegisterThe writable 16-bit relative card address (RCA) register contains the device address as-signed by the host during device identification. After the device identification proce-dure, this device address is used for the addressed host-to-device communication. Thedefault value for the RCA is 0x0001. The value 0x0000 is reserved to set all devices to thestandby state with the SELECT/DESELECT_CARD (CMD7) command.

DS RegisterThe 16-bit drive stage (DS) register is optional and can be used to improve bus perform-ance for extended operating conditions. The improvement in bus performance is de-pendent on parameters such as bus length, transfer rate, and number of devices. TheCSD carries information about DS register usage. The default value of the DS register is0x404.

4GB, 8GB, 16GB, 32GB: e·MMCRCA Register



Bus Protocol – Message TypesFollowing a power-on reset, the host must initialize the device using e·MMC bus proto-col. Each message on the bus is represented by one of the following message types:

• Command token

• Response token

• Data packet

• CRC status

Figure 9: Typical Bus Protocol

Command ResponseCMD

DAT[7:0]

From hostto device

From deviceto host

Data block CRC statusCRC

Data between hostand device

For write operationfrom device to host

( )

4GB, 8GB, 16GB, 32GB: e·MMCBus Protocol – Message Types



Bus Protocol – Command TokenA command token sent from the host to a device starts an operation. The command istransferred serially on the CMD line; one command bit is transferred per clock cycle.

All commands have a fixed 48-bit code length and require a 0.92µs transmission time at52 MHz.

A command always starts with a start bit, which is always 0. The start bit is followed bythe bit indicating the direction of transmission from the host (bit value = 1). The next 6bits indicate the command index, with this value being interpreted as a binary codednumber between 0 and 63. Some commands need an argument that consists of 32 bits.A value of x in the table below indicates that this variable is dependent on the com-mand. All commands are protected by a CRC so that transmission errors can be detec-ted, and the operation can be repeated. Every command is terminated by the end bit,which is always 1.

Figure 10: Command Token Format

0MSB 1 Content CRC 1 LSB

Command content: command and address informationor parameter, protected by 7-bit CRC checksum

Total length = 48 bits

Command ResponseCMD

DAT[7:0]

From deviceto host

End bit:always 1

Transmitter bit:1 = host command

Start bit:always 0




From hostto device

( )

Table 92: Command Token Format

Bit Position 47 46 [45:40] [39:8] [7:1] 0

Width (bits) 1 1 6 32 7 1

Value description Start bit = 0 Transmission bit = 1for host transmission

on the bus

Command index = x Argument = x CRC7 = x End bit = 1

4GB, 8GB, 16GB, 32GB: e·MMCBus Protocol – Command Token



Command TypesThe host controls all communication between the host and the device. The host sendstwo command types: broadcast commands and addressed (point-to-point) commands.Broadcast commands are intended for all devices in the e·MMC system. Addressed com-mands are sent to the addressed device and result in a response from the device. Someof the commands shown in both command types require a response.

All commands and responses are sent over the CMD line of the e·MMC bus. The com-mand transmission always starts with the leftmost bit of the bitstring corresponding tothe command code word.

Table 93: Command Types

CommandNotation Description

bc Broadcast commands with no response

bcr Broadcast commands with response

ac Addressed (point-to-point) commands with no data transfer on DAT lines

adtc Addressed (point-to-point) data transfer commands with data transfer on DATlines

Command ClassesThe device command set is divided into six classes:

• Basic commands (class 0)

• Block-oriented read commands (class 2)

• Block-oriented write commands (class 4)

• Erase commands (class 5)

• Block-oriented write protection commands (class 6)

• Lock card (class 7)

Each class supports a subset of device functions. The supported card command classes(CCC) are coded as a parameter in the card-specific data (CSD) register of each device,providing the host with information on how to access the device.

Command DescriptionsMicron e·MMC bus commands and their arguments are defined in the following tables.All future reserved commands will have a code-word length of 48 bits. Stuff bits shouldbe filled with 0s to ensure fixed-length frames for commands and responses.




Table 94: Basic Commands (class 0)

CommandIndex Type Argument Response Abbreviation Command Description

CMD0 bc [31:0] 00000000 None GO_IDLE_STATE Resets the device to idle state.

bc [31:0] F0F0F0F0 None GO_PRE_IDLE_STATE Resets the device to pre-idle state.

– [31:0] FFFFFFFA1 None BOOT_INITIATION Initiates the alternative BOOT operation.

CMD1 bcr [31:0] OC registerwithout busy

R3 SEND_OP_COND In the idle state, requests the device to sendits OC register contents in the response onthe CMD line.

CMD2 bcr [31:0] Stuff bits2 R2 ALL_SEND_CID Requests the device to send its CID numberon the CMD line.

CMD3 ac [31:16] RCA R1 SET_RELATIVE_ADDR Assigns the RCA to the device.

CMD4 bc [31:16] DSR[15:0] Stuff bits2

None SET_DSR Programs the device DS register. Refer to CSDregister bit 76 to determine if the device sup-ports this command.

CMD5 ac [31:16] RCA[15] Sleep/awake[14:0] Stuff bits2

R1b SLEEP_AWAKE Toggles the device between the standby andsleep states; set bit 15 to 1 for the device toenter the sleep state; set bit 15 to 0 for thedevice to exit the sleep state.

CMD6 ac [31:26] Set to 0[25:24] Access[23:16] Index[15:8] Value[7:3] Set to 0[2:0] CMD set

R1b SWITCH Switches the operating mode of the selecteddevice or modifies the ECSD registers.

CMD7 ac [31:16] RCA[15:0] Stuff bits2

R1/R1b3 SELECT/ DESE-LECT_CARD

Toggles the device between the standby andtransfer states or between the programmingand disconnect states. In both cases, the de-vice is selected by its own relative address andis deselected by any other address.

CMD8 adtc [31:0] Stuff bits2 R1 SEND_EXT_CSD The device sends its ECSD register as a blockof data.


R2 SEND_CSD The addressed device sends card-specific data(CSD) on the CMD line.


R2 SEND_CID The addressed device sends card identification-specific data (CID) on the CMD line.

CMD12 ac [31:16] RCA4

[15:1] Stuff bits2

[0] HPI

R1/R1b5 STOP_TRANSMISSION Forces the device to stop transmission.If the HPI flag is set, the device will interruptits internal operations according to the set-ting in byte 198 of the ECSD register.


[0] HPI

R1 SEND_STATUS The addressed device sends its status register.If the HPI flag is set, the device will interruptits internal operations according to the set-ting in byte 198 of the ECSD register.




Table 94: Basic Commands (class 0) (Continued)


CMD14 adtc [31:0] Stuff bits2 R1 BUSTEST_R The host reads the reversed bus test data pat-tern from a device.


None GO_INACTIVE_STATE Sets the device to the inactive state.

CMD19 adtc [31:0] Stuff bits2 R1 BUSTEST_W The host sends the bus test data pattern tothe device.

Notes: 1. If the device receives CMD0 with an argument of 0xFFFFFFFA immediately following pow-er-on, the device recognizes that the command is for initiating the alternative BOOToperation and begins preparing boot data to be sent to the host.

2. Stuff bits should be filled with 0s.3. R1 when a device is changed from standby status to transfer state; R1b when a device is

changed from the disconnected state to the programming state.4. RCA in CMD12 is used only if the HPI bit is set. The argument does not imply any RCA

check on the device side.5. R1 for read cases and R1b for write cases.

Table 95: Block-Oriented Read Commands (class 2)


CMD16 ac [31:0] Blocklength

R1 SET_BLOCKLEN Sets the block length (in bytes) for all fol-lowing block commands (READ andWRITE). Default block length is specified inthe CSD.

CMD17 adtc [31:0] Data ad-dress1

R1 READ_SINGLE_BLOCK Reads a block of the size selected by theSET_BLOCKLEN command.2


R1 READ_MULTIPLE_BLOCK Continuously transfers data blocks from de-vice to host until interrupted by a STOPcommand or until the requested numberof data blocks is transmitted.

CMD23 ac [31] Reliablewrite request[30:16] Set to 0[15:0] Number ofblocks

R1 SET_BLOCK_COUNT Defines the number of blocks to be trans-ferred in the immediately succeeding a mul-tiple-block read or write command. If theargument is all 0s, the subsequent READ orWRITE operation is open-ended.

Notes: 1. The data address for media ≤2GB is a 32-bit byte address; the data address for media>2GB is a 32-bit sector address (of 512 bytes).

2. Transferred data must not cross a physical block boundary unless READ_BLK_MISALIGNis set in the CSD register.




Table 96: Block-Oriented Write Commands (class 4)


CMD16 ac [31:0] Blocklength

R1 SET_BLOCKLEN Sets the block length (in bytes) for all fol-lowing block commands (READ andWRITE). Default block length is specifiedin the CSD.

CMD23 ac [31] Reliablewrite request[30:16] Set to 0[15:0] Number ofblocks

R1 SET_BLOCK_COUNT Defines the number of blocks to be trans-ferred in the immediately succeeding mul-tiple-block read or write command. If theargument is all 0s, the subsequent READor WRITE operation is open-ended.


R1 WRITE_BLOCK Writes a block of the size selected by theSET_BLOCKLEN command.3


R1 WRITE_MULTIPLE_BLOCK Continuously writes blocks of data until aSTOP_TRANSMISSION is issued or until therequested number of blocks is received.

CMD26 adtc [31:0] Stuff bits2 R1 PROGRAM_CID Programs the CID register. This commandis issued only once. The device containshardware to prevent this operation afterthe first programming. Normally this com-mand is reserved for use by the manufac-turer.

CMD27 adtc [31:0] Stuff bits2 R1 PROGRAM_CSD Programs the programmable bits of theCSD register.


2. Stuff bits should be filled with 0s.3. Transferred data must not cross a physical block boundary unless WRITE_BLK_MISALIGN

is set in the CSD register.




Table 97: Erase Commands (class 5)


CMD32,CMD34

Reserved1

CMD35 ac [31:0] Data ad-dress2

R1 ERASE_GROUP_START Sets the address of the first erase group with-in a range to be selected for the ERASE.


R1 ERASE_GROUP_END Sets the address of the last erase group with-in a continuous range to be selected for theERASE.

CMD37 Reserved2

CMD38 ac [31] Secure re-quest[30:16] Set to 0[15] Force gar-bage collect re-quest4

[14:1] Set to 0[0] Identify writeblock for erase4

R1b ERASE Erases all previously selected write blocks ac-cording to the argument bits.5

Notes: 1. To maintain backward compatibility with older versions of e·MMC, these command in-dexes are reserved and cannot be used.

2. The data address for media ≤2GB is a 32-bit byte address; data address for media >2GBis a 32-bit sector address (of 512 bytes).

3. Argument bit 31 is an optional feature that is only supported if ECSD register byte 231,bit 0 (SEC_ER_EN) is set.

4. Argument bits 15 and 0 are optional features that are only supported if ECSD registerbyte 231, bit 4 (SEC_GB_CL_EN) is set.

5. Supported argument combinations are listed under “Operating Modes – Data TransferMode: ERASE Operation”




Table 98: Block-Oriented Write Protection Commands (class 6)



R1b SET_WRITE_PROT If the device has write protection fea-tures, this command sets the write protec-tion bit of the addressed group. Theproperties of write protection are codedin the device-specific data (WP_GRP_SIZEor HC_WP_GRP_SIZE).


R1b CLR_WRITE_PROT If the device provides write protection fea-tures, this command clears the write pro-tection bit of the addressed group.

CMD30 adtc [31:0] Write-pro-tected data ad-dress

R1 SEND_WRITE_PROT If the device provides write protection fea-tures, this command asks the device tosend the status of the write protection bits.2

CMD31 adtc [31:0] Write-pro-tected data ad-dress

R1 SEND_WRITE_PROT_TYPE This command sends the type of write pro-tection that is set for the different writeprotection groups.3


2. Starting at the specified address, 32 write protection bits, representing 32 write protectgroups, followed by 16 CRC bits are transferred in a payload format via the data lines.The last (least significant) bit of the protection bits corresponds to the first addressedgroup. If the addresses of the last groups are outside the valid range, the correspondingwrite protection bits are set to 0.

3. 64 write protection bits (representing 32 write-protect groups starting at the specifiedaddress), followed by 16 CRC bits, are transferred in a payload format via the data lines.Each set of two protection bits shows the type of protection set for each of the writeprotection groups. The definition of the different bit settings are shown below. The last(least significant) two bits of the protection bits correspond to the first addressed group.If the addresses of the last groups are outside the valid range, then the correspondingwrite protection bits are set to zero.00 - Write protection group not protected01 - Write protection group is protected by temporary write protection10 - Write protection group is protected by power-on write protection11 - Write protection group is protected by permanent write protection




Table 99: Lock Card (class 7)


CMD42 adtc [31:0] Stuff bits1 R1b LOCK_UNLOCK Used to set and reset the password or to lockand unlock the device. The size of the datablock is set by the SET_BLOCK_LEN command.

CMD43…CMD54

Reserved2

Notes: 1. Stuff bits should be filled with 0s.2. To maintain backward compatibility with older versions of e·MMC, these command in-

dexes are reserved and cannot be used.

Table 100: Device State Transitions by Command

Current state...

idle ready ident stby tran data btst rcv prg dis ina slp irq

Command Transitions to...

Class-independent

CRC error – – – – – – – – – – – – stby

Comand not suppor-ted

– – – – – – – – – – – – stby

Class 0

CMD0(arg = 0x00000000)

idle idle idle idle idle idle idle idle idle idle – idle stby

CMD0(arg = 0xF0F0F0F0)

Pre-idle

Pre-idle

Pre-idle

Pre-idle

Pre-idle

Pre-idle

Pre-idle

Pre-idle

Pre-idle

Pre-idle

– Pre-idle

stby

CMD1, device VDD

range compatibleready – – – – – – – – – – – stby

CMD1, device is busy idle – – – – – – – – – – – stby

CMD1, device VDD

range not compatibleina – – – – – – – – – – – stby

CMD2, device winsbus

– ident – – – – – – – – – – stby

CMD2, device losesbus

– ready – – – – – – – – – – stby

CMD3 – – stby – – – – – – – – – stby

CMD4 – – – stby – – – – – – – – stby

CMD5 – – – slp – – – – – – – stby stby

CMD6 – – – – prg – – – – – – – stby

CMD7, device is ad-dressed

– – – tran – – – – – prg – – stby

CMD7, device is notaddressed

– – – – stby stby – – dis – – – stby




Table 100: Device State Transitions by Command (Continued)

Current state...



CMD8 – – – – data – – – – – – – stby

CMD9 – – – stby – – – – – – – – stby

CMD10 – – – stby – – – – – – – – stby

CMD12, arg[0] = 0 – – – – – tran – prg – – – – stby

CMD12, arg[0] = 1 – – – – – – – – prg – – – stby

CMD13, arg[0] = 0 or1

– – – stby tran data btst rcv prg dis – – stby

CMD14 – – – – – – tran – – – – – stby

CMD15 – – – ina ina ina ina ina ina ina – – stby

CMD19 – – – – btst – – – – – – – stby

Class 1

CMD11 – – – – data – – – – – – – stby

Class 2

CMD16 – – – – tran – – – – – – – stby

CMD17 – – – – data – – – – – – – stby

CMD18 – – – – data – – – – – – – stby

CMD23 – – – – tran – – – – – – – stby

Class 3

CMD20 – – – – rcv – – – – – – – stby

Class 4

CMD16 See class 2

CMD23 See class 2

CMD24 – – – – rcv – – – rcv1 – – – stby

CMD25 – – – – rcv – – – rcv1 – – – stby

CMD26 – – – – rcv – – – – – – – stby

CMD27 – – – – rcv – – – – – – – stby

Class 6

CMD28 – – – – prg – – – – – – – stby

CMD29 – – – – prg – – – – – – – stby

CMD30 – – – – data – – – – – – – stby

CMD31 – – – – data – – – – – – – stby

Class 5

CMD35 – – – – tran – – – – – – – stby

CMD36 – – – – tran – – – – – – – stby

CMD38 – – – – prg – – – – – – – stby

Class 7




Table 100: Device State Transitions by Command (Continued)

Current state...



CMD16 See class 2

CMD42 – – – – rcv – – – – – – – stby

Class 8

CMD55 – – – stby tran data btst rcv prg dis – – irq

CMD56, RD/WR = 0 – – – – rcv – – – – – – – stby

CMD56, RD/WR = 1 – – – – data – – – – – – – stby

Class 9

CMD39 – – – stby – – – – – – – – stby

CMD40 – – – irq – – – – – – – – stby

Class 10–11

CMD41,CMD43...CMD54,CMD57...CMD59

Reserved

CMD60...CMD63 Reserved for manufacturer

Notes: 1. Due to legacy considerations, a device may treat CMD24/25 during a prg state, whilebusy is active, as either a legal or an illegal command. A device that treats CMD24/25during a prg state, while busy is active, as an illegal command will not change its stateto the rcv state. A host should not send CMD24/25 while the device is in a prg state andbusy is active.

2. As there is no way to obtain state information in boot mode, boot mode states are notshow in this table.




Bus Protocol – Response TokenA response token is sent from the device to the host as an answer to a previously re-ceived command. The response transmission always starts with the leftmost bit of thebitstring corresponding to the response code word. The code length depends on theresponse type. A response always starts with a start bit (always 0), followed by the bitindicating the direction of transmission from the device (bit value = 0); one response bitis transferred per clock cycle.

A value denoted by x in the following tables indicates a variable entry. All responses ex-cept for the R3 type are protected by a CRC. Every command code word is terminatedby the end bit (always 1).

There are three main types of response tokens: R1, R2, and R3. Each type of responsetoken has a particular coding scheme, depending on its content. The token length iseither 48 bits or 136 bits.

Figure 11: Response Token Format

0 0 ContentR1

R2

CRC 1

Start bit:always 0

End bit:always 1

Transmitter bit:0 = card response Response content: mirrored command

and status information (R1 response)or OCR register (R3 response),

protected by 7-bit CRC checksum

End bit:always 1


0 0 Content = CID or CSD CRC 1


0 0 ContentR3 1


Command ResponseCMD

DAT[7:0]

From hostto device




From deviceto host

( )

4GB, 8GB, 16GB, 32GB: e·MMCBus Protocol – Response Token



R1 Response TokenThe R1 response (normal response) token has a code length of 48 bits. Bits[45:40] indi-cate the index of the command to which the device will respond. This value is interpre-ted as a binary coded number between 0 and 63. The status of the device is coded in 32bits.

The R1 response format contains a 32-bit field called card status. This field is used totransmit device status information.

Three attributes are associated with the card status bits: bit type, detection mode, andclear condition.

Bit Type

• Error bits signal an error condition detected by the device. These bits are cleared assoon as the response reporting the error is sent.

• Status bits serve as information fields only and do not alter the execution of the com-mand being responded to. These bits are set and cleared in accordance with thedevice status.

Detection Mode

The detection mode attribute defines the detection mode for each bit in the card statusfield. Exceptions are detected by the device either during the command interpretationand validation phase (response mode) or during the command execution phase (execu-tion mode). Response mode exceptions are reported in the response to the commandthat raised the exception. Execution mode exceptions are reported in the response to aSTOP_TRANSMISSION command used to terminate the operation or in the response toa SEND_STATUS command issued after the operation is complete.

When an error bit is detected in response mode, the device reports the error in the re-sponse to the command that raised the exception. The command is not executed andthe associated state transition does not take place. When an error is detected in execu-tion mode, the execution is terminated. The error is reported in the response to the nextcommand.

The ADDRESS_OUT_OF_RANGE and ADDRESS_MISALIGN exceptions may be detec-ted both in response and execution modes.

Clear Condition

The clear condition attribute includes two valid conditions: A and B. Clear condition Ameans that the card status field bit is cleared when the device changes status. Clear con-dition B means the card status field bit is cleared as soon as the response reporting theerror is sent.




R1b Response TokenThe R1b response token is identical to R1 with an optional busy signal transmitted onthe data line, DAT0. The device may become busy after receiving commands based onits state before the commands were issued. For timing and detailed descriptions, seeCommand/Response Timing.

Table 101: R1/R1b Response Token Format

Bit Position 47 46 [45:40] [39:8] [7:1] 0

Value 0 0 x x x 1

Description Start bit Transmission bit Command index Card status CRC7 End bit

Table 102: R1/R1b Card Status Field

Bits IdentifierBit

Type1Det

Mode2 Value DescriptionClearCond3

31 ADDRESS_OUT_OF_RANGE

E R 0 = no error1 = error

The command’s address argument wasout of the supported range for this device.

B

X A multiple-block READ or WRITE opera-tion (although started in a valid address)is attempting to read or write beyond thedevice capacity.

30 ADDRESS_MISALIGN E R 0 = no error1 = error

The command’s address argument (in ac-cordance with the currently set blocklength) misaligns the first data block withthe physical blocks of the device.

B

X A multiple-block READ or WRITE opera-tion (although started with a valid address/block-length combination) is attemptingto read or write a data block that doesnot align with the physical blocks of thedevice.

29 BLOCK_LEN_ERROR E R 0 = no error1 = error

Either the argument of a SET_BLOCKLENcommand exceeds the maximum valuesupported for the device, or the previous-ly defined block length is illegal for thecurrent command (for example, the hostissues a write command; the currentblock length is smaller than the device’smaximum block length, and partial blockwrites are not supported).

B

28 ERASE_SEQ_ERROR E R 0 = no error1 = error

An error in the ERASE command se-quence occurred.

B

27 ERASE_PARAM E X 0 = no error1 = error

An invalid selection of erase groups forERASE occurred.

B

26 WP_VIOLATION E X 0 = no error1 = error

An attempt to program a write-protectedblock.

B




Table 102: R1/R1b Card Status Field (Continued)

Bits IdentifierBit

Type1Det


25 CARD_IS_LOCKED S R 0 = device unlocked1 = device locked

When set, this signals that the device islocked by the host.

A

24 LOCK_UN-LOCK_FAILED

E X 0 = no error1 = error

Set when a sequence or password errorhas been detected in the LOCK_UNLOCKdevice command.

B

23 COM_CRC_ERROR E R 0 = no error1 = error

The CRC check of the previous commandfailed.

B

22 ILLEGAL_COMMAND E R 0 = no error1 = error

The command is not legal for the devicestate.

B

21 CARD_ECC_FAILED E X 0 = success1 = failure

The device's internal ECC was applied,but failed to correct the data.

B

20 CC_ERROR E R 0 = no error1 = error

A device error occurred that is not rela-ted to the host command.(Undefined by the MMC specification.)

B

19 ERROR E X 0 = no error1 = error

A generic device error occurred that wasrelated to (and detected during) execu-tion of the last host command (for exam-ple, a read or write failure).(Undefined by the MMC specification.)

B

18 Reserved

17 Reserved

16 CID/CSD_OVERWRITE E X 0 = no error1 = error

Can be one of the following errors:– The CID register has already been writ-ten and cannot be overwritten.– The read-only section of the CSD regis-ter does not match the device content.– An attempt was made to set the copybit as original or to unprotect permanent-ly write-protected bits.

B

15 WP_ERASE_SKIP E X 0 = not protected1 = protected

Only partial address space was eraseddue to existing write-protected blocks.

B

14 Reserved; must be set to 0.

13 ERASE_RESET E R 0 = cleared1 = set

An erase sequence was cleared before ex-ecuting because an out-of-erase- se-quence command was received (com-mands other than CMD13, CMD35,CMD36, or CMD38).

B




Table 102: R1/R1b Card Status Field (Continued)

Bits IdentifierBit

Type1Det


12:9 CURRENT_STATE S R 0 = idle1 = ready2 = ident3 = stby4 = tran5 = data6 = rcv7 = prg8 = dis9 = btst10 = slp 11–15 = re-served

Indicates the state of the device when itreceives a command. If the command exe-cution causes a state change, it will bevisible to the host in the response to thenext command.The four bits are interpreted as a binarynumber between 0 and 15.

A

8 READY_FOR_DATA S R 0 = not ready1 = ready

Corresponds to buffer empty signaling onthe bus.

A

7 SWITCH_ERROR E X 0 = no error1 = switch error

If set, the device did not switch to the ex-pected mode as requested by the SWITCHcommand.

B

6 URGENT_BKOPS S R 0 = not urgent1 = urgent

If set, the device must perform back-ground operations urgently.The host can check the ECSD fieldBKOPS_STATUS for the detailed level.

5 APP_CMD S R 0 = disabled1 = enabled

The device expects an application-specificcommand, or an indication that the com-mand has been interpreted as an applica-tion-specific command.4

A

4 Reserved

[3:2] Reserved

[1:0] Reserved for manufacturer test mode

Notes: 1. E = Error bit; S = Status bit2. R = Response mode detection; X = Execution-mode detection3. A = Bit cleared when the device changes status

B = Bit cleared as soon as the response reporting the error is sent4. APP_CMD is not supported by the e·MMC device.




R2 Response TokenThe R2 response token has a 136-bit code length. This is used to send the contents ofthe CID register as a response to commands CMD2 and CMD10, and the contents of theCSD register as a response to CMD9. Only bits[127:1] of the CID and CSD are transfer-red. The reserved bit 0 of these registers is replaced by the end bit of the response.

Table 103: R2 Response Token Format

Bit Position 135 134 [133:128] [127:1] 0

Width (bits) 1 1 6 127 1

Value 0 0 111111 x 1

Description Start bit Transmission bit Check bits CID or CSD register including internal CRC7 End bit

R3 Response TokenThe R3 response token code length is 48 bits. This token is used to send the contents ofthe OC register as a response to CMD1. The level coding is:

• Restricted voltage windows = LOW

• Device busy = LOW

Table 104: R3 Response Token Format

Bit Position 47 46 [45:40] [39:8] [7:1] 0

Width (bits) 1 1 6 32 1 1

Value 0 0 111111 x 1111111 1

Description Start bit Transmission bit Check bits OC register Check bits End bit




Bus Protocol – Data PacketData packets can be transferred from the device to the host or vice-versa. Data is trans-ferred via the data lines. The number of data lines used for the data transfer can be 1(DAT0), 4 (DAT[3:0]), or 8 (DAT[7:0]).

Figure 12: Data Packet Transfer

Command ResponseCMD

DAT[7:0]

From deviceto host

From hostto device



Data packet


( )

Figure 13: Data Packet Format: 1-Bit Bus (only DAT0 used)

DAT0

Block dataStart bit:always 0

0 CRC 1

End bit:always 1

Block length × 8

b7 b6 … b1 b0b7 b6 … …b1 b0

Leastsignificant byte

Mostsignificant byte

Figure 14: Data Packet Format: 4-Bit Bus (DAT[3:0] used)

0DAT3

DAT2

DAT1

DAT0

b7 … b3 CRC 1

0 b6 … b2 CRC 1

0 b5 … b1 CRC 1

0 b4 … b0 CRC 1


(high nibble)


(low nibble)

Block length × 2

b7

b6

b5

b4

b3

b2

b1

b0

4GB, 8GB, 16GB, 32GB: e·MMCBus Protocol – Data Packet



Figure 15: Data Packet Format: 8-Bit Bus (DAT[7:0] used)

0DAT7

DAT6

DAT5

DAT4

DAT3

DAT2

DAT1

DAT0

b7b7 … b7 CRC 1

0 b6b6 … b6 CRC 1

0 b5b5 … b5 CRC 1

0 b4b4 … b4 CRC 1

0 b3b3 … b3 CRC 1

0 b2b2 … b2 CRC 1

0 b1b1 … b1 CRC 1

0 b0b0 … b0 CRC 1



Block length

4GB, 8GB, 16GB, 32GB: e·MMCBus Protocol – Data Packet



Bus Protocol – CRCThe cyclic redundancy check (CRC) protects e·MMC commands, responses, and datatransfers against transmission errors on the e·MMC bus. One CRC value is generated forevery command and checked for every response on the CMD line.

For data blocks, one CRC is generated for each transferred block on each data line. TheCRC value is generated and checked as described below.

CRC7The CRC7 check is used for all commands, for all responses except type R3, and for theCSD and CID registers. CRC7 is a 7-bit value computed as follows:

G(x) = x7 + x3 +1M(x) = ( first bit ) × xn + (second bit ) × xn–1 + ... + ( last bit ) × x0

CRC[6 ... 0] = Remainder [M(x) × (x7)/G(x)]

All CRC registers are initialized to 0. The first bit is the leftmost bit of the correspondingbit string (in the command, response, CID, or CSD). The degree n of the polynomial isthe number of CRC protected bits decreased by 1. The number of bits to be protected is40 for commands and responses (n = 39) and 120 for the CSD and CID (n = 119).

Figure 16: CRC7 Generator/Checker

Data in

Data out

4GB, 8GB, 16GB, 32GB: e·MMCBus Protocol – CRC



CRC16CRC16 is used for payload protection in block transfer mode. The CRC checksum is a 16-bit value and is computed as follows:

G(x) = x16 + x12 + x5 + 1M(x) = ( first bit ) × xn + (second bit ) × xn–1 + ... + ( last bit ) × x0

CRC[15 ... 0] = Remainder [M(x) × (x16)/G(x)]

All CRC registers are initialized to 0. The first bit is the first data bit of the correspondingblock. The degree n of the polynomial denotes the number of bits in the data block de-creased by 1 (for example, n = 4095 for a block length of 512 bytes). The generatorpolynomial is a standard CCITT polynomial. The CRC code has a minimal distance d =4 and is used for a payload length of up to 2048 bytes (n ≤ 16,383). The same CRC16calculation is used for all bus configurations. In 4-bit and 8-bit bus configurations,CRC16 is calculated for each line separately. The sending of the CRC is synchronized sothe CRC code is transferred at the same time on all lines.

Figure 17: CRC16 Generator/Checker

Data in

Data out

4GB, 8GB, 16GB, 32GB: e·MMCBus Protocol – CRC



Bus Protocol – CRC Status Token

CRC Status TokenDuring a write operation, data sent by the host is suffixed with CRC bits to enable thedevice to check for transmission errors. The device sends back the CRC result as a CRCstatus token on DAT0. If a transmission error occurs on any of the active data lines, thedevice sends a negative CRC status (101) on DAT0. If a transmission is successful overall active data lines, the device sends a positive CRC status (010) on DAT0 and starts thedata programming sequence.

Figure 18: CRC Status

Command ResponseCMD

DAT[7:0]

From hostto device

From deviceto host




( )

4GB, 8GB, 16GB, 32GB: e·MMCBus Protocol – CRC Status Token



Bus Protocol – Clock ControlThe e·MMC bus clock signal can be used by the host to put the device into energy sav-ing mode or to control the data flow (avoiding underrun or overrun conditions) on thebus. The host is able to lower the clock frequency or shut it down.

Host RestrictionsThere are a few restrictions the host must accommodate relative to clock control:

• The bus frequency can be changed at any time, as long as the maximum data transferfrequency requirements (defined by the device) and the identification frequency re-quirements (defined by the data sheet) are met.

• The clock must be running for the device to output data or response tokens. Follow-ing the last e·MMC bus transaction, the host must provide 8 clock cycles for thedevice to complete the operation. The host can then shut down the clock.

Bus TransactionsThe host must accommodate these e·MMC bus transactions and clock controls:

• A command with no response: The host must provide 8 clocks after sending the hostcommand end bit.

• A command with a response: The host must provide 8 clocks after the device re-sponse end bit is received.

• A read data transaction: The host must provide 8 clocks after the end bit of the lastdata block is received.

• A write data transaction: The host must provide 8 clocks after the CRC status token isreceived.

• The host can shut down the clock of a busy device. The device will complete the pro-gramming operation underway regardless of the host clock. However, the host mustprovide a clock edge for the device to turn off its busy signal. Without a clock edge,the device (unless previously disconnected by a deselect command such as CMD7)will force the DAT0 line LOW.

4GB, 8GB, 16GB, 32GB: e·MMCBus Protocol – Clock Control



Bus Protocol – Bus Error ConditionsThe following error conditions can occur on the e·MMC bus:

• COM_CRC_ERROR

• ILLEGAL_COMMAND

• ADDRESS_OUT_OF_RANGE

COM_CRC_ERROR BitAll commands are protected by CRC bits. If the addressed device’s CRC fails, the devicedoes not respond, the command is not executed, and the device does not change itsstate. The COM_CRC_ERROR bit is set in the status register.

ILLEGAL_COMMAND Error BitIf an illegal command is received, the device does not change its state or respond; it setsthe ILLEGAL_COMMAND error bit in the status register. Illegal commands include com-mands that belong to classes not supported by the device (for example, write com-mands in read-only devices); commands that are not supported in the current state (forexample, CMD2 in the transfer state); and commands that are not defined (for example,CMD44).

ADDRESS_OUT_OF_RANGE ErrorTo improve read performance for multiple-block read operations, the device can fetchdata from the memory array ahead of the host. The device may attempt to access databeyond the last physical memory address while the host is still reading the data fromthe last physical address. In this situation, the device may generate an AD-DRESS_OUT_OF_ RANGE error, even though the data being read by the host is valid.The host should ignore the error.

Even if the host issues the STOP_TRANSMISSION command to stop the device immedi-ately after the last byte of data is read, the device may already have generated the error,and it will show in the response to the STOP_TRANSMISSION command. Again, thehost should ignore this error.

4GB, 8GB, 16GB, 32GB: e·MMCBus Protocol – Bus Error Conditions



MMC Mode Bus Operations

NO RESPONSE OperationIn a NO RESPONSE operation, a host issues a command to the device and the devicedoes not respond. The following commands elicit no response:

• CMD0 (GO_IDLE_STATE, GO_PRE_IDLE_STATE, BOOT_INITIATION)

• CMD4 (SET_DSR)

• CMD7 (DESELECT_CARD)

• CMD15 (GO_INACTIVE_STATE)

Figure 19: MMC Mode NO RESPONSE Operation

CommandCMD

DAT[7:0]

From hostto device(s)

Command

From hostto device

Operation (no response)

NO DATA Operation Without a Busy IndicatorThis operation is composed of a command token and a response token. The followingcommands elicit a no data response without a busy indicator:

• CMD1 (SEND_OP_COND)

• CMD2 (ALL_SEND_CID)

• CMD3 (SET_RELATIVE_ADDR)

• CMD7 (SELECT)

• CMD9 (SEND_CSD)

• CMD10 (SEND_CID)

• CMD12 (STOP_TRANSMISSION)

• CMD13 (SEND_STATUS)

• CMD16 (SET_BLOCKLEN)

• CMD23 (SET_BLOCK_COUNT)

• CMD35 (ERASE_GROUP_START)

• CMD36 (ERASE_GROUP_END)

4GB, 8GB, 16GB, 32GB: e·MMCMMC Mode Bus Operations



Figure 20: MMC Mode NO DATA Operation Without a Busy Indicator

CMD

DAT[7:0]

Command

From hostto device

From deviceto host

Response

Operation (no data)

R1, R2, R3

NO DATA Operation With a Busy IndicatorThis operation is composed of a command token and a response token. The followingcommands elicit a no data response with a busy indicator:

• CMD5 (SLEEP_AWAKE)

• CMD6 (SWITCH)

• CMD7 (SELECT)

• CMD12 (STOP_TRANSMISSION)

• CMD38 (ERASE)

• CMD28 (SET_WRITE_PROT)

• CMD29 (CLR_WRITE_PROT)

Figure 21: MMC Mode NO DATA Operation With a Busy Indicator

CMD

DAT0

DAT[7:1]

Command

From hostto device

From deviceto host

Response

Operation (no data)

Busy




DATA TRANSFER OperationThis operation applies to block-oriented commands and is composed of a commandtoken, a response token, and data packets. The block-oriented commands transfer a da-ta block followed by CRC bits. Both READ and WRITE operations support single ormultiple block data transfers. A multiple block transfer is terminated when aSTOP_TRANSMISSION command follows a read or write command on the CMD line.

See Data Read Timing and Data Write Timing for detailed data transfer operation timing.

Figure 22: MMC Mode Multiple-Block Read Operation

Command ResponseCMD

DAT[7:0]

From hostto device

Command

STOP commandstops data transfer

From deviceto host

Data block CRCData block CRC Data block

Response

CRC

Data from deviceto host

Single-block READ operation STOP TRANSFER operation

Multiple-block READ operation

The following read commands elicit a data transfer response:

• CMD8 (SEND_EXT_CSD)

• CMD14 (BUSTEST_R)

• CMD17 (READ_SINGLE_BLOCK)

• CMD18 (READ_MULTIPLE_BLOCK)

• CMD30 (SEND_WRITE_PROT)

• CMD31 (SEND_WRITE_PROT_TYPE)

In a BLOCK WRITE operation, the device sends a busy signal to the host on the data(DAT0) line.




Figure 23: MMC Mode Multiple-Block Write Operation

Command ResponseCMD

DAT0

DAT[7:1]

From hostto device

Command

STOP commandstops data transfer

From deviceto host

Data block CRC CRC status Busy CRC status BusyData block

Response

CRCData

from hostto device

Busyfrom device

to host

XXXXXXXXXX XXXXXXXXXXData block CRC Data block CRC

Single-block WRITE operation STOP_TRANSFER operation

Multiple-block WRITE operation

The following write commands elicit data transfer and busy responses:

• CMD19 (BUSTEST_W)

• CMD24 (WRITE_BLOCK)

• CMD25 (WRITE_MULTIPLE_BLOCK)

• CMD26 (PROGRAM_CID)

• CMD27 (PROGRAM_CSD)

• CMD42 (LOCK_UNLOCK)




Partition Management

Memory Partition OrganizationPrior to any PARTITION operation, the memory configuration consists of the user dataarea, an RPMB area partition, and boot area partitions, which have dimensions and tech-nology features that are defined by the memory manufacturer.

Figure 24: e·MMC Memory Partitions Prior to PARTITION Operation

Userdata area

Boot areapartition 1

0x000000000x00000000


0x00000000

RPMBpartition

0x00000000

Size as multipleof 128KB

Device size - 1

The device can also be configured with additional split local memory partitions thathave independent addressable space, starting with logical address 0x00000000 for differ-ent system usage models.

The memory block areas can be classified as follows:

• Two boot area partitions, the sizes of which are a multiple of 128KB, from which boot-ing from the e·MMC can be performed.

• One RPMB partition accessed through a trusted mechanism, the size of which is de-fined as a multiple of 128KB.

• Four general-purpose partitions for storing sensitive data, or for other host usage mod-els, the sizes of which are a multiple of a write protect group (WPG).

Each of the general-purpose partitions can be implemented with enhanced technologi-cal features (such as better reliability), which distinguish them from the default storagemedia. If the enhanced storage media feature is supported by the device, boot andRPMB area partitions are implemented as enhanced storage media by default.

Boot and RPMB area partition sizes and attributes are defined by the memory manufac-turer (read-only), while general-purpose partition sizes and attributes can be program-med by the host.

Moreover, the host can configure one segment in the user data area that can be imple-mented as enhanced storage media, and it can specify its starting location and size interms of write protect groups.

The sizes and attributes of the general-purpose partition and the enhanced user dataarea can be programmed only once, and at the same time, during the device life cycle.

4GB, 8GB, 16GB, 32GB: e·MMCPartition Management



Figure 25: Example of Partitions and User Data Area Configuration

Userdata area

Enhanced userdata area


Boot area partition

RPMB area partition

General-purpose partitions(four partitions maximum)

0x00000000

0x00000000


0x00000000

RPMBpartition

Partition 1 Partition 2 Partition 3 Partition 4

Partition Defaultstorage media

Enhancedstorage media

0x00000000

0x00000000

Size as multipleof 128KB

Multipleof WPG1 size

Device size2

WPG1 size

Notes: 1. WPG = Write Protect Group.2. Device size needs to be recalculated by C_SIZE value for a device up to 2GB and

SEC_COUNT value for a device greater than 2GB.

General-purpose partitions and enhanced user data area configuration by the host canaffect device initialization time and the data previously stored (that is, the data can bedestroyed).

In particular, the initialization time after the first power cycle subsequent to the config-uration can exceed the maximum initialization time defined by the specifications, sincethe internal controller could execute operations to set up the configurations stated bythe host. The maximum initialization time is specified in ECSD register byte 241.

More generally, the following initialization time can be affected by the new configuration.

Partition Command RestrictionsThe following are restrictions for commands that can be issued to each partition:

• Boot partitions: Command class 6 (write protect) and class 7 (lock card) are not per-mitted.




• RPMB partition: Only commands of classes 0, 2, and 4 are permitted. Use of com-mands other than CMD0, CMD6, CMD8, CMD12, CMD13, or CMD15, or commandsdefined in the Data Transfer Mode – RPMB section, are considered illegal.

• General-purpose partitions: Command classes 0, 2, 4, 5, 6 are permitted. Write protec-tion can be set individually for each WPG in each partition. The host can set writeprotection types differently in each WPG.

In the enhanced user data area, all the commands belonging to the classes permitted inthe user data area can be issued.

Configuring PartitionsBit 0 (PARTITIONING_EN) in the PARTITIONING_SUPPORT field of the properties seg-ment in the ECSD register indicates whether the memory device supports partitioningfeatures. Bit 1 (ENH_ATTRIBUTE_ EN) in the same field indicates whether the memorydevice supports the enhanced features attribute in the general-purpose partitions andin the enhanced user data area.

The attributes of general-purpose partitions and the enhanced user data area can beprogrammed by the host by setting the corresponding values in the extended CSD regis-ters only once during the device life cycle.

In particular, the host may issue a SWITCH command to set the R/W field of partitionfeatures that contain the following parameters:

• General-purpose partitions: The size and attribute of a maximum of four partitions.The following fields should be set in the modes segment of the ECSD register:– GP_SIZE_MULT_GP0 – GP_SIZE_MULT_GP3 for the size– PARTITIONS_ATTRIBUTE for the enhanced attribute

• Enhanced user data area: The start address and attribute of the region. The followingfields should be set in the modes segment of the ECSD register:– ENH_START_ADDR for the start address– ENH_SIZE_MULT for the size– PARTITIONS_ATTRIBUTE for the enhanced attribute

The enhanced user data area start address (ENH_START_ADDR in the extended CSDregister) is aligned with the WPG. It is a group address in byte units for densities up to2GB, or in sector units for densities greater than 2GB. The device ignores the LSBs be-low the write group size and aligns the enhanced user data area start address with theWPG that the address (in bytes or sectors) belongs to. The address space of the en-hanced user data area is contiguous with the address space of the rest of the user dataarea; there is no gap in addresses between the enhanced user data area and the rest ofthe user data area.

The granularity of general-purpose partitions and of the enhanced user data area is inunits of high-capacity WPG sizes (see ECSD Register). When the partition parametersare configured, the ERASE_GROUP_DEF bit in the extended CSD register is set to indi-cate that high-capacity erase group sizes and high-capacity WPG sizes are to be used. Ifthe partition parameters are sent to a device via the SWITCH (CMD6) command beforesetting the ERASE_GROUP_DEF bit, the device issues a SWITCH_ERROR.

If a user wishes to execute a partition configuration on a device in which user data hasalready been stored, the data must first be erased before configuring the partition.

After the device is partitioned and the configuration is stable, all the command class 5and 6 commands are referred to the high-capacity erase groups and write-protect groups.




In addition to partitioning parameter fields mentioned before, the host needs to set bit0 in PARTITIONING_SETTING_COMPLETED in the modes segment. In this way, thehost notifies the device that the setting procedure has successfully completed. Settingthis bit protects the partitioning sequence against an unexpected power loss event. Ifthis bit is not set, and if a sudden power loss occurs after the partitioning process hasonly been partially executed, at the next power-on, the device can detect and invalidatethe incomplete partitioning process. This enables the host to repeat and correctly com-plete the partitioning process.

The host issues a CMD13 to ensure that all the parameters are correctly set. If any of thepartitioning parameters is not correct, the device issues a SWITCH_ERROR. The devicedoes not know the total size of the configured partitions and the user data area until thePARTITIONING_SETTING_COMPLETED bit is set; therefore, if the total size of the con-figured partitions and the user data area does not fit in the available space of the device,the device may issue a SWITCH_ERROR when the host sets thePARTITIONING_SETTING_COMPLETED bit. So, after the next power cycle, the hostmust set the proper values in each of the partition configuration register bytes again.

The device only configures itself after a power cycle, according to the partition parame-ters in the extended CSD. Any valid commands issued after the PARTITIONING_SET-TING_COMPLETED bit is set, but before a power cycle takes place, are executed in anormal way. Any previous incomplete partitioning configuration sequence, before thisbit is set, is canceled upon a power cycle.

After the power cycle, following the partition configuration, C_SIZE value for up to 2GBdevices, and SEC_COUNT value for greater than 2GB devices, are changed to indicatethe size of the user data area after the configuration. The size, compared to 2GB, shouldbe the size of the user data area before configuring partitions. For example, for greaterthan 2GB devices, before configuring partitions, SEC_COUNT should keep indicatingthe size of the user data area after configuring partitions, even if the size is decreased toless than or equal to 2GB. The size of the user data area includes the size of the en-hanced user data area in the user area. The host may need to read these values after thepower cycle to calculate the size of the user data area. Access mode (byte or sector)should be kept after configuring partitions.

If the host attempts to change general-purpose partitions and enhanced user data areafeatures by using SWITCH (CMD6) command after a power-on and the following config-uration procedure, the device asserts the SWITCH_ERROR bit in the status register of aCMD6 response without performing any internal action.

Partition configuration parameters are stored in one-time programmable fields of theECSD register. The host can issue a SEND_EXT_CSD (CMD8) command to read them,even though PARTITIONING_SETTING_COMPLETED has not been set. However, theexecution of partitioning takes place only after the power-on. After reading the partitionconfiguration parameters, changes to those parameters should be avoided, since theyare one-time programmable fields.

The host must follow the flowchart in Figure 26 (page 104) for configuring the parame-ters of general-purpose area partitions and the enhanced user data area; otherwise,undefined behavior may result.




Figure 26: General-Purpose and Enhanced User Data Area Parameter-Setting Flow Chart

Set number of general-purpose partitions,general-purpose partitions sizes

and enhanced attribute, enhanceduser data area size, and start address,

and enhanced attribute

Set number of general-purpose partitionsand general purpose partitions sizes

Device in tran state

Partitions correctlyconfigured

Partitioning feature not supportedor device not configurable

Host wants to configuredevice partitioning

PARTITIONING_SETTING_COMPLETED(to notify the device that the host

has completed partitioning configuration)

PARTITIONING_EN = 1?

Does host want toset ENH attribute to

partitions?

EN_ATTRIBUTE = 1?

No

No

Yes

Yes

Yes

No

Possible change in size parametersfor user data area1

Power cycle

Note: 1. Longer initialization time, compared to a nonconfigured device.




Accessing PartitionsAfter every power-on, when the host uses a device in which partitions are configured, itmust set the ERASE_GROUP_DEF bit to 1 before issuing read, write, erase, and writeprotect commands. This is because the ERASE_GROUP_DEF bit is reset after power-on.Otherwise, those commands may not function properly and stored data may be left inan unknown state.

Each time the host wants to access a partition, the following steps are executed:1. PARTITION_ACCESS bits in the PARTITION_CONFIG field of the extended CSD

register are set to address one of the partitions.2. Commands referred to the selected partition are issued.3. Data access is redirected to another partition by performing step 1.

All the reset events caused by issuing CMD0 or asserting the RST_n signal restore accessto the user data area by default.

If an unwanted power loss occurs, access to the user data area is restored by default.

When the host attempts to access a partition that has not previously been created, thedevice sets the SWITCH_ERROR bit in the status register and does not change the PAR-TITION_ACCESS bits.




Operating ModesThe four device operating modes are: inactive mode, boot mode, card identificationmode, and data transfer mode. Dependencies between operating modes, bus modes,and valid device states are shown in the following table. Each state in the e·MMC statediagram is associated with one bus mode and one operating mode.

Table 105: Operating Modes, Bus Modes, and Device States

Operating Mode Bus Mode Valid Device StatesDevice State

Abbreviations

Inactive Open-drain Inactive state ina

Boot mode Pre-idle state preidle

Preboot state preboot

Card identification mode Idle state idle

Ready state ready

Identification state ident

Data transfer mode Push-pull Standby state stby

Sleep state slp

Transfer state tran

Bus test state btst

Sending data state data

Receive data state rcv

Programming state prg

Disconnect state dis

Boot mode Boot state boot

4GB, 8GB, 16GB, 32GB: e·MMCOperating Modes



Boot ModeThe device has two boot partition regions and a user area. The minimum size of eachboot partition is defined in the extended card-specific data (ECSD) register.

In boot operation mode, the host can read boot data from the device by keeping theCMD line LOW or sending CMD0 with an argument of 0xFFFFFFFA before using CMD1.The data can be read either from the boot area or the user area, depending on the regis-ter setting.

Device Reset to Pre-Idle StateThe device may enter into the pre-idle state through any of the following four mechanisms:

• After power-on by the host, the device, even if it has been in the inactive state, is inMultiMediaCard mode and in the pre-idle state.

• The device receives the GO_PRE_IDLE_STATE command (CMD0 with an argument of0xF0F0F0F0). This is a software reset command that moves the device into the pre-idle state.

• The host asserts the RST_n signal, which performs a hardware reset on the device andmoves it to the pre-idle state. This also disables the power-on period write protect onblocks that have been set as power-on write-protected before the RST_n signal wasasserted.

• The device receives the GO_PRE_IDLE_STATE command (CMD0 with an argument of0xF0F0F0F0) or assertion of the RST_n signal during the sleep state.

Figure 27: Write Protect Condition Transition Due to Assertion of RST_n Signal

WP group B(Power-on period WP)

WP group C(Temporary WP)

WP group D(Unprotected)

WP group B(Unprotected)

WP group C(Temporary WP)

WP group D(Unprotected)

After power-on, the GO_PREIDLE_STATE command is issued, or the RST_n signal is as-serted, the device’s output bus drivers are in the High-Z state, and the device is initial-ized with a default relative device address (0x0001) and with a default driver stageregister setting.

4GB, 8GB, 16GB, 32GB: e·MMCBoot Mode



Boot PartitionsThe maximum boot partition size is calculated as:

Maximum boot partition size = 128KB × BOOT_SIZE_MULTwhereBOOT_SIZE_MULT = Value in ECSD register byte 226

The boot partitions are separated from the user area, as shown below.

Figure 28: Boot Partitions

Userarea

Bootpartition 1

Bootpartition 2

0x000000000x00000000

Maximum bootpartition size

Maximum bootpartition size

0x00000000

The boot configuration is stored in ECSD register byte 179. The host selects the configu-ration by setting the register using the SWITC (CMD6) command. The device can alsobe configured to boot from the user area by setting the BOOT_PARTITION_ ENABLEbits in the ECSD register byte 179 to 111 binary.




Boot Mode OperationAfter a power-on or reset sequence (either through CMD0 with an argument of0xF0F0F0F0 or assertion of the RST_n signal, if enabled), if the CMD line is held LOWfor 74 or more clock cycles before the SEND_OP_COND (CMD1) command is issued,the device recognizes that boot mode is being initiated and prepares to boot data inter-nally. The partition from which the host will read the boot data can be selected inadvance using ECSD byte 179, bits[5:3].

The data size that the host can read during a BOOT operation is calculated as 128KB ×BOOT_SIZE_MULT (ECSD register byte 226). Within 1 second after the CMD line goesLOW, the device starts to send the first boot data to the host on the DAT line(s). Thehost must keep the CMD line LOW to read all of the boot data. The host must use push-pull mode until the BOOT operation is terminated.

By setting the proper values in ECSD register byte 177, bits[4:3], the host can choose touse single data rate mode with backward-compatible interface timing, single data ratemode with high-speed interface timing, or dual data rate timing (if supported) (see Busand Device Interface Timing). ECSD register byte 228, bit 2 notifies the host whether thedevice supports high-speed timing during a boot.

The host can choose to receive boot acknowledgement from the device by setting ECSDregister byte 179, bit 6 to 1. This enables the host to recognize that the device is operat-ing in boot mode.

If the BOOT ACKNOWLEDGE function is enabled, the device must send the acknowl-edge pattern 010 to the host within 50ms after the CMD line goes LOW. If the BOOTACKNOWLEDGE function is disabled, the device does not send out the acknowledgepattern 010.

The host can terminate boot mode with the CMD line HIGH. If the host pulls the CMDline HIGH in the middle of a data transfer, the device must terminate the data transferor acknowledge pattern within NST clock cycles (1 data cycle and 1 end bit cycle). If thehost terminates boot mode between consecutive blocks, the device must release the da-ta line(s) within NST clock cycles.

A BOOT operation is terminated when all contents of the enabled boot partition aresent to the host. After a BOOT operation is complete, the device is ready for a normale·MMC initialization sequence, and the host can send CMD1 to begin an e·MMC identi-fication sequence.




Figure 29: Boot Mode Operation Timing

Z Z Z Z * * * * * *Z

Z Z Z * * * Z

S 0 1 0 E S EP P * * *P P

CMD

DAT0

Z Z Z S * * *L

512 bytes + CRC S 512 bytes

Boot terminated

Boot acknowledge1

P Z

CMD

DAT0

* P

S E512 bytes + CRC * * * *

Device activeHost active

1

1

CMD1 CMD2 CMD3RESP RESP RESP

Note: 1. This is optional for the host. To use this feature, the host must set ECSD register byte179, bit 6, to 1.

See BOOT Operation Timing for detailed BOOT operation timing diagrams.

The device can operate in boot mode only if, following a power-on, the CMD line isheld LOW for at least 74 clock cycles or CMD0 with an argument of 0xFFFFFFFA is is-sued before issuing CMD1.

After power-on, before initiating boot mode, if the CMD line is held LOW for less than74 clock cycles, or the host sends any normal MMC command other than CMD0 with anargument of 0xFFFFFFFA, the device does not respond. It is locked out of boot modeuntil the next power cycle, CMD0 with an argument of 0xF0F0F0F0, or assertion of theRST_n signal, and enters the idle state.

When BOOT_PARTITION_ENABLE bits are set and the host sends CMD1(SEND_OP_COND), the device enters card identification mode and responds to the com-mand.

Following power-on, if the BOOT_PARTITION_ENABLE bit is cleared, the device auto-matically enters the idle state.




Alternative Boot Mode OperationAn alternative boot mode operation is mandatory for a device that conforms to thee·MMC v4.4 specification. To invoke the alternative boot mode operation, the devicemust set bit 0 to a 1 in ECSD register byte 228.

After a power-on or reset sequence (initiated by CMD0 with an argument of0xF0F0F0F0 or assertion of the RST_n signal, if enabled), if the host issues CMD0 withan argument of 0xFFFFFFFA after 74 clock cycles, and before CMD1 is issued, the de-vice recognizes that boot mode is being initiated and starts preparing boot data internal-ly. The partition from which the host will read the boot data can be selected in advanceusing ECSD register byte 179, bits[5:3].

The data size that the host can read during a BOOT operation can be calculated as128KB × BOOT_SIZE_MULT (ECSD register byte 226). Within 1 second after CMD0 withan argument of 0xFFFFFFFA is issued, the device starts to send the first boot data to thehost on the DAT line(s). The host must use push-pull mode until the BOOT operation isterminated.

By setting the proper values in ECSD register byte 177, bits[4:3], the host can choose touse single data rate mode with backward-compatible interface timing, single data ratemode with high-speed interface timing, or dual data rate timing (if supported) (see Busand Device Interface Timing). ECSD register byte 228, bit 2 notifies the host whether thedevice supports high-speed timing during a boot.

The host can choose to receive boot acknowledge from the device by setting ECSD regis-ter byte 179, bit 6 to 1. This enables the host to recognize that the device is operating inboot mode.

If BOOT ACKNOWLEDGE is enabled, the device must send the acknowledge pattern010 to the host within 50ms after CMD0 with an argument of 0xFFFFFFFA is received. IfBOOT ACKNOWLEDGE is disabled, the device does not send out acknowledge pattern010.

The host can terminate boot mode by issuing the GO_IDLE_STATE (CMD0) command.If the host issues CMD0 in the middle of a data transfer, the device must terminate thedata transfer or acknowledge pattern within NST clock cycles (1 data cycle and end bitcycle). If the host terminates boot mode between consecutive blocks, the device mustrelease the data line(s) within NST clock cycles.

A BOOT operation is terminated when all the contents of the enabled boot data are sentto the host. After the BOOT operation is executed, the device is ready for the host toissue the SEND_OP_COND (CMD1) command to start an e·MMC identification sequence.




Figure 30: Alternative Boot Mode Timing

Z Z Z Z * * * * * *

* * *

Z

Z Z Z * * * Z

Z * * * Z

S 0 1 0 E S EP P * * *P P

CMD

DAT0

Z Z

512 bytes + CRC S 512 bytes

Boot terminated

Boot acknowledge

P Z Z

CMD

DAT0

*

Note 2

Note 1

S E512 bytes + CRC * * * *


1

1

CMD1CMD0

CMD0

CMD2 CMD3RESP RESP RESP

Notes: 1. CMD0 with an argument of 0xFFFFFFFA.2. A minimum of 74 clocks are required after power is stable to start the BOOT command.

Detailed BOOT operation timings are shown in BOOT Operation Timing (page 179).

After power-on, before initiating boot mode, if the CMD line is held LOW for fewer than74 clock cycles or the host sends any standard MMC command other than CMD0 withan argument of 0xFFFFFFFA, the device does not respond. It is locked out of boot modeuntil the next power cycle and enters the idle state.

When BOOT_PARTITION_ENABLE bits are set and the host sends theSEND_OP_COND (CMD1) command, the device enters the card identification modeand responds to the command.

Following power-on, if the BOOT_PARTITION_ENABLE bit is cleared, the device auto-matically enters the idle state.




Figure 31: Boot Mode State Diagram

CMD signal LOWfor 74 or more clock cycles

Boot sequence not supportedor

BOOT_PARTITION_ENABLE bit clear

Pre-idle state(preidle)

Pre-boot state(preboot)

BOOT_PARTITION_ENABLE bit set

CMD signal LOWfor fewer than 74 clock cycles

except CMD1 and CMD0 with argument = 0xFFFFFFFA

CMD signal HIGHor completion of the

boot operation(Data in the wholeboot area has been

read out)

Boot state(boot)

CMD1 CMD15Inactive state

(ina)

Idle state(idle)

CMD0with argument = 0x00000000

CMD0with argument = 0xF0F0F0F0

From all states exceptinactive state (ina)

RST signalFrom all states exceptinactive state (ina)


Bootmode

Device is busyor host omittedvoltage range

Power-up

CMD0with argument = 0xFFFFFFFA

CMD0 or completion of the boot operation

(Data in the wholeboot area has been

read out)

Boot state(boot)




Accessing Boot PartitionsTo access a boot partition, the host must first put the device into the transfer state, andthen send the SWITCH (CMD6) command to set the PARTITION_ACCESS bits in ECSDregister byte 179. The host can then use standard e·MMC commands to access a bootpartition.

The host can program boot data on DAT line(s) by issuing the WRITE_BLOCK (CMD24)command or the WRITE_MULTIPLE_BLOCK (CMD25) command with the addressingmode supported by the device (byte addressing or sector addressing). If the host usesCMD25 and subsequently writes past the selected partition boundary, the device re-ports an ADDRESS_OUT_OF_RANGE error. Data that is within the partition boundaryis written to the selected boot partition.

The host can read boot data on DAT line(s) using the READ_SINGLE_BLOCK (CMD17)command or the READ_MULTIPLE_BLOCK (CMD18) command with the addressingmode supported by the device (byte addressing or sector addressing). If the host usesCMD18 and then reads past the selected partition boundary, the device reports an AD-DRESS_OUT_OF_RANGE error.

After completing boot partition data access, the PARTITION_ACCESS bits must becleared. After the bits are cleared, nonvolatile BOOT_PARTITION_ENABLE bits in theECSD register should be set to indicate which partition is enabled for booting. This ena-bles the device to read data from the designated boot partition during a BOOT operation.

The host can also access the user area using standard commands by clearing the PARTI-TION_ACCESS bits in ECSD register byte 179 to 000 binary.

If the user area is locked and enabled for boot, data is not sent to the host while in bootoperation mode. However, if the user area is locked and one of the two boot partitionsis enabled, data is sent to the host while in boot operation mode.

Boot Bus Width and Access ConfigurationDuring a BOOT operation, the bus width can be configured using nonvolatile configura-tion bits in ECSD register byte 177, bits[1:0]. Bit 2 in ECSD register byte 177 determineswhether the device will return to x1 bus width and single data rate mode with backward-compatible timing after a BOOT operation or remain in the configured boot bus widthduring normal operation. Bits[4:3] in ECSD register byte 177 determines whether thedata lines are configured for single data rate using backward-compatible or high-speedtimings or for dual data rate mode during a BOOT operation. If a BOOT operation is notexecuted, the device initializes in normal x1 bus width, single data rate operation, andbackward compatible timing, regardless of the register setting.




Boot Partition Write ProtectionTo enable the host to protect the boot area against an ERASE or WRITE, the device sup-ports two levels of write protection:

• The boot area can be permanently write-protected by setting B_PERM_WP_EN(ECSD register byte 173, bit 2).

• The boot area can be power-on write-protected by setting B_PWR_WP_EN (ECSD reg-ister byte 173, bit 0).

When using power-on write protection for the boot area, the host must be aware of thefollowing:

• After a power cycle event that causes a device reboot, or after the RST_n signal is asser-ted, power-on write protection must be reapplied, if required, since the boot areareturns to the unprotected state.

• Permanent write protection can still be applied to the boot area after power-on pro-tection has been enabled. Therefore, if permanent write protection is not required,B_PERM_WP_DIS (ECSD register byte 173, bit 4) should be set to prevent permanentprotection from being set maliciously or unintentionally.

The host can disable both permanent and power-on write protection in the boot areaby setting B_PERM_WP_DIS (ECSD register byte 173, bit 4) and B_PWR_WP_DIS (ECSDregister byte 173, bit 6). If boot area protection is not required, it is recommended thatthese bits be set in order to ensure that the boot area is not protected unintentionally ormaliciously.




Card Identification ModeThe device is in card identification mode after the boot mode has completed, or if thehost does not support boot mode. The device is in this mode until it receives theSET_RCA command (CMD3).

In card identification mode, the host resets the device, validates the operating voltagerange and access mode, identifies the device, and assigns an RCA to the device on thebus. In card identification mode, all data communications use the CMD line only.

Figure 32: Card Identification Mode State Diagram

CMD15

CMD2

Ready state(ready)

CMD3

Identificationstate (ident)

Standby state(stby)

Inactive state(ina)Host cannot use

sector access modein cards > 2GB

From all states exceptsleep state (slp)

in data transfer mode

Data transfermode

Cardidentification

mode

Outgoing device CID bitsdo not match corresponding bits

on the command line

Outgoing device CID bits matchcorresponding bits on the command line

CMD signal HIGHor CMD0

CMD1

Idle state(idle) CMD0


Bootmode

Device is busyor host omittedvoltage range

4GB, 8GB, 16GB, 32GB: e·MMCCard Identification Mode



Device ResetAfter receiving the GO_IDLE_STATE (CMD0 with an argument of 0x00000000) com-mand, the device goes to the idle state.

A device also enters the idle state after completing a BOOT operation, after receivingSEND_OP_COND (CMD1) in a pre-idle state, or after power-on if the device is not boot-enabled.

In the idle state, the device’s output bus drivers are in a High-Z state and the device isinitialized with a default relative card address (0x0001) and with a default driver stageregister setting. The host clocks the bus at the identification clock rate FOD, as describedunder “Bus and Device Interface Timing”.

CMD0 with an argument of 0x00000000 is valid in all states except the inactive state.While in the inactive state, the device does not accept CMD0 with an argument of0x00000000.

For backward-compatibility reasons, if a device receives CMD0 with an argument otherthan 0xFFFFFFFA or 0xF0F0F0F0 in any state except the inactive state, the device treatsit as a reset command and enters the idle state. CMD0 with an argument of0xFFFFFFFA is a BOOT_INITIATION command in a pre-boot state, but if the host issuesthis command in any state except the inactive or pre-boot state, the device treats it as areset command, and the state changes to idle.

Idle State to Ready StateEach e·MMC device is able to establish communication with the host and perform overspecified voltages.

The SEND_OP_COND (CMD1) command is designed for MMC hosts to identify and re-ject MMC cards that do not match the host’s operating voltage range. The host sendsthe required VCCQ voltage range window as the argument of this command. However,the voltage range of CMD1 is no longer valid for e·MMC devices. Regardless of the volt-age range indicated by the host, the e·MMC devices respond and do not move into theinactive state.

Even though e·MMC devices do not care about the host operating voltage range bits,the host must still send the correct access mode in the CMD1 argument. The accessmode is specified in bits[30:29] of the argument. For byte access mode, the bits shouldbe set to 00; for sector access mode, the bits should be set to 10. Byte access mode willbe applied to devices less than or equal to 2GB; sector access mode will be applied devi-ces greater than 2GB.

If the host supports byte access mode, the host cannot use a device with a capacity great-er than 2GB. Therefore, the host must use an e·MMC device with a capacity less than orequal to 2GB on the system. When the host issues CMD1 with byte access mode to adevice with a capacity less than or equal to 2GB, it responds with a fixed pattern of0x00FF8080 as an operating voltage range when the device is busy. When the device isready, it responds with 0x80FF8080.

If the host supports sector access mode, it should also be able to provide byte accessmode for devices with capacities less than or equal to 2GB. Therefore, the host can use adevice of any capacity. When the host issues CMD1 with sector access mode to ane·MMC device, the device responds with a fixed pattern of 0x00FF8080 as an operatingvoltage range when the device is busy. The host should ignore bits[30:29] when the de-




vice is busy. When the device is ready, it responds with either 0x80FF8080 (for acapacity less than or equal to 2GB), or 0xC0FF8080 (for a capacity greater than 2GB).Bits [30:29] are valid only when the device is ready.

When the host issues CMD1 with an argument of all 0s (0x00000000), the argument istreated by the device as a command the host uses to query the MMC card and e·MMCdevice to determine their operating voltage ranges. The e·MMC device responds with afixed pattern of 0x00FF8080 as an operating voltage range. In this case, the host must re-issue CMD1 with a proper argument to the device.

In a multiple-device system, a byte-access-mode device (≤2GB) blocks the OC registerresponse in such way that a sector-access-mode device (>2GB) is not necessarily recog-nized as such during initialization. Thus, the access mode must be reconfirmed byreading the SEC_COUNT information from the ECSD register.

The device can use the busy bit in the CMD1 response to tell the host it is busy workingon its power-on or reset sequence and is not ready for communication. In this case, thehost must repeatedly send CMD1 until the busy bit is cleared.

The host cannot change the operating voltage range. Any changes will be ignored by thedevice. If there is a change in the operating conditions, the host must reset the deviceusing CMD0 with an argument of 0x00000000 and restart the identification mode. How-ever, to access a device that is already in an inactive state, a power cycle must beinitiated to reset the device.

The GO_INACTIVE_STATE (CMD15) command can be used to move an addressed de-vice to the inactive state. CMD15 is used when the host deactivates a device (forexample, when the host is changing VDD to a range that is not supported).

Ready State to Identification StateThe following explanation refers to devices in a multiple-device environment, as de-fined in versions of the e·MMC standard prior to version 4.0. This information is main-tained for backward compatibility with those systems. The device identification processis started by the host in open-drain mode with the identification clock rate FOD. Duringdevice identification, the open-drain driver is used on the CMD line to accommodateparallel device operation.

After the bus is activated, the host uses the SEND_OP_COND (CMD1) command to re-quest valid operating conditions from the devices on the system. The response toCMD1 is the wired-AND operation on the condition restrictions of all devices in the sys-tem. Incompatible devices are sent to the inactive state. The host then issues thebroadcast command ALL_SEND_CID (CMD2), requesting the unique card identifica-tion (CID) number from each device on the bus. All unidentified devices simultaneous-ly begin sending their CID numbers, while at the same time monitoring their outgoingbitstream bit-wise.

Devices with outgoing CID bits that do not match the corresponding bits on the com-mand line in any one of the bit periods stop sending their CID immediately. Thedevices remain in the ready state and wait for the next identification cycle.




Identification State to Standby StateBecause CID numbers are unique to each device, only one device should successfullysend its full CID number to the host. The successful device then enters the identifica-tion state. Thereafter, the host issues the SET_RELATIVE_ADDR (CMD3) command toassign a relative card address (RCA). The RCA is shorter than a CID and addresses thedevice when it enters data transfer mode, typically with a higher clock rate than FOD.

After the RCA is received, the device state changes to standby, and the device does notrespond to further identification cycles. The device also switches its output drivers fromopen-drain to push-pull.

The host repeats the identification process as often as it receives a response (CID) to theALL_SEND_CID (CMD2) command. All devices are identified when there are no otherresponses to this command. The timeout condition that recognizes completion of theidentification process is the absence of a start bit for more than NID clock cycles afterCMD2 is sent.




Data Transfer Mode – OverviewThe device enters data transfer mode after a relative card address (RCA) is assigned toit. The host enters data transfer mode after identifying the device on the bus.

When the device is in the standby state, communication over the CMD and DAT lines isperformed in push-pull mode. Until the contents of the CSD register are known by thehost, the FPP clock rate must remain at FOD. The host issues SEND_CSD (CMD9) to ob-tain information from the CSD register, including block length, device storage capacity,and maximum clock rate.

Figure 33: Data Transfer Mode State Diagram

CMD15

CMD4,9, 10

CMD3 CMD0

CMD7

CMD7

Sleep state(slp)

Standby state(stby)

Transfer state(tran)

Sending-data state (data)

Bus test state(btst)

CMD16, 23,35, 36

CMD19

CMD5 CMD5

From all states indata transfer mode

From all states exceptsleep state (slp) in

data transfer mode

No state transitionin data transfer mode

(except sleep state)

Data transfer mode

Card identification mode

CMD24, 25,26, 27, 42

CMD13

Operationcomplete

Operationcomplete

CMD6, 28,29, 38

CMD14CMD12 ortransfer end

High-priority interrupt(CMD12/CMD13)

Receive-datastate (rcv)

CMD7

CMD24, 25

CMD7

Programmingstate (prg)

Disconnectstate (dis)

CMD12,operationcomplete

CMD8,17, 18,

30

The broadcast command SET_DSR (CMD4) configures the driver stages of the device.SET_DSR programs its DSR so that it corresponds to the application bus layout (length)

4GB, 8GB, 16GB, 32GB: e·MMCData Transfer Mode – Overview



and the data transfer frequency. Refer to the value of DSR_IMP in the ECSD register tocheck whether the device supports this feature.

The clock rate can be changed from FOD to FPP after the device enters the data transfermode.

When the device is in the standby state, the SELECT/DESELECT_CARD (CMD7) com-mand is used with the device’s RCA in the argument to select it and move it into thetransfer state. If the device is in the transfer state, it is deselected if it receives CMD7with any address other than its own RCA. The host connection is released and the de-vice returns to standby. The device also reverts to standby when CMD7 is issued withthe reserved RCA (0x0000). If the device is in the transfer state and receives CMD7 withits own RCA, it ignores the command and treats it as illegal. After a device is assigned anRCA, it does not respond to further identification commands (CMD1, CMD2, and CMD3).

When the device is in the disconnect state, CMD7 is used with the device’s RCA in theargument to select it and put it into the programming state. If the device is in the pro-gramming state, it is deselected if it receives CMD7 with any address other than its ownRCA. The host connection is released and the device returns to the disconnect state. Ifthe device is in the programming state and receives CMD7 with its own RCA, it ignoresthe command and treats it as illegal.

Data communication in data transfer mode is point-to-point between the host and theselected device, using addressed commands. All addressed commands are acknowl-edged by a response on the CMD line.

The relationships between the various data transfer modes is summarized below (seealso Figure 33 (page 120) in this section).

• All data read commands can be aborted any time by the STOP_TRANSMISSION(CMD12) command. The data transfer terminates and the device returns to the trans-fer state. The read commands include: READ_SINGLE_BLOCK (CMD17); READ_MUL-TIPLE_BLOCK (CMD18); and SEND_WRITE_PROT (CMD30).

• All data write commands can be aborted any time by the STOP_TRANSMISSION com-mand (CMD12). The write commands must be stopped before CMD7 deselects thedevice. The write commands include: WRITE_BLOCK (CMD24); WRITE_MULTI-PLE_BLOCK (CMD25); PROGRAM_CID (CMD26); and PROGRAM_CSD (CMD27).

• As soon as the data transfer is complete, the device exits the receive-data state andmoves either to the programming state if the transfer was successful, or to the trans-fer state if the transfer failed.

• If a BLOCK WRITE operation is stopped, and the block length and CRC in the lastblock are valid, the data is programmed.

• The device is capable of providing buffering for block writes. This means that the nextblock can be sent to the device while the previous block is being programmed.

• If all write buffers are full, the DAT0 line is kept LOW for as long as the device is in theprogramming state.

• The PROGRAM_CID (CMD26) and PROGRAM_CSD (CMD27) commands do not havea buffering option. While the device is busy servicing any of these commands, no oth-er data transfer commands are accepted. The DAT0 line is kept LOW for as long as thedevice is busy and in the programming state.

• The SET_BLOCK_LEN (CMD16), ERASE_GROUP_START (CMD35), andERASE_GROUP_END (CMD36) commands are not supported while the device is pro-gramming.

4GB, 8GB, 16GB, 32GB: e·MMCData Transfer Mode – Overview



• The read commands are not supported while the device is programming.

• Moving another device from the standby to the transfer state (using CMD7) does notterminate a programming operation. The device switches to the disconnect state andreleases the DAT0 line.

• While in the disconnect state, a device can be reselected using CMD7. In this case, thedevice moves to the programming state and reactivates the busy indicator.

• Resetting a device by issuing CMD0 or CMD15, asserting the RST_n signal, or a powercycle will terminate any pending or active programming operation. This may leavesome or all the data addressed by the operation in an unknown state, unless reliablewrite was enabled. The host must prevent this from happening.

• Micron recommends that the data transfer clock frequency be set prior to executionof the bus testing procedure (CMD19 and CMD14). The bus test gives a true result ifthe data transfer clock frequency is set. A true result might not be given if the bustesting procedure is performed at a clock frequency lower than the data transfer fre-quency.

Data Transfer Mode – Command Sets and Extended SettingsBy default, after a power cycle, a reset initiated by CMD0 with an argument of0x00000000, or a BOOT operation, the device supports the standard MMC commandset and uses a single data line (DAT0) for data transfers. The host can change the activecommand set by issuing the SWITCH (CMD6) command with the command set accessmode selected.

The supported command sets and the selected command sets are defined in the ECSDRegister section.

The host reads the ECSD register by issuing the SEND_EXT_CSD command. The devicesends the ECSD register as a 512-byte block of data. Any reserved or write-only fieldreads as 0.

The host can write to the modes segment of the ECSD register by issuing a SWITCHcommand and setting one of the access modes (set bits, clear bits, or write byte). Referto the CMD6 argument in Command Descriptions for additional details.

The index field can contain any value from 0–255, but only values 0–191 are valid. If theindex value is in the range of 192–255, the card does not perform any modification andthe SWITCH_ERROR status bit is set.

4GB, 8GB, 16GB, 32GB: e·MMCData Transfer Mode – Command Sets and Extended Settings



Table 106: ECSD Register Access Modes

Access Bits Access Name Operation

00 Command set The command set is changed in reference to the command setfield of the argument.

01 Set bits The bits in the byte addressed by the index field in CMD6 areset in reference to the 1 bits in the value field.

10 Clear bits The bits in the byte addressed by the index field in CMD6 arecleared in reference to the 1 bits in the value field.

11 Write byte The value field is written in the byte addressed by the indexfield in CMD6.

The SWITCH (CMD6) command can be used to write to the ECSD register or to changethe command set. If the SWITCH command changes the command set, the index andvalue fields are ignored, and the ECSD register is not written to. If the SWITCH com-mand writes to the ECSD register, the command set field is ignored and the commandset remains unchanged.

The SWITCH command response is an R1b response. Therefore, to verify the result ofthe SWITCH operation, the host should use the SEND_STATUS command to read thedevice status after the busy signal is deasserted.

High-Speed Mode SelectionAfter verifying that the device complies with version 4.0 or higher of the e·MMC specifi-cation, the host is required to enable high-speed mode timing in the device. High-speedmode must be enabled before the host changes the clock frequency to a frequency high-er than 26 MHz.

After power-on or a software reset, the interface timing of the device is set as specifiedin the ECSD register. The host must enable the high-speed interface timing to change toa higher clock frequency. The host uses the SWITCH command to write 0x01 to theHS_TIMING byte in the modes segment of the ECSD register.

For this register, valid values are defined in HS_TIMING Field (Byte 185). If the host at-tempts to write an invalid value, the HS_TIMING byte is not changed, high-speed-interface timing is not enabled, and the SWITCH_ERROR bit is set.

An example of the host command token to enable high-speed timing on the bus isshown in the table below.

Table 107: Example of Host Command Token to Enable High-Speed Timingon the Bus

Bit Binary Value Comments

47 0 Start bit is always 0.

46 1 Transmitter bit = 1 for host transmission on the bus.

[45:40] 00 0110 This field is the e·MMC command.

[39:34] 00 0000 These bits are set to 0 per CMD6 definition.

[33:32] 11 Use write byte access mode for ECSD register.




Table 107: Example of Host Command Token to Enable High-Speed Timingon the Bus (Continued)


[31:24] 1011 1001 The offset address in the ECSD register for the HS_TIMING byteis 185d (B9h).

[23:16] 0000 0001 HS_TIMING byte = 01h for 52 MHz bus operation.


[10:8] 000 There is no change to the command set.

[7:1] This is the 7-bit CRC value.

0 1 End bit is always 1.

Power Class SelectionThe host can change the power class of the device after verifying that the device com-plies with version 4.0 or higher of the e·MMC specification.

After power-on or a software reset, the device power class is the default class 0. ThePWR_CL_ff_vvv bytes in the ECSD register reflect the power consumption levels of thedevice for a 4-bit bus or an 8-bit bus at the supported clock frequencies (52 MHz).

The host reads the power class selection information using the SEND_EXT_CSD(CMD8) command and determines whether the device will use a higher power class. If apower class change is necessary, the host uses the SWITCH command to write the POW-ER_CLASS byte in the modes segment of the ECSD register.

For this register, valid values are defined in “PWR_CL_DDR_ff_vvv Fields(Bytes[239:238]), PWR_CL_ff_vvv Fields (Bytes[203:200])”. If the host attempts to writean invalid value, the POWER_CLASS byte is not changed and the SWITCH_ERROR bit isset.

Bus Width SelectionThe host uses the SWITCH command to change the bus width configuration accordingly.

The bus width configuration is changed by writing a required value to the BUS_WIDTHbyte in the modes segment of the ECSD register. After power-on or a software reset, thecontents of the BUS_WIDTH byte is 0x00.

For this register, valid values are defined in “BUS_WIDTH Field (Byte 183)”. If the hosttries to write an invalid value, the BUS_WIDTH byte is not changed, and the SWITCH_ER-ROR bit is set. This is a write-only register.

Table 108: Example of Host Command Token to Switch from 1-Bit to 8-BitI/O Operation


47 0 Start bit is always 0.

46 1 Transmitter bit = 1 for host transmission on the bus.

[45:40] 00 0110 This field is the e·MMC command.





Table 108: Example of Host Command Token to Switch from 1-Bit to 8-BitI/O Operation (Continued)


[33:32] 11 Use write byte access mode for ECSD register.

[31:24] 1011 0111 The offset address in the ECSD register for the BUS_WIDTHbyte is 183d (B7h).

[23:16] 0000 0010 BUS_WIDTH bytes = 02h for 8-bit I/O operation.


[10:8] 000 There is no change to command set.

[7:1] This is the 7-bit CRC value.

0 1 End bit is always 1.

Bus Testing ProcedureBy issuing the BUSTEST_W (CMD19) and BUSTEST_R (CMD14) commands, the hostcan detect the functional pins on the bus. The host sends CMD19 to the card, followedby a specific data pattern on each selected data line. The data pattern to be sent perdata line is defined in the table below. Next, the host sends CMD14 to request the de-vice to send back the reversed data pattern. With the data pattern sent by the host andthe reversed pattern sent back by the device, the functional pins on the bus can be de-tected.

Table 109: Bus Testing Pattern

Start Bit Data Pattern End Bit

0 1 0 x x x x … x x 1

The device ignores all but the first 2 bits of the data pattern. Therefore, the device buffersize does not limit the maximum length of the data pattern. The minimum length of thedata pattern is 2 bytes, of which the first 2 bits of each data line are sent back by thedevice reversed. The data pattern sent by the host may optionally include a CRC16 check-sum, which is ignored by the device.

The device detects the start bit on DAT0 and synchronizes accordingly the reading of allits data inputs.

The host ignores all but the first 2 bits of the reverse data pattern. The length of thereverse data pattern is 8 bytes and is always sent using all the device DAT lines. See thefollowing three tables for 1-bit, 4-bit, and 8-bit bus testing patterns.

The reverse data pattern sent by the device may optionally include a CRC16 checksum,which is ignored by the host.

The device has internal pull-ups in the DAT1–DAT7 lines. In cases where the device isconnected to only a 1-bit or a 4-bit HS-MMC system, the input value of the upper bits(for example, DAT1–DAT7 or DAT4–DAT7) is detected as a logical 1 by the device.




Table 110: 1-Bit Bus Testing Pattern

Data LineData Pattern Sent

by the HostReversed Pattern Sent

by the Device Notes

DAT0 0, 10xxxxxxxxxx, [CRC16], 1 0, 01000000, [CRC16], 1 Start bit defines beginning ofpattern

DAT1 0, 00000000, [CRC16], 1 No data pattern sent










by the Device Notes


DAT1 0, 01xxxxxxxxxx, [CRC16], 1 0, 10000000, [CRC16], 1










by the Device Notes












Data Transfer Mode – Data READ OperationThe DAT[7:0] bus line levels are HIGH when no data is being transmitted. Transmitteddata consists of a start bit (LOW) on each DAT line, followed by a continuous datastream. The data stream contains the payload data. The data stream ends with an endbit (HIGH) on each DAT line.

The data transmission is synchronous with the clock signal.

The payload for a block-oriented data transfer is protected by a CRC checksum on eachDAT line.

Block ReadA block read is a block-oriented data transfer. The maximum block length is defined inthe CSD (READ_BL_LEN).

If READ_BL_PARTIAL is set, smaller blocks with starting and ending addresses con-tained entirely within one physical block (defined by READ_BL_LEN) can also be trans-mitted. A CRC is appended to the end of each block to ensure data transfer integrity.

The READ_SINGLE_BLOCK (CMD17) command initiates a block read. After the datatransfer has completed, the device returns to the transfer state.

The READ_MULTIPLE_BLOCK (CMD18) command starts a transfer of several consecu-tive blocks. Two types of multiple-block read transactions are defined. The host can useeither one at any time.

• Open-ended multiple-block read: The number of blocks for the READ_MULTI-PLE_BLOCK operation is not defined. The device continuously transfers data blocksuntil a STOP_TRANSMISSION (CMD12) command is received.

• Multiple-block read with a predefined block count: The device transfers the reques-ted number of data blocks during the READ_MULTIPLE_BLOCK operation. After thedata transfer has completed, the device returns to the transfer state. The STOP_TRANS-MISSION (CMD12) command is not required at the end of this type of multiple-blockread unless it has been terminated with an error. To start a multiple-block read with apredefined block count, the host must use the SET_BLOCK_COUNT (CMD23) com-mand immediately prior to issuing the READ_MULTIPLE_BLOCK (CMD18) com-mand. Otherwise, the device starts an open-ended multiple-block read, which can bestopped with a STOP_TRANSMISSION (CMD12) command.

Within a multiple-block operation, the host can abort reading at any time, regardless ofthe type of operation. A transaction abort is initiated by sending the STOP_TRANSMIS-SION (CMD12) command.

If any of the following conditions occur, the device rejects the command, remains in thetransfer state, and responds with the appropriate error bit set.

• The host provides an out-of-range address as an argument either to CMD17 orCMD18; ADDRESS_OUT_OF_RANGE is set.

• The currently defined block length is illegal for a read operation; BLOCK_LEN_ERRORis set.

• The address/block-length combination misaligns the first data block with respect tothe device physical blocks; ADDRESS_MISALIGN is set.

4GB, 8GB, 16GB, 32GB: e·MMCData Transfer Mode – Data READ Operation



If the device detects an error during either type of multiple-block read operation, itstops data transmission and remains in the data state. The host must then abort theoperation by sending the STOP_TRANSMISSION (CMD12) command. The read error isreported in response to the STOP_TRANSMISSION (CMD12) command.

If the host sends a STOP_TRANSMISSION command after the device transmits the lastblock of a multiple block operation with a predefined number of blocks, the commandis considered illegal because the device is no longer in the sending-data state. If the hostuses partial blocks with an accumulated length that is not block-aligned, and block mis-alignment is not supported, the device detects a block misalignment error conditionduring the transmission of the first misaligned block. The contents of further transfer-red bits are undefined. As the host sends the STOP_TRANSMISSION (CMD12) com-mand, the device responds with the ADDRESS_MISALIGN bit set and returns to thetransfer state.

The host can issue the SET_BLOCK_COUNT (CMD23) command with the argument setto all 0s. However, a subsequent read follows the open-ended multiple-block read pro-tocol. The STOP_TRANSMISSION (CMD12) command is required to complete theoperation.

After the host sends the SET_BLOCKLEN (CMD16) command to set the password for adevice exceeding a 2GB density, the host must resend CMD16 before a read data trans-fer, or the device responds with a BLK_LEN_ERROR and stays in the transfer statewithout transferring data. This is because the block size of devices exceeding a 2GB den-sity is defined in sector units of 512 bytes; this differs from the block size for thepassword setting, which is in byte units. The same error is generated for devices exceed-ing the 2GB density when partial read access is not supported.

4GB, 8GB, 16GB, 32GB: e·MMCData Transfer Mode – Data READ Operation



Data Transfer Mode – Data WRITE OperationThe data WRITE operation data transfer format is similar to the data READ format.

For block-oriented write data transfers, the CRC bits are added to each data block. Thedevice performs a CRC parity check for each data block received prior to the internalprogram operation. This mechanism can prevent the writing of erroneously transferreddata.

In general, an interruption to a WRITE process should not cause corruption in existingdata at any other address. However, the risk of power being removed during a WRITEoperation is different in different applications. Also, for some technologies used to im-plement e·MMC, there is a trade-off between protecting existing data (for example, datawritten by previously completed write operations), during a power failure, and write per-formance. When the write data reliability parameters (WR_DATA_REL_USR, WR_DA-TA_REL_1, WR_DATA_REL_2, WR_DATA_REL_3, and WR_DATA_REL_4) in theWR_REL_SET field of the ECSD register are set to 1, this indicates to the host that thewrite mechanism in the associated partition has been implemented to protect existingdata in that partition. This means that once a device indicates to the host that a WRITEhas completed successfully, the data that was written, along with all previously writtendata, cannot be corrupted by other operations that are host-initiated, controller-initi-ated, or accidental. A value of 0 for these bits indicates there is some risk to previouslywritten data in those partitions, if power is removed. This reliability setting only im-pacts the reliability of the main user area and the general purpose partitions. The datain the boot partitions and the RPMB partition must have the same reliability that is im-plied by setting the WR_DATA_REL bit to 1. The reliability of these partitions is notimpacted by the value of the WR_DATA_REL bit.

The HS_CTRL_REL bit in the ECSD register WR_REL_PARAM field indicates whetherthe bits in the WR_REL_SET register are read-only or write once. If the bits are writeonce, the host has the option of changing the reliability of the writes in one or morepartitions on the device. The entire register is considered to be write once so the hosthas one opportunity to write all the bits in the register. (Separate writes to change indi-vidual bits are not permitted.) This write must occur as part of the partitioning processand must occur before the PARTITIONING_SETTING_COMPLETED bit is set. Thechanges made to the WR_REL_SET field will not have an impact until the partitioningprocess is complete (that is, after the power cycle has occurred and the partitioning hascompleted successfully). Data reliability settings for partitions that do not exist in thedevice have no impact on the device.

All write operations must be completed in the order in which they arrive. The order re-striction is applicable to each WRITE command that a device receives and does notapply to the data within a specific write command.

Block WriteDuring block writes (CMD24–CMD27), one or more blocks of data are transferred fromthe host to the device; the host appends CRC bits to the end of each block. The maxi-mum block length is defined in the CSD register (WRITE_BL_LEN). If the CRC fails, thedevice indicates the failure on the DAT0 line. The transferred data is discarded, and allfurther blocks transmitted in multiple block write mode are ignored.

The WRITE_MULTIPLE_BLOCK (CMD25) command starts a transfer of several consec-utive blocks. Three types of multiple-block write transactions are defined; the host canuse any transaction at any time:

4GB, 8GB, 16GB, 32GB: e·MMCData Transfer Mode – Data WRITE Operation



• Open-ended multiple-block write: The number of blocks for the WRITE_MULTI-PLE_BLOCK operation is not defined. The device accepts and programs data blockscontinuously until a STOP_TRANSMISSION (CMD12) command is received.

• Multiple-block write with a predefined block count: The device accepts the reques-ted number of data blocks during the WRITE_MULTIPLE_BLOCK operation, termi-nates the transaction, and returns to the transfer state. A STOP_TRANSMISSION(CMD12) command is not required at the end of this type of multiple-block write un-less it has been terminated with an error.

To start a multiple-block write with a predefined block count, the host must send theSET_BLOCK_COUNT (CMD23) command immediately prior to sending theWRITE_MULTIPLE_BLOCK (CMD25) command. Otherwise, the device starts an open-ended multiple-block write that can only be stopped by using the STOP_TRANSMIS-SION (CMD12) command.

• Reliable write: A WRITE_MULTIPLE_BLOCK operation with a predefined block countand reliable write parameters. This transaction is similar to a multiple-block writewith a predefined block count, with the following two exceptions: 1) The old data poin-ted to by a logical address must remain unchanged until the new data written to thesame logical address has not been successfully programmed. This ensures that thetarget address updated by the reliable write transaction never contains undefined da-ta; and 2) Data must remain valid even if a sudden power loss occurs during theprogramming.

There are two versions of reliable write: legacy implementation and enhanced imple-mentation. The EN_REL_WR bit in the WR_REL_PARAM field of the ECSD registerindicates the version of reliable write supported by the device.

For the case of EN_REL_WR = 0:

– Two different sizes of reliable write transactions are supported: 512 bytes and thereliable write sector count parameter in ECSD register byte 222 (REL_WR_SEC_C) mul-tiplied by 512 bytes.

– A reliable write is enabled by setting the reliable write request parameter (bit 31) to 1in the SET_BLOCK_COUNT (CMD23) command argument. The reliable write sectorcount parameter in the ECSD register indicates the supported write sector count.

– A reliable write is only possible when: the length of the WRITE_MULTIPLE_BLOCKoperation equals the supported reliable write size or 512 bytes; the start address of theWRITE_MULTIPLE_BLOCK operation is aligned to the length of the operation (thatis, the reliable write start address is always a multiple of its own length); and the relia-ble write request is active. Otherwise, the transaction is handled as a basic predefinedmultiple-block scenario. When the length of the WRITE_MULTIPLE_BLOCK opera-tion is set to 0, the operation is executed as a basic, open-ended multiple-block write,even when the reliable write request is active.

For the case of EN_REL_WR = 1:

– The block size defined by the SET_BLOCKLEN (CMD16) command is ignored andall blocks are 512 bytes in length. There is no limit on the size of the reliable write.

– The function is activated by setting the reliable write request parameter (bit 31) to 1in the SET_BLOCK_COUNT (CMD23) command argument.

– Reliable write transactions must be sector-aligned; if a reliable write is not sector-aligned, the error bit 19 will be set and the transaction will not complete.




– If a power loss occurs during a reliable write, each sector being modified by thewrite is atomic. After a power failure, sectors may contain either old data or new data.All the sectors being modified by the WRITE operation that was interrupted may be inone of the following states: all sectors contain new data; all sectors contain old data;or some sectors contain new data and some sectors contain old data.

– In the case where a reliable write is interrupted by a high-priority interrupt opera-tion, the sectors that the register marks as completed will contain new data and theremaining sectors will contain old data.

– ECSD register byte 222 (REL_WR_SEC_C) should be set to 1 and has no impact onthe reliable write.

The host can abort writing at any time within a multiple-block operation, regardless ofits type. Transactions are aborted by sending the STOP_TRANSMISSION command. If aWRITE_MULTIPLE_BLOCK command with predefined block count is aborted, the datain the remaining blocks is not defined.

If any of the following conditions occurs, the device rejects the command, remains inthe transfer state, and responds with the appropriate error bit set.

• The host provides an out-of-range address as an argument to WRITE_BLOCK(CMD24) or WRITE_MULTIPLE_BLOCK (CMD25); ADDRESS_OUT_OF_RANGE is set.

• The currently defined block length is illegal for a write operation; BLOCK_LEN_ER-ROR is set.

• The address/block length combination misaligns the first data block with respect tothe device physical blocks; ADDRESS_MISALIGN is set.

If the device detects an error (for example, a write-protect violation, an out-of-rangeerror, an address misalignment, or an internal error) during a WRITE_MULTI-PLE_BLOCK operation, the device ignores any incoming data blocks internally andremains in the receive data state.

The host must then abort the operation by sending the STOP_TRANSMISSION com-mand. A write error is reported in response to the STOP_TRANSMISSION command.

If the host sends a STOP_TRANSMISSION (CMD12) command after the device receivesthe last data block of a WRITE_MULTIPLE_BLOCK operation with a predefined numberof blocks, it is regarded as an illegal command because the device is no longer in thereceive data state.

If block misalignment is not permitted (CSD parameter WRITE_BLK_MISALIGN is notset), the host uses partial blocks for a WRITE operation, and the accumulated blocklength is not aligned with a block boundary, the device detects the block misalignmenterror upon receiving the first misaligned block. After detecting the error, the deviceaborts the WRITE operation and ignores all further incoming data. When the host sendsthe STOP_TRANSMISSION (CMD12) command, the device responds with the AD-DRESS_MISALIGN bit set and returns to the transfer state.

The host can issue the SET_BLOCK_COUNT (CMD23) command with the argument setto all 0s. However, a subsequent write follows the open-ended multiple-block write pro-tocol, so the STOP_TRANSMISSION (CMD12) command is required to complete theoperation.

Programming the CID and CSD registers does not require a previous block length set-ting. The transferred data is CRC-protected. If a part of the CSD or CID register is stored




in ROM, this part must match the corresponding part in the receive buffer. If this matchfails, the device reports an error and does not change any register contents.

Some devices require long or unpredictable times to write blocks of data. After receivinga block of data and completing the CRC, the device begins writing and holds the DAT0line LOW if the write buffer is full and unable to accept new data. The host can poll thestatus of the device with a SEND_STATUS (CMD13) command any time during any sta-tus in data transfer mode, other than during the sleep state. The device responds withits status. The READY_FOR_DATA status bit indicates whether the write process is stillin progress or whether the device can accept new data. The host can deselect the deviceby issuing the SELECT/DESELECT_CARD (CMD7) command. CMD7 places the deviceinto the disconnect state and releases the DAT0 line without interrupting the WRITEoperation. When the host reselects the device, if programming is still in progress andthe write buffer is unavailable, the device reactivates the busy indicator by taking DAT0LOW.

After the host sends the SET_BLOCKLEN (CMD16) command to set the password for adevice exceeding a 2GB density, the host must resend CMD16 before a read data trans-fer, or the device responds with a BLK_LEN_ERROR and remains in the transfer statewithout transferring data. This is because the block size of a device exceeding 2GB indensity is defined in sector units of 512 bytes; this differs from the block size for thepassword setting, which is in bytes.




Data Transfer Mode – ERASE OperationThe device provides the host with an explicit erase function, even though it executes anERASE operation as part of the WRITE operation. Erasable units are referred to as erasegroups. Erase groups are measured in write blocks—the basic writable units of the de-vice. The size of an erase group is a device-specific parameter and is defined in the CSDregister. The contents of an explicitly erased memory range is 0 or 1, depending on thememory technology in use. The value to be used for a given device is defined in theECSD register.

The host can erase a contiguous range of erase groups. Starting an ERASE operationrequires a three-step sequence:

1. The host defines the start address of the range using the ERASE_GROUP_START(CMD35) command.

2. The host defines the last address of the range using the ERASE_GROUP_END(CMD36) command.

3. The host issues the ERASE (CMD38) command, with argument bits set to 0, start-ing the erase process. See the following table for valid arguments supported byCMD38.

The address field in CMD35 or CMD36 is an erase group address in bytes for densitiesup to 2GB and in sectors for densities greater than 2GB. The device ignores least signifi-cant bits smaller than the erase group size, effectively rounding the address down to theerase group boundary.

If CMD35, CMD36, or CMD38 is received out of the defined erase sequence, the devicesets the ERASE_SEQ_ERROR bit in the status register and resets the entire sequence.

If the host provides an out-of-range address as an argument to CMD35 or CMD36, thedevice rejects the command, responds with the ADDRESS_OUT_OF_RANGE bit set,and resets the entire erase sequence.

If a command other than these ERASE commands is received, the device responds withthe ERASE_RESET bit set, resets the erase sequence, and executes the last command.Commands not addressed to the selected device will not abort the erase sequence.

If the erase range includes write-protected blocks, these blocks are left intact, and onlythe unprotected blocks are erased. The WP_ERASE_SKIP status bit in the status registeris set.

During an ERASE operation, the device indicates that an erase is in progress by holdingDAT0 LOW. The actual erase time can be quite long, and the host can issue the SELECT/DESELECT_CARD (CMD7) command to deselect the device.

4GB, 8GB, 16GB, 32GB: e·MMCData Transfer Mode – ERASE Operation



Table 113: ERASE Command Valid Arguments

Argument Command Description

SEC_GB_CL_EN(ECSD Register Byte

231, Bit 4)

SEC_ER_EN(ECSD Register Byte

231, Bit 0)

0x00000000 ERASE: Erase the erase groups identified byCMD35 and CMD36. Controller can perform actualerase at a convenient time. (legacy implementa-tion)

n/a n/a

0x80000000 SECURE ERASE: Performs a SECURE PURGE1 on theerase groups identified by CMD35 and CMD36and any copies of those erase groups.

n/a Required

0x80008000 SECURE TRIM Step 2: Performs a SECURE PURGE1

operation on the write blocks and copies of thosewrite blocks that were previously identified usingCMD35, CMD36, and CMD38 with an argument of0x80000001.

Required Required

0x00000001 TRIM: Erases the write blocks identified by CMD35and CMD36. The controller can perform the actualerase at a convenient time.

Required n/a

0x80000001 SECURE TRIM Step 1: Marks the write blocks, indi-cated by CMD35 and CMD36, for SECURE ERASE.

Required Required

Note: 1. The process of overwriting all the addressable locations within an identified range witha single character and then performing an ERASE on those same locations.

Table 114: ERASE Command Comparison

Operation

Minimum

Unit Size

BasicOperation(s)Required by

the ControllerImpacts All

Copies of Data

All CopiesMust Be

Removed

Operation TimingDetermined bythe Controller

SECURE ERASE Erase Group ERASE Yes Yes –ERASE Erase Group ERASE – – Yes

SECURE TRIM Write Block WRITE and ERASE1 Yes Yes –TRIM Write Block WRITE and ERASE1 – – Yes

Note: 1. Since the minimum size for an ERASE operation is an erase group and a write block issmaller than an erase group. The TRIM operation implies that write blocks in an erasegroup that are not marked for erasure must be copied by the controller to another loca-tion before the ERASE operation is applied.




When executing an ERASE command or an ERASE command with a SECURE argument,the host should be aware that an erase group contains multiple write blocks, whichcould each contain different pieces of information. When an ERASE/SECURE ERASEcommand is executed, it applies to all write blocks within an erase group. Before thehost executes the command, it should ensure that the information in the individualwrite blocks is no longer required. To avoid the accidental deletion of valid data, theERASE command is best used to erase the entire device or a partition within the device.If the host wants to purge only a single write block, performing a TRIM or SECURETRIM operation might be more appropriate.




Data Transfer Mode – SECURE ERASE OperationIn addition to the basic ERASE command, the ERASE command can be used with a SE-CURE argument. The SECURE ERASE command differs from the basic ERASE com-mand in that it requires the device to execute the ERASE operation on the memoryarray when the command is issued and requires the device and host to wait until theoperation is complete before moving to the next operation. Also, the SECURE ERASEcommand requires the device to perform a SECURE PURGE operation on the erasegroups, and any copies of items in those erase groups, identified for erasure.

This command enables applications that have high security requirements to requestthe device to perform SECURE operations, while accepting a possible erase time per-formance impact.

The SECURE ERASE command is executed the same way as the ERASE command out-lined in the Erase Operations section, except that the ERASE command (CMD38) isexecuted with argument bit 31 set to 1 and the other argument bits set to 0. For detailson the argument combinations supported with the ERASE command, see Data TransferMode – ERASE Operation. For definitions of the argument bits associated with theERASE command, see the table below.

The host should execute the SECURE ERASE command with caution to avoid uninten-tional data loss.

If a device is reset with CMD0, CMD15, or assertion of the RST_n signal, or if a powercycle occurs, any pending or active SECURE ERASE command is terminated. This mayleave the data involved in the operation in an unknown state.

Table 115: ERASE Command Argument Definitions

Bit Argument Definition

31 Secure Request 0 = Insecure form of the command is performed (default).1 = Secure form of the command is performed.

15 Force Garbage Collect 0 = Command uses the erase groups identified by CMD35 and CMD36.1 = CMD35 and CMD36 are ignored. ERASE is performed on previouslyidentified write blocks.

0 Identify Write Blocks for Erase 0 = Execute an erase.1 = Mark write block identified by CMD35 and CMD36 for erase (bit 1set) or execute TRIM operation (bit 31 cleared).

4GB, 8GB, 16GB, 32GB: e·MMCData Transfer Mode – SECURE ERASE Operation



Data Transfer Mode – TRIM OperationThe TRIM operation is similar to the default ERASE operation described in the ERASEOperation section. The TRIM operation applies the ERASE operation to write blocks in-stead of erase groups. The TRIM function allows the host to identify data that is nolonger required so that the device can erase the data, if necessary, during backgrounderase events. The contents of a write block where the TRIM function has been applied is0 or 1, depending on the memory technology. This value is defined in the ECSD register.

The TRIM operation is completed in a three-step sequence:1. The host defines the start address of the range using the ERASE_GROUP_START

(CMD35) command.2. The host defines the last address of the range using the ERASE_GROUP_END

(CMD36) command.3. The host starts the ERASE process by issuing the ERASE (CMD38) command with

argument bit 0 set to 1 and the remainder of the arguments set to 0. During aTRIM operation, both CMD35 and CMD36 identify the addresses of write blocks,rather than erase groups.

If a command element of the TRIM operation (CMD35, CMD36, CMD38) is received outof the defined erase sequence, the device sets the ERASE_SEQ_ERROR bit in the statusregister and resets the whole sequence.

If the host provides an out-of-range address as an argument to CMD35 or CMD36, thedevice rejects the command, responds with the ADDRESS_OUT_OF_RANGE bit set,and resets the whole erase sequence.

If a non-erase command is received (a command that is not CMD35, CMD36, CMD38,or CMD13), the device responds with the ERASE_RESET bit set, resets the erase se-quence, and executes the last command. Commands not addressed to the selecteddevice will not abort the erase sequence.

If the TRIM operation range includes write-protected blocks, they are left intact and on-ly the non-protected blocks are erased. The WP_ERASE_SKIP status bit in the statusregister is set.

As described for a block write, the device indicates that a TRIM command is in progressby holding DAT0 LOW. The actual erase time may be quite long, and the host may issuethe SELECT/DESELECT_CARD (CMD7) command to deselect the device.

The TRIM command should be executed with caution to avoid unintentional data loss.

If a device is reset with CMD0, CMD15, or assertion of the RST_n signal, or if a powercycle occurs, any pending or active TRIM command is terminated. This may leave thedata involved in the operation in an unknown state.

4GB, 8GB, 16GB, 32GB: e·MMCData Transfer Mode – TRIM Operation



Data Transfer Mode – SECURE TRIM OperationThe SECURE TRIM operation is very similar to the SECURE ERASE operation. The SE-CURE TRIM operation performs a SECURE PURGE on write blocks instead of erasegroups.

To minimize the impact on the device’s performance and reliability, the SECURE TRIMoperation is completed by performing two steps:

1. The host defines the range of write blocks to be marked for the SECURE PURGE.This step does not perform the actual purge operation. The blocks are marked bythe start address of the block range defined by the argument for theERASE_GROUP_START (CMD35) command and the end address of the blockrange defined by the argument for the ERASE_GROUP_END (CMD36) command.After a range of blocks is identified, the ERASE (CMD 38) command is executedwith argument bits 31and 0 set to 1, and the remainder of the argument bits set to0 (see Data Transfer Mode – ERASE Operation for the valid arguments). This stepcan be repeated several times, with other commands between the steps, until allthe write blocks that need to be purged have been identified. It is recommendedthat this step be performed on as many blocks as possible to improve the efficien-cy of the SECURE TRIM operation.

2. The ERASE_GROUP_START (CMD35) and ERASE_GROUP_END (CMD36) com-mands are issued with block addresses that are in range. The arguments used withthese commands are ignored. Then, the ERASE (CMD 38) command is sent withbits 31 and 15 set to 1 and the remainder of the argument bits set to 0. This stepactually performs a SECURE PURGE on all the write blocks, as well as any copiesof those blocks that were marked during step 1, and completes the SECURE TRIMoperation. Other commands can be issued to the device between steps 1 and 2.

The host may perform step 2 of the SECURE TRIM operation without performing step 1.This may be required after a power cycle event in order to complete unfinished SE-CURE TRIM operations. If step 2 is performed, and there are no write blocks marked forerasure, then step 2 has no impact on the device.

Once a write block is marked for erasure in step 1, the host should consider this blockerased. However, if the host writes to a block after it has been marked for erasure, thenthe last copy of the block, which occurred as a result of the modification, is not markedfor erasure. All previous copies of the block remain marked for erasure.

If the host application wishes to use the SECURE TRIM operation as the method to re-move data from the device, then the host should ensure that it completes step 1 of theSECURE TRIM operation for a write block before using a write command to overwritethe block. This ensures that the overwritten data is removed securely from the devicethe next time step 2 of the SECURE TRIM operation is performed.

If CMD35, CMD36, or CMD38 is received out of the defined erase sequence, the devicesets the ERASE_SEQ_ERROR bit in the status register and resets the whole sequence foran individual step.

If the host provides an out-of-range address as an argument to CMD35 or CMD36, thedevice rejects the command, responds with the ADDRESS_OUT_OF_RANGE bit set,and resets the whole erase sequence.

If a non-erase command is received (a command that is not CMD35, CMD36, CMD38,or CMD13), while the device is performing step 1 or step 2 of the SECURE TRIM opera-tion, the device responds with the ERASE_RESET bit set, resets the step without complet-

4GB, 8GB, 16GB, 32GB: e·MMCData Transfer Mode – SECURE TRIM Operation



ing the SECURE TRIM operation, and executes the last command. Commands notaddressed to the selected device will not abort the sequence. Other commands may oc-cur between multiple iterations of step 1 of the SECURE TRIM operation and/or beforestep 2 of the SECURE TRIM operation has begun. However, the sequence of routinesperformed during the execution of the SECURE TRIM steps cannot be interrupted.

If a power cycle occurs or the RST_n signal is asserted between steps 1 and 2, the blocksthat were identified for the SECURE_TRIM operation remain marked. The next time thedevice detects step 2 of the SECURE_TRIM operation, it purges the blocks that weremarked prior to the power cycle or assertion of the RST_n signal, along with any blocksthat were identified after that event.

The SECURE TRIM command should be executed with caution to avoid unintentionaldata loss.

If a device is reset with CMD0, CMD15, or assertion of the RST_n signal, or if a powercycle occurs during step 1 or step 2, any pending or active command is terminated. Thismay leave the data involved in the operation in an unknown state.

If the erase range includes write-protected blocks, they are left intact and only the non-protected blocks are erased. The WP_ERASE_SKIP status bit in the status register is set.

If the device needs a write block that is marked for SECURE TRIM, and step 2 of theSECURE TRIM operation has not begun, the device can initiate a SECURE PURGE oper-ation internally on that write block as a background task before the command for step 2of the SECURE TRIM operation is received.

During the operation, the device indicates that step 1 or step 2 is in progress by holdingDAT0 LOW. The actual time for the operation may be quite long, and the host may issueCMD7 to deselect the device.

If the write block size is changed between steps 1 and 2 of the SECURE TRIM operation,then the write block size used during step 1 of the operation applies.

4GB, 8GB, 16GB, 32GB: e·MMCData Transfer Mode – SECURE TRIM Operation



Data Transfer Mode – Write-Protect ManagementThe device supports two levels of write protection so that the host can protect dataagainst erase or write commands:

• The entire device (including the boot area partitions, general-purpose area partition,RPMB, and user/enhanced user data area partition) may be write-protected by set-ting the permanent or temporary write-protect bits in the CSD register. When perma-nent protection is applied to the entire device, it overrides all other protectionmechanisms currently enabled in the entire device or in a specific segment of the de-vice. CSD register bits and ECSD register bits are not impacted by this protection.When temporary write protection is enabled for the entire device, it applies only tothose segments that are not already protected by another mechanism (see the follow-ing table for details).

• Specific segments of the devices may be permanently, power-on, or temporarily write-protected. ERASE_GROUP_DEF in the ECSD register decides the segment size. Whenset to 0, the segment size is defined in units of WP_GRP_SIZE erase groups, as speci-fied in the CSD register. When set to 1, the segment size is defined in units ofHC_WP_GRP_SIZE erase groups, as specified in the ECSD register. If the host doesnot set the ERASE_GROUP_DEF bit for a device in which high-capacity write protec-tion has been set in some area during the previous power cycle, the device mayexhibit unknown behavior when the host issues write or erase commands to the de-vice. This is because the write-protect group size set previously does not match thecurrent write-protect group size. Similarly, if the host sets the ERASE_GROUP_DEFbit for a device in which default write protection has already been set in some areaduring the previous power cycle, the device may exhibit unknown behavior when thehost issues write or erase commands to the device. The host must use the sameERASE_GROUP_DEF value for the device after every power-on.

• The SET_WRITE_PROT command sets the write protection of the addressed write-pro-tect group to the type of write protection dictated by ECSD register byte 171, bit 2(US_PERM_WP_EN) and ECSD register byte 171, bit 0 (US_PWR_WP_EN). For the re-sult of the SET_WRITE_PROT (CMD28) command, when protection is already ena-bled in a segment, see the following table. For the impact of the differentcombinations of the protection enable bits, see the table Write Protection Types (Dis-able Bits Cleared). The CLR_WRITE_PROT (CMD29) command clears the temporarywrite protection of the addressed write-protect group. If CMD29 is issued to a write-protect group that has either permanent or power-on write protection, then thecommand fails.

The ability of the host to set permanent protection for the entire device and permanentand power-on protection for specific device segments can be disabled by setting theCD_PERM_WP_DIS, US_PERM_WP_DIS, and US_PWR_WP_DIS bits in ECSD registerbyte 171 (USER_WP). It is recommended that all protection modes that are not requiredto prevent unused write protection modes from being set maliciously or unintentional-ly, be disabled.

The host can check the write protection status of a given segment or segments by usingthe SEND_WRITE_PROT_TYPE (CMD31) command. When full device protection is ena-bled, all the segments are shown as having permanent protection.

The SEND_WRITE_PROT (CMD30) and SEND_WRITE_PROT_TYPE (CMD31) com-mands are similar to a READ_SINGLE_BLOCK (CMD17) command. The device sends adata block containing 32 or 64 write-protect bits (representing 32 write-protect groups

4GB, 8GB, 16GB, 32GB: e·MMCData Transfer Mode – Write-Protect Management



starting at the specified address), followed by 16 CRC bits. The address field in the write-protect commands is a group address in byte units for densities up to 2GB, and insector units for densities greater than 2GB. The device ignores all LSBs below the writegroup size.

If the host provides an out-of-range address as an argument to SET_WRITE_PROT(CMD28), CLR_WRITE_PROT (CMD29), or SEND_WRITE_PROT (CMD30), the devicerejects the command, sets the ADDRESS_OUT_OF_ RANGE bit, and remains in the trans-fer state.

Table 116: Write Protection Hierarchy (disable bits cleared)

CurrentProtection Mode CSD[12] Action

ResultingProtection Mode

Permanent n/a Power cycle or assertion of RST_n signal Permanent

Permanent n/a SET_WRITE_PROT (US_PERM_WP_EN = 0) Permanent

Power-On 1 Power cycle or assertion of RST_n signal Temporary

Power-On 0 Power cycle or assertion of RST_n signal None

Power-On n/a SET_WRITE_PROT (US_PERM_WP_EN = 1) Permanent

Power-On n/a SET_WRITE_PROT (US_PERM_WP_EN = 0 andUS_PWR_WP_EN = 0)

Power-On

Temporary 1 Power cycle or assertion of RST_n signal Temporary

Temporary 1 SET_WRITE_PROT (US_PERM_WP_EN = 1) Permanent

Temporary 1 SET_WRITE_PROT (US_PERM_WP_EN = 0 andUS_PWR_WP_EN = 1)

Power-On

Table 117: Write Protection Types (disable bits cleared)

US_PERM_WP_EN US_PWR_WP_ENType of Protection Set by

SET_WRITE_PROT Command

0 0 Temporary

0 1 Power-On

1 0 Permanent

1 1 Permanent

4GB, 8GB, 16GB, 32GB: e·MMCData Transfer Mode – Write-Protect Management



Data Transfer Mode – LOCK/UNLOCK OperationsThe password-protection feature enables the host to lock the device by providing a pass-word to unlock the device. The password and its size are kept in a 128-bit PWD registerand an 8-bit PWD_LEN register. These registers are nonvolatile; a power cycle does noterase them.

The password-protection feature can be disabled permanently by setting bit 7 in ECSDregister byte 171 (PERM_PSWD_DIS). If the host attempts to permanently disableCMD42 features on a device with a password set, the action fails and the device sets theERROR bit (19) in the card status register. It is recommended that the password-protec-tion feature on the device be disabled, if it is not required, to prevent it being setunintentionally or maliciously.

If the host issues the LOCK_UNLOCK (CMD42) command to a device with the pass-word permanently disabled, the LOCK_UNLOCK_FAILED error bit is set in the statusregister.

A locked device responds to, and executes, all commands in the basic command class(class 0) and lock card command class (class 7). Thus, the host is able to reset, initialize,select the device, and query the device for status; the host cannot access data on alocked device. If the password was previously set (the value of PWD_LEN is not 0), thedevice is automatically locked after power-on.

On v4.3 and later devices, the LOCK command can only be applied to the user dataarea. So, the host can still access the boot partitions, RPMB, and general partition areasafter the LOCK command is issued to the device.

Similar to the existing CSD and CID register write commands, the LOCK_UNLOCK(CMD42) command is available only in the transfer state. Also, CMD42 does not includean address argument, so the device must be selected before the host issues CMD42.

Structure and bus transaction types are the same for the LOCK_UNLOCK (CMD42) andthe WRITE_BLOCK (CMD24) commands. The data structure includes all the informa-tion the device requires to execute the LOCK_UNLOCK operation (such as passwordsetting, the password itself, and the LOCK_UNLOCK command issued to the device).

The device LOCK_UNLOCK (CMD42) command can be performed only when the de-vice operates in single data rate mode. CMD42 is an illegal command in dual data ratemode.

The data block size is defined by the host before it sends the LOCK_UNLOCK com-mand. This supports different password sizes.

4GB, 8GB, 16GB, 32GB: e·MMCData Transfer Mode – LOCK/UNLOCK Operations



Table 118: LOCK/UNLOCK Data Structure

Byte# Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 Reserved ERASE LOCK_UNLOCK CLR_PWD SET_PWD

1 PWD_LEN

2 Password data

···

PWD_LEN + 1

Table 119: LOCK/UNLOCK Data Descriptions

Byte#/Bit# Field Value Description

0/[7:4] Reserved

0/3 ERASE 0 No ERASE operation occurs.

1 Defines a forced ERASE operation; all other bits must be 0 and onlythe command byte is sent.

0/2 LOCK_UNLOCK 0 Unlocks the device. Setting this bit together with setting SET_PWD isvalid; setting it together with setting CLR_PWD is invalid.

1 Locks the device. Setting this bit together with setting SET_PWD is val-id; setting it together with setting CLR_PWD is invalid.

0/1 CLR_PWD 0 Retains the device password.

1 Clears the device password.

0/0 SET_PWD 0 Does not set the new password.

1 Sets the new password to PWD.

1/[7:0] PWD_LEN 1–16 Defines the password length that follows (in bytes). Valid passwordlengths are 1 to 16 bytes.

≥2/[7:0] Password data The password (new or currently used, depending on the command)




LOCK/UNLOCK Command SequencesThe following sections define the various lock/unlock command sequences.

Setting the Password1. If the device is not already selected, send the SELECT/DESELECT_CARD (CMD7)

command to select the device.2. Send the SET_BLOCKLEN (CMD16) command to define the block length given by

the 1-byte device lock/unlock mode, the 1-byte password size, and the number ofbytes used for the new password. If a password replacement is initiated, the blocksize must accommodate both passwords, the old and the new, because both aresent with the command.

3. Send the LOCK_UNLOCK (CMD42) command on the data line, with the appropri-ate data block size, including the 16-bit CRC. The data block indicates the mode(SET_PWD), the password length (PWD_LEN), and the password (PWD) itself.When a password replacement is made, the password length value (PWD_LEN)must include both passwords, the old and the new, and the PWD field must in-clude the old password (currently used), followed by the new password.

When a password replacement is attempted with PWD_LEN set to the length of the oldpassword only, the LOCK_UNLOCK_FAILED error bit is set in the status register, andthe old password is not changed.

When the old password sent is incorrect (not equal in size and content), the LOCK_UN-LOCK_FAILED error bit is set in the status register, and the old password is notchanged. When PWD matches the old password sent, the new password and its size aresaved in the PWD and PWD_LEN fields, respectively.

Note that the password length register (PWD_LEN) indicates whether a password is cur-rently set. When PWD_LEN is 0, no password is set. If the value of PWD_LEN is not 0,the device locks itself following power-on. It is possible to lock the device during thecurrent power session (without powering down) by setting the LOCK/UNLOCK bitwhile setting the password or sending another LOCK_UNLOCK command to lock thedevice.

Resetting the Password1. If the device is not already selected, send the SELECT/DESELECT_CARD (CMD7)


the 1-byte device lock/unlock mode, the 1-byte password size, and the number ofbytes used for the current password.

3. Send the LOCK_UNLOCK (CMD42) command on the data line, with the appropri-ate data block size, including the 16-bit CRC. The data block indicates the mode(CLR_PWD), the password length (PWD_LEN), and the password (PWD) itself (andthe LOCK/UNLOCK bit is “Don’t Care”). If the PWD and PWD_LEN content matchthe sent password and its size, the content of the PWD register is cleared, andPWD_LEN is set to 0. If the password is incorrect, the LOCK_UNLOCK_FAILED er-ror bit is set in the status register.




Locking the Device1. If the device is not already selected, send the SELECT/DESELECT_CARD (CMD7)


the 1-byte device lock/unlock mode, the 1-byte password size, and the number ofbytes used for the current password.

3. Send the LOCK_UNLOCK (CMD42) command on the data line, with the appropri-ate data block size, including the 16-bit CRC. The data block includes the LOCK bitset to 1, the password length (PWD_LEN), and the password (PWD) itself.

If the PWD content matches the sent password, the device is locked, and the devicelocked status bit is set in the status register. If the password is incorrect, the LOCK_UN-LOCK_FAILED error bit is set in the status register. Note that it is possible to set thepassword and lock the device in the same sequence. To do this, the host must completeall the required steps for setting the password, including setting the LOCK bit when thenew password command is sent.

If the password was previously set (PWD_LEN is not 0), the device is locked automatical-ly following the power-on reset. Attempts to lock a locked device or to lock a device thatdoes not have a password will fail, and the LOCK_UNLOCK_FAILED error bit will be setin the status register.

Unlocking the Device1. If the device is not already selected, send the SELECT/DESELECT_CARD (CMD7)

command to select the device.2. Send the SET_BLOCKLEN (CMD16) command to define the block length (CMD16)

given by the 1-byte device lock/unlock mode, the 1-byte password size, and thenumber of bytes used for the current password.

3. Send the LOCK_UNLOCK (CMD42) command on the data line, with the appropri-ate data block size including the 16-bit CRC. The data block includes the unlockmode, the password length (PWD_LEN), and the password (PWD) itself.

If the PWD content matches the sent password, the device is unlocked, and the devicelocked status bit is cleared in the status register. If the password is incorrect, theLOCK_UNLOCK_FAILED error bit is set in the status register.

Note that unlocking applies only for the current power session. As long as the PWD bitis not cleared, the device is locked automatically on the next power-on. The only way tounlock the device is to clear the password.

An attempt to unlock an unlocked device will fail, and the LOCK_UNLOCK_FAILED er-ror bit will be set in the status register.




Forcing an Erase

If the user forgets the password (the PWD content), it is possible to erase all the datacontent in the device along with the PWD content. This is a FORCED ERASE operation.

1. If the device is not already selected, send the SELECT/DESELECT_CARD (CMD7)command to select the device.

2. Send the SET_BLOCKLEN (CMD16) command to define the block length (CMD16)to 1 byte (8-bit device lock/unlock command).

3. Send the LOCK_UNLOCK (CMD42) command on the data line, with the appropri-ate 1-byte block data, including the 16-bit CRC. The data block indicates the erasemode (the erase bit is the only bit set).

If the ERASE bit is not the only bit in the data field, the LOCK_UNLOCK_FAILED errorbit is set in the status register, and the erase request is rejected.

If the command is accepted, all the device contents are erased, including the PWD andPWD_LEN register content, and the locked device is unlocked. In addition, if the deviceis temporarily write protected, it is unprotected (write enabled); the temporary writeprotect bit in the CSD register and all write protect groups are cleared.

An attempt to perform a FORCED ERASE operation on an unlocked device will fail, andthe LOCK_UNLOCK_FAILED error bit will be set in the status register.

If a FORCED ERASE is performed on permanently write-protected media, the LOCK_UN-LOCK command will fail, the device will stay locked, and the LOCK_UNLOCK_FAILEDerror bit will be set in the status register.

On v4.3 and later devices, when the host performs a FORCED ERASE operation, onlythe data stored in the user data area (including the enhanced attribute area) will beerased. The FORCED ERASE operation will not be applied to the boot, RPMB, and gen-eral partition areas.




Data Transfer Mode – SLEEP/AWAKE OperationsA device can be switched between a sleep state and a standby state by issuing theSLEEP_AWAKE (CMD5) command. In the sleep state, the power consumption of thedevice is minimized. In this state, the device responds only to a reset (CMD0) commandwith an argument of either 0x00000000 or 0xF0F0F0F0, or assertion of the RST_n signal,and the SLEEP_AWAKE (CMD5) command. All the other commands are ignored by thedevice. The timeout for state transitions between the standby state and sleep state isdefined in ECSD register byte 217 (S_A_TIMEOUT). The maximum current consump-tions during the sleep state are defined in the ECSD register byte 220 (S_C_VCC) andbyte 221 (S_C_VCCQ).

• SLEEP command: Bit 15 is set to 1 in the sleep/awake argument of the SLEEP_AWAKE(CMD5) command.

• AWAKE command: Bit 15 is set to 0 in the sleep/awake argument of theSLEEP_AWAKE (CMD5) command.

The SLEEP command initiates the state transition from the standby state to the sleepstate. The device indicates busy during the transition phase by pulling down the DAT0line. No further commands should be sent during the busy period. The sleep state isreached when the device stops pulling down the DAT0 line.

The AWAKE command initiates the transition from the sleep state to the standby state.The device indicates busy during the transition phase by pulling down the DAT0 line.No further commands should be sent during the busy period. The standby state isreached when the device stops pulling down the DAT0 line.

The transition from the standby state to the sleep state may be canceled by the AWAKEcommand. The response should include the current target state information (slp). Thetransition from the sleep state to the standby state may be canceled by the SLEEP com-mand. The response should include the current target state information (stby).

During the sleep state, the VCC power supply may be switched off. This enables furthersystem power consumption savings. The VCC supply can be switched off only after thesleep state has been reached (the device has stopped pulling down the DAT0 line). TheVCC supply must be ramped to at least the minimum operating voltage level before thestate transition from the sleep state to the standby state can be initiated (AWAKE com-mand).

A locked device can be placed into the sleep state by first deselecting the device throughthe SELECT/DESELECT_CARD (CMD7) command, which is a Class 0 command thatcan be executed in the locked state, and then issuing the SLEEP command. This enablesthe device to reduce power consumption while it is locked. When the AWAKE com-mand is issued to the locked device, the device exits the sleep state and enters a standbystate.

The reverse sequence, locking the device after it has already entered the sleep state, isnot allowed.

4GB, 8GB, 16GB, 32GB: e·MMCData Transfer Mode – SLEEP/AWAKE Operations



Data Transfer Mode – RPMBA signed access to a replay-protected memory block (RPMB) is provided. This functionprovides a means for the system to store data to the specific memory area in an authen-ticated and replay-protected manner. This function is enabled by first programmingauthentication key information into the e·MMC memory.

Because the system cannot be authenticated yet in this phase, authentication key pro-gramming must take place in a secure environment. Later on, the authentication key isused to sign the read and write accesses made to the replay-protected memory areawith a message authentication code (MAC).

Use of random number generation and a count register provides additional protectionagainst the replay of messages where messages could be recorded and played back laterby an attacker.

RPMB Access Data FrameThe data frame to access the replay-protected memory block includes the data fieldsshown in the following table.

Table 120: RPMB Access Data Frame

StartStuffBytes

Key/MAC Data Nonce

WriteCounter Address

BlockCount

OpResult

Req/Resp CRC16 End

1 bit 196bytes

32bytes

256bytes

16bytes

4bytes

2bytes

2bytes

2bytes

2bytes

2bytes

1 bit

– [511:316] [315:284] [283:28] [27:12] [11:8] [7:6] [5:4] [3:2] [1:0] – –

The byte order of the RPMB access data frame is MSB first. For example, the MSB ofWrite Counter (byte 11) stores the uppermost byte of the counter value.

Table 121: RPMB Access Data Frame Field Descriptions

Field Direction Description

Start n/a Start bit.

Stuff Bytes n/a Stuff bytes are filled with 0s.

Key/MAC(Authentication Key/Message AuthenticationCode)

Request (key or MAC)/Re-sponse (MAC)

The authentication key or the message authentication code(MAC) depending on the request/response type. The MAC is de-livered in the last (or the only) block of data.

Data Request and response Data to be written or read by signed access.

Nonce Request and response Random number generated by the host for the requests and cop-ied to the response by the e·MMC RPMB engine.

Write Counter Request and response Counter value for the total number of successfully authenticateddata write requests made by the host.

Address(Data Address)

Request and response Address of the data to be programmed to or read from theRPMB. Address is the serial number of the accessed half-sector(256 bytes). The address argument in CMD18 and CMD25 is ignor-ed.

4GB, 8GB, 16GB, 32GB: e·MMCData Transfer Mode – RPMB



Table 121: RPMB Access Data Frame Field Descriptions (Continued)

Field Direction Description

Block Count Request The number of blocks (half-sectors, 256 bytes) requested to beread/programmed. This value is equal to the count value in theCMD23 argument.

Op Result(Operation Result)

Response Includes information about the status of the write counter (validor expired) and the success of the access to the RPMB. See Ta-ble 122 (page 149) for the data structure of the operation resultfield. See Table 123 (page 149) for defined results and possiblereasons for failures.

Req/Resp(Request/Response Type)

Request (to the memory);response (from the memo-

ry)

Defines the type of request and response to/from the memory.See Table 124 (page 150) for defined requests and responses.The response type corresponds to the previous RPMB read/writerequest.

CRC16 n/a CRC16 value.

End n/a End bit.

Table 122: RPMB Operation Result Field Data Structure

Bit[15:8] Bit 7 Bit[6:0]

Reserved Write Counter Status Operation Result

Table 123: RPMB Operation Result Field Defined Results

Operation Results1 Description

0x00 (0x80) Operation OK

0x01 (0x81) General failure

0x02 (0x82) Authentication failure (MAC comparison is not matching, MAC calculation failure)

0x03 (0x83) Counter failure (counters are not matching in comparison, counter incrementing failure)

0x04 (0x84) Address failure (address out of range, wrong address alignment)

0x05 (0x85) Write failure (data/counter/result write failure)

0x06 (0x86) Read failure (data/counter/result read failure)

0x072 Authentication key not yet programmed

Notes: 1. The values in parentheses are valid in the case that the write counter has expired(reached its maximum value).

2. This value is the only valid result value until the authentication key has been program-med, after which it can never occur again.




Table 124: RPMB Request/Response Message Types

Message Types

Request

0x0001 Authentication key programming request

0x0002 Reading of the write counter value request

0x0003 Authenticated data write request

0x0004 Authenticated data read request

0x0005 Result read request1

Response

0x0100 Authentication key programming response

0x0200 Reading of the write counter value response

0x0300 Authenticated data write response

0x0400 Authenticated data read response

Note: 1. There is no corresponding response type for the result read request because the readingof the result with this request is always relative to previous programming access.

RPMB Memory MapThe RPMB map is shown in the following table.

Table 125: RPMB Memory Map

Register/Memory Partition Size Type Description

Authentication Key 32 bytes Write once One-time programmable authentication key register.This register cannot be overwritten, erased, or read.The key is used by the e·MMC RPMB engine to authenti-cate the accesses when the MAC is calculated. The MACis delivered in the last (or the only) block of data.

Data 128KB (MIN)(RPMB_SIZE_MULT x

128KB)

Read/write Data that can only be read and written via successfullyauthenticated read/write access. This data can be over-written by the host, but can never be erased.

Write Counter 4 bytes Read-only Counter value for the total amount of successfully au-thenticated data write requests made by the host. Theinitial value after e·MMC production is 0x0000 0000.The value is incremented by one automatically by thee·MMC RPMB engine, along with successful program-ming accesses. The value cannot be reset. After thecounter reaches its maximum value of 0xFFFF FFFF, it isno longer incremented (overflow prevention), and bit 7in the operation result value is permanently set.




MAC Calculation for RPMBThe message authentication code (MAC) is calculated using HMAC SHA-256 (Refer-ence: [HMAC-SHA] Eastlake, D. and T. Hansen, "US Secure Hash Algorithms (SHA andHMAC-SHA)," RFC 4634, July 2006). The HMAC SHA-256 calculation takes a key and amessage as inputs. The resulting MAC is 256 bits (32 bytes), which are embedded in thedata frame as part of the request or response.

The key used for the MAC calculation is always the 256-bit authentication key stored inthe e·MMC. The message used as input to the MAC calculation is the concatenation ofthe fields in the data frames, excluding stuff bytes, the MAC itself, the start bit, CRC16,and the end bit. That is, the MAC is calculated over bytes[283:0] of the data frame inthat order.

If several data frames are sent as part of one request or response, then the input mes-sage to the MAC is the concatenation of bytes[283:0] of each data frame in the order inwhich the data frames are sent. The MAC is added only to the last data frame.

MAC Data Frame Example: Assume that the write counter is 0x12345678. The hostwants to write two sectors at address 0x0010; the first sector is 256 bytes of 0xAA and thesecond sector is 256 bytes of 0xBB. The host must then send the two request framesshown in the following table, where the MAC in the second request frame is an HMACSHA-256 calculated over the following message:

0xAA... (total 256 times) ... 0xAA

0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000

0x1234 0x5678 0x0010 0x0002 0x0000 0x0003

0xBB... (total 256 times) ... 0xBB

0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000

0x1234 0x5678 0x0010 0x0002 0x0000 0x0003

The key used for the HMAC SHA-256 calculation is the authentication key stored in thee·MMC.

Table 126: MAC Request Frames

StartStuffBytes

Key/MAC Data Nonce


BlockCount Result

Req/Resp CRC16 End

1 bit 196bytes

32bytes

256bytes

16bytes

4bytes

2bytes

2bytes

2bytes

2bytes

2bytes

1 bit

[511:316] [315:284] [283:28] [27:12] [11:8] [7:6] [5:4] [3:2] [1:0]

Request Frame 1

0x0000... 0x0000... 0xAA... 0x0000... 0x12345678 0x0010 0x0002 0x0000 0x0003

Request Frame 2

0x0000... MAC 0xBB... 0x0000... 0x12345678 0x0010 0x0002 0x0000 0x0003




Accesses to the RPMBAfter placing a device into the transfer state, the host sends the SWITCH (CMD6) com-mand to set the PARTITION_ACCESS bits in ECSD register byte 179. Thereafter, thehost can use the SET_BLOCK_COUNT (CMD23), READ_MULTIPLE_BLOCK (CMD18),and WRITE_MULTIPLE_BLOCK (CMD25) commands to access the RPMB partition.The defined accesses are listed in following sections.

Any undefined set of parameters, sequence of commands, or high-priority interrupt dur-ing an authenticated write will result in failed access, as indicated in the following cases:

• Data programming: The data will not be programmed.

• Data READ operation: The data read will be 0x00 in all frames of a multiple block.

General Failure (0x01) will be indicated in the results register (in all frames of a multipleblock). If more than one failure is related to an access, the first type or error will be indi-cated in the results register. The order of error checking is defined in each access below.

After finishing data access to the RPMB partition, the PARTITION_ACCESS bits shouldbe cleared.

Programming of the Authentication Key: The authentication key is programmed withthe WRITE_MULTIPLE_BLOCK (CMD25) command. Prior to issuing CMD25, the blockcount is set to 1 by the SET_BLOCK_COUNT (CMD23) command, with argument bit 31set to 1 to indicate the reliable write type of programming. If the block count has notbeen set to 1 and/or argument bit 31 has not been set to 1, then the subsequentWRITE_MULTIPLE_BLOCK command fails and General Failure is indicated.

The authentication key information is delivered in a 512-byte data packet that includesthe request type information and the authentication key (see the table below). The re-quest type value of 0x0001 indicates programming of the authentication key.

Table 127: Authentication Key Information Data Packet

StartStuffBytes

Key/MAC Data Nonce


BlockCount Result

Req/Resp CRC16 End

1 bit 196bytes

32bytes

256bytes

16bytes

4bytes

2bytes

2bytes

2bytes

2bytes

2bytes

1 bit

[511:316] [315:284] [283:28] [27:12] [11:8] [7:6] [5:4] [3:2] [1:0]

0b 0x0000... 0x00 0x00 0x00 0x00 0x00 0x00 0x0001 1b

The busy signal on the DAT0 line after the CRC status is issued by the device indicatesprogramming of the authentication key. The status can also be polled with the SEND_STA-TUS (CMD13) command. The status response received in R1 indicates the genericstatus condition, excluding the status of successful programming of the authenticationkey.

The successful programming of the authentication key should be checked by readingthe result register of the RPMB. The result read sequence is initiated by the WRITE_MUL-TIPLE_BLOCK (CMD25) command. Prior to issuing CMD25, the block count is set to 1by the SET_BLOCK_COUNT (CMD23) command. If the block count has not been set to1, then the subsequent CMD25 fails and General Failure is indicated.




The request type information is delivered in a 512-byte data packet that includes therequest type information. The request type value of 0x0005 indicates result register readrequest initiation.

Table 128: Authentication Key Request Type Information Data Packet

StartStuffBytes

Key/MAC Data Nonce


BlockCount Result

Req/Resp CRC16 End

1 bit 196bytes

32bytes

256bytes

16bytes

4bytes

2bytes

2bytes

2bytes

2bytes

2bytes

1 bit

[511:316] [315:284] [283:28] [27:12] [11:8] [7:6] [5:4] [3:2] [1:0]

0b 0x0000... 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x0005 1b

The busy signal on the DAT0 line after the CRC status by the device indicates RequestBusy. The result is read out with a READ_MULTIPLE_BLOCK (CMD18) command. Priorto CMD18, the block count is set to 1 by the SET_BLOCK_COUNT (CMD23) command.If the block count has not been set to 1, then CMD18 fails, and General Failure is indicated.

The result information is delivered in a 512-byte read data packet that includes the re-sponse type information and the result of the KEY PROGRAMMING operation. Theresponse type value of 0x0100 corresponds to the KEY PROGRAMMING request.

Table 129: Authentication Key Result Information Data Packet

StartStuffBytes

Key/MAC Data Nonce


BlockCount Result

Req/Resp CRC16 End

1 bit 196bytes

32bytes

256bytes

16bytes

4bytes

2bytes

2bytes

2bytes

2bytes

2bytes

1 bit

[511:316] [315:284] [283:28] [27:12] [11:8] [7:6] [5:4] [3:2] [1:0]

0b 0x0000... 0x00 0x00 0x00 0x00 0x00 0x00 0x0100 1b

Access to the RPMB is not enabled before the authentication key is programmed.

The state of the device can be checked by trying to write data to or read data from theRPMB and then reading the result register. If the authentication key is not yet program-med, then message 0x07 (authentication key not yet programmed) is returned in theresult field.

If programming of the authentication key fails, then the returned result is 0x05 (writefailure).

If other errors occur during authentication key programming, then the returned resultis 0x01 (General Failure).

Reading of the Counter Value: The counter read sequence is initiated by the WRITE_MUL-TIPLE_BLOCK (CMD25) command. Prior to CMD25, the block count is set to 1 by theSET_BLOCK_COUNT (CMD23) command. If the block count has not been set to 1, thenthe subsequent CMD25 fails and General Failure is indicated.

The request type information is delivered in a 512-byte data packet that includes therequest type information and the nonce. The request type value of 0x0002 indicatescounter value read request initiation.




Table 130: Counter Read Request Type Information Data Packet

StartStuffBytes

Key/MAC Data Nonce


BlockCount Result

Req/Resp CRC16 End

1 bit 196bytes

32bytes

256bytes

16bytes

4bytes

2bytes

2bytes

2bytes

2bytes

2bytes

1 bit

[511:316] [315:284] [283:28] [27:12] [11:8] [7:6] [5:4] [3:2] [1:0]

0b 0x0000... 0x00 0x00 0x00 0x00 0x00 0x00 0x0002 1b

The busy signal in the DAT0 line after the CRC status by the device indicates request busy.

The counter value is read out with the READ_MULTIPLE_BLOCK (CMD18) command.Prior to CMD18, the block count is set to 1 by the SET_BLOCK_COUNT (CMD23) com-mand. If the block count has not been set to 1, then CMD18 fails and General Failure isindicated.

The counter value is delivered in a 512-byte read data packet that includes the responsetype information, a copy of the nonce received in the request, the write counter value,the MAC, and the result.

Table 131: Counter Value Read Data Packet

StartStuffBytes

Key/MAC Data Nonce


BlockCount Result

Req/Resp CRC16 End

1 bit 196bytes

32bytes

256bytes

16bytes

4bytes

2bytes

2bytes

2bytes

2bytes

2bytes

1 bit

[511:316] [315:284] [283:28] [27:12] [11:8] [7:6] [5:4] [3:2] [1:0]

0b 0x0000... 0x00 0x00 0x00 0x0200 1b

If reading of the counter value fails, then the returned result is 0x06 (Read Failure).

If other errors occur, then the returned result is 0x01 (General Failure).

If the counter has also expired, bit 7 is set to 1 in the returned results (Result values0x80, 0x86, and 0x81, respectively).

Authenticated Data Write: Data to the RPMB is programmed with the WRITE_MULTI-PLE_BLOCK (CMD25) command. Prior to CMD25, the block count is set by theSET_BLOCK_COUNT (CMD23) command, with argument bit 31 set to 1 to indicate areliable write type of programming access. The block count is the number of the half-sectors (256 bytes) to be programmed. The size of the access cannot exceed the size ofthe reliable write access (REL_WR_SEC_C x 512 bytes).

• REL_WR_SEC_C = 1: Access sizes of 256 bytes and 512 bytes are supported for theRPMB partition.

• REL_WR_SEC_C > 1: Access sizes up to REL_WR_SEC_Cx512 bytes are supported forthe RPMB partition with 256-byte granularity.




If the block count has not been set, and/or argument bit 31 has not been set to 1, and/or the size exceeds the maximum size of the reliable write access, then the subsequentCMD25 fails and General Failure is indicated.

Authenticated write data is delivered in a 512-byte data packet that includes the requesttype information, the block count, the counter value, the start address of the data, thedata itself, and the MAC. In the case of a multiple-block write, the MAC is included onlyto the last packet n, and the n-1 packets include a value of 0x00. In every packet, theaddress is the start address of the full access (not the address of the individual half -sec-tor) and the block count is the total count of the half-sectors (not the sequence numberof the half -sector).The request type value of 0x0003 indicates programming of the data.

Table 132: Authenticated Data Write Data Packet

StartStuffBytes

Key/MAC Data Nonce


BlockCount Result

Req/Resp CRC16 End

1 bit 196bytes

32bytes

256bytes

16bytes

4bytes

2bytes

2bytes

2bytes

2bytes

2bytes

1 bit

[511:316] [315:284] [283:28] [27:12] [11:8] [7:6] [5:4] [3:2] [1:0]

0b 0x0000... 0x00 0x00 0x0003 1b

The BUSY signal on the DAT0 line after the CRC status by the device indicates BufferBusy between the sent blocks (in the case of a multiple-block write) and the Program-ming Busy status of the key after the last block. The status can also be polled with theSEND_STATUS (CMD13) command. The status response received in R1 indicates thegeneric access status condition (for example, state transitions), excluding the status ofsuccessful programming of the data.

When the device receives this message, it first checks whether the write counter has ex-pired. If the write counter has expired, then the device sets the result to 0x85 (WriteFailure, Write Counter Expired) and no data is written to the device.

Next, the address is checked. If there is an error in the address (for example, AddressOut of Range), then the result is set to 0x04 (Address Failure) and no data is written tothe device.

If the write counter has not expired, then the device calculates the MAC of the requesttype, block count, write counter, address, and data, and compares this with the MAC inthe request. If the two MACs are different, then the device sets the result to 0x02 (Authen-tication Failure) and no data is written to the device.

If the MAC in the request and the calculated MAC are equal, then the device comparesthe write counter in the request with the write counter stored in the device. If the twocounters are different, then the device sets the result to 0x03 (Counter Failure) and nodata is written to the device.

If the MAC and write counter comparisons are successful, then the write request is con-sidered to be authenticated. The data from the request is written to the address indica-ted in the request and the write counter is incremented by 1.

If the write fails, then the returned result is 0x05 (Write Failure).

If other errors occur during the write procedure, then the returned result is 0x01 (Gener-al Failure).




The success of the data programming should be checked by the host by reading the re-sult register of the RPMB. The result read sequence is initiated by the WRITE_MULTI-PLE_BLOCK (CMD25) command. Prior to CMD25, the block count is set to 1 by theSET_BLOCK_COUNT (CMD23) command. If the block count has not been set to 1, thenthe subsequent CMD25 fails and General Failure is indicated.

The request type information is delivered in a 512-byte data packet that includes therequest type information. The request type value of 0x0005 indicates the result registerread request initiation.

Table 133: Authenticated Data Write Request Type Information Data Packet

StartStuffBytes

Key/MAC Data Nonce


BlockCount Result

Req/Resp CRC16 End

1 bit 196bytes

32bytes

256bytes

16bytes

4bytes

2bytes

2bytes

2bytes

2bytes

2bytes

1 bit

[511:316] [315:284] [283:28] [27:12] [11:8] [7:6] [5:4] [3:2] [1:0]

0b 0x0000... 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x0005 1b

The BUSY signal on the DAT0 line after the CRC status by the device indicates RequestBusy.

The result is read out with the READ_MULTIPLE_BLOCK (CMD18) command. Prior toCMD18, the block count is set to 1 by the SET_BLOCK_COUNT (CMD23) command. Ifthe block count has not been set to 1, then CMD18 fails and General Failure is indicated.

The Result information is delivered in a 512-byte read data packet that includes the re-sponse type information, the incremented counter value, the data address, the MAC,and the result of the data programming operation.

Table 134: Authenticated Data Write Result Information Data Packet

StartStuffBytes

Key/MAC Data Nonce


BlockCount Result

Req/Resp CRC16 End

1 bit 196bytes

32bytes

256bytes

16bytes

4bytes

2bytes

2bytes

2bytes

2bytes

2bytes

1 bit

[511:316] [315:284] [283:28] [27:12] [11:8] [7:6] [5:4] [3:2] [1:0]

0b 0x0000... 0x00 0x00 0x00 0x0300 1b




Authenticated Data Read: The authenticated data read sequence is initiated by theWRITE_MULTIPLE_BLOCK (CMD25) command. Prior to CMD25, the block count is setto 1 by the SET_BLOCK_COUNT (CMD23) command. If the block count has not beenset to 1, then the subsequent CMD25 fails and General Failure is indicated.

The request type information is delivered in a 512-byte data packet that includes therequest type information, the nonce, and the data address. The request type value of0x0004 indicates data read request initiation.

Table 135: Authenticated Data Read Request Type Information Data Packet

StartStuffBytes

Key/MAC Data Nonce


BlockCount Result

Req/Resp CRC16 End

1 bit 196bytes

32bytes

256bytes

16bytes

4bytes

2bytes

2bytes

2bytes

2bytes

2bytes

1 bit

[511:316] [315:284] [283:28] [27:12] [11:8] [7:6] [5:4] [3:2] [1:0]

0b 0x0000... 0x00 0x00 0x00 0x00 0x00 0x0004 1b

The BUSY signal on the DAT0 line after the CRC status by the device indicates RequestBusy.

When the device receives this request it first checks the address. If there is an error inthe address, then result is set to 0x04 (Address Failure) and the data read is not valid.

After a successful data fetch, the MAC is calculated from response type, nonce, address,data, and result. If the MAC calculation fails, then the returned result is 0x02 (Authenti-cation Failure).

The data is read out with the READ_MULTIPLE_BLOCK (CMD18) command. Prior toCMD18, the block count is set by the SET_BLOCK_COUNT (CMD23) command. Theblock count is the number of 256-byte half-sectors to be read. If the block count has notbeen set, then CMD18 fails and General Failure is indicated.

The data information is delivered in a 512-byte read data packet that includes the re-sponse type information, the block count, a copy of the nonce received in the request,the data address, the data itself, the MAC, and the result. In the case of a multiple-blockread, the MAC is included only to the last packet n; the n-1 packets include the value of0x00. In every packet, the address is the start address of the full access (not the addressof the individual half-sector) and the block count is the total count of the half-sectors(not the sequence number of the half-sector).

Table 136: Authenticated Data Read Information Data Packet

StartStuffBytes

Key/MAC Data Nonce


BlockCount Result

Req/Resp CRC16 End

1 bit 196bytes

32bytes

256bytes

16bytes

4bytes

2bytes

2bytes

2bytes

2bytes

2bytes

1 bit

[511:316] [315:284] [283:28] [27:12] [11:8] [7:6] [5:4] [3:2] [1:0]

0b 0x0000... 0x00 0x0400 1b

If the data fetched from an address location inside the device fails, then the returnedresult is 0x06 (Read Failure).




If other errors occur during the READ operation, then the returned result is 0x01 (Gener-al Failure).




Data Transfer Mode – Background OperationDevices have various maintenance operations need to perform internally. In order toreduce latencies during time-critical operations like READ and WRITE, it is better to ex-ecute maintenance operations at other times, such as when the host is not beingserviced. Operations are then separated into two types:

• Foreground operations: Operations that the host needs serviced such as read or writecommands

• Background operations: Operations that the device executes while not servicing thehost

In order for the device to know when the host does not need it and it can execute back-ground operations, the host will write any value to BKOPS_START (ECSD byte 164) tomanually start background operations. The device will stay busy until no more back-ground processing is required.

Since foreground operations are of a higher priority than background operations, thehost may interrupt ongoing background operations using the high-priority interruptfunction (see High-Priority Interrupt).

In order for the device to know if the host is going to periodically start background oper-ations, the host will set bit 0 of BKOPS_EN (ECSD byte 163) to indicate that it is going towrite to BKOPS_START periodically. The device may then delay some of its mainte-nance operations to a time when the host writes to BKOPS_START.

The device reports its background operation status in bits[1:0] of BKOPS_STATUS(ECSD byte 246), which can be at one of four possible levels:

• 0x0: Level 0 – No operations required

• 0x1: Level 1 – Operations outstanding – Non-critical

• 0x2: Level 2 – Operations outstanding – Perfomance being impacted

• 0x3: Level 3 – Operations outstanding – Critical

The host will check the status periodically and start background operations as needed,so that the device has enough time for its maintenance operations, to help reduce thelatencies during foreground operations.

If the status is at level 3 (critical), some operations may extend beyond their originaltimeouts due to maintenance operations which can no longe be delayed. The hostshould give the device enough time for background operations to avoid ever reachingthis level.

To enable the host to quickly detect the higher levels of background operation status,the URGENT_BKOPS bit in the card status register is set whenever the level is either 2 or3. This enables the host to detect urgent levels on every R1-type of response. The hostwill still read the full status from the BKOPS_STATUS byte periodically and start back-ground operations as needed.

The background operations feature is optional. If it is supported, bit 0 of BKOPS_SUP-PORT (ECSD byte 502) will be set.

4GB, 8GB, 16GB, 32GB: e·MMCData Transfer Mode – Background Operation



Data Transfer Mode – High-Priority InterruptIn some scenarios, different types of data on the device bus may have different priori-ties for the host. For example, a WRITE operation may be time-consuming and theremay be a need to suppress that operation to enable demand paging requests to launcha process requested by the user.

The high-priority interrupt (HPI) function enables servicing high-priority requests byenabling the device to interrupt a lower-priority operation before it is actually comple-ted, within the OUT_OF_INTERRUPT_BUSY_TIME timeout. The host may need torepeat the interrupted operation, or part of it, to complete the original request.

The HPI command can have one of two of the following implementations in the device:

• CMD12: Based on the STOP_TRANSMISSION command when the HPI bit is set in itsargument.

• CMD13: Based on the SEND_STATUS command when the HPI bit is set in its argument.

The host will check the read-only HPI_IMPLEMENTATION bit in ECSD byte 503(HPI_FEATURES) and use the appropriate command index.

If CMD12 is used with the HPI bit set, it differs from the non-HPI command in the ena-bled state transitions. (See the Card State Transitions table in Bus Protocol – CommandToken.)

An HPI command will only be executed durin the prg state. Then, it indicates to thedevice that a higher-priority command is pending and, therefore, it should interrupt thecurrent operation and return to the tran state, as soon as possible, with a different time-out value.

If an HPI command is received in states other than the prg state, the device behavior isdefined by the Card State Transitions table in Bus Protocol – Command Token. If thestate transition is enabled, a response is sent but the HPI bit is ignored. If the state tran-sition is not enabled, the command is regarded as illegal.

An HPI command is accepted as a legal command in the prg state. However, only somecommands can be interrupted by HPI. If an HPI command is received during com-mands that are not interruptible, a response is sent but the HPI command has no effectand the original command is completed normally, although possibly exceeding theOUT_OF_INTERRUPT_TIME timeout. The following table shows which commands areinterruptible and which are not.

Table 137: Interruptible Commands

CMD Index Name Interruptible? Restrictions

CMD24 WRITE_BLOCK Yes –CMD25 WRITE_MULTIPLE_BLOCK Yes –CMD38 ERASE Yes –CMD6 SWITCH Yes –

All other commands No Only interruptible when writing to theBKOPS_START field in the ECSD register

Following a WRITE_MULTIPLE_BLOCK (CMD25) command, the device updates theCORRECTLY_PRG_SECTORS_NUM field (ECSD bytes [245:242]) with the number of 512-byte sectors successfully written to the device. The host may use this information when

4GB, 8GB, 16GB, 32GB: e·MMCData Transfer Mode – High-Priority Interrupt



repeating an interrupted WRITE command. It does not need to rewrite all data sectors;it may skip the correctly programmed sectors and continue writing only the rest of thedata that had not yet been programmed.

If an HPI command is received during a reliable write, and EN_REL_WR is 0, the reliablewrite command is either completed (all new data is written) or canceled (no new data iswritten). Note that if HPI is supported, REL_WR_SEC_C is always 1.

If an HPI command is received during a reliable write and EN_REL_WR is 1, the firstCORRECTLY_PRG_SECTORS_NUM sectors will contain the new data and all the rest ofthe sectors will contain the old data.

The HPI function will be enabled before it may be used, by setting the HPI_EN bit in theHPI_MGMT field (ECSD byte 161).

The HPI function is optional. If it is supported, the HPI_SUPPORT bit in the HPI_FEA-TURES field (ECSD byte 503) will be set.

4GB, 8GB, 16GB, 32GB: e·MMCData Transfer Mode – High-Priority Interrupt



Data Transfer Mode – R/W Blocks, Erase Groups, and WPGsThe basic unit of data transfer to and from the device is 1 byte. All data transfer opera-tions that require a block size always define block lengths as integer multiples of bytes.Some special functions need additional partition granularity.

The block is the unit related to the block-oriented read and write (R/W) commands. Theblock size is the number of bytes that will be transferred when one block command issent by the host. The size of a block is either programmable or fixed. Information aboutsupported block sizes and programmability is stored in the CSD register.

For read/write devices, the following erase and write-protect units are defined:

• Erase group: The smallest number of consecutive write blocks that can be erased. Thesize of the erase group is device-specific and is stored in the CSD register whenERASE_GROUP_DEF in the ECSD register is disabled and in the ECSD register whenERASE_GROUP_DEF is enabled.

• Write-protect group (WPG): The smallest unit that can be individually write protec-ted. The size of a WPG is device-specific and is stored in the CSD register whenERASE_GROUP_DEF in the ECSD register is disabled and in the ECSD register whenERASE_GROUP_DEF is enabled.

Figure 34: Relationships Between Write Blocks, Erase Groups, and WPGs

Write block 0

Erase group 0

Erase group 1

Erase group 2

Erase group 3

Erase group n

Write block 1 Write block 2 Write block 3 Write block n

e·MMC

Write protect group 0



Write protect group n

4GB, 8GB, 16GB, 32GB: e·MMCData Transfer Mode – R/W Blocks, Erase Groups, and WPGs



Inactive ModeThe device enters inactive mode if the access mode is not valid. The device can alsoenter the inactive mode when the GO_INACTIVE_STATE command (CMD15) is re-ceived. The device resets to the pre-idle state with a power cycle.

4GB, 8GB, 16GB, 32GB: e·MMCInactive Mode



DC Electrical Specifications – Bus (MLC e·MMC)

Bus Topology

Figure 35: Bus Circuitry Diagram (MLC e·MMC)

ROD

CMD

DAT[7:0]

CLK

RST_n(Host optional)

RDAT RCMDM

MC

Ho

st

e·MMC

ROD is switched on and off by the host to alternate between the open-drain and push-pull bus modes. The host is not required to have open-drain drivers, but it mustrecognize this mode to switch on the ROD. The RDAT and RCMD are pull-up resistors thatprevent the CMD and the DAT lines from floating when no device is inserted or whenall device drivers are in High-Z mode.

A constant current source can replace the ROD for better performance by maintainingconstant slopes for the rising and falling edges of the signal. If the host does not allowthe switchable ROD implementation, a fixed RCMD can be used (the minimum value isdefined in the the following table). The maximum operating frequency in the open-drain mode must be reduced if the RCMD value used is higher than the minimumindicated in the following table.

4GB, 8GB, 16GB, 32GB: e·MMCDC Electrical Specifications – Bus (MLC e·MMC)



Table 138: Host and Bus Resistance Values (MLC e·MMC)

Parameter Symbol Min Typ Max Unit Description

Pull-up resistance for CMD RCMD 4.7 1001 kΩ Prevents bus floating

Pull-up resistance for DAT[7:0] RDAT 10 1001 kΩ Prevents bus floating

Internal pull-up resistance for DAT[7:1] RINT 10 150 kΩ Prevents unconnected lines floating

Bus signal line capacitance CL 30 pF Single device

Single device capacitance CDEVICE 7 12 pF

Maximum signal line inductance 16 nH FPP ≤ 52 MHz

Note: 1. Recommended maximum pull-up resistance is 50kΩ for 1.2V and 1.8V interface supplies.A 3V device can use the whole range of values, up to 100kΩ.

Bus Operating Conditions

Table 139: Bus Operating Conditions (MLC e·MMC)

Parameters/Conditions Min Max Unit Notes

Peak voltage on all lines –0.5 VCCQ + 0.5 V

Input leakage current (before initializing and/or connect-ing the internal pull-up resistors)

–100 100 μA All lines except RST_n

Input leakage current (after changing the bus width anddisconnecting the internal pull-up resistors)

–2 2 μA Except the DAT3 pin1

and RST_n

Output leakage current (before initializing and/or connect-ing the internal pull-up resistors)

–100 100 μA All lines except RST_n

Output leakage current (after changing the bus width anddisconnecting the internal pull-up resistors)

–2 2 μA Except the DAT3 pin1

and RST_n

RST_n leakage current –2 2 μA

Note: 1. To ensure that the device enters e·MMC mode, the DAT3 signal has an internal pull-upresistor. For the DAT3 signal, the specification for input/output leakage current is –100μA (MIN) to 100μA (MAX).

Bus Signal Line LoadThe total load capacitance (CL) of each line of the e·MMC bus is the sum of the hostcapacitance (CHOST), the bus capacitance (CBUS), and the capacitance of the device con-nected to the line (CDEVICE):

CL = CHOST + CBUS + CDEVICE

The sum of the host and the bus capacitances must not exceed 20pF.




Bus Signal LevelsThe bus can be supplied with a variable supply voltage; all signal levels are directly rela-ted to the supply voltage.

Figure 36: Bus Signal Levels (MLC e·MMC)

VCCQ

VSSQ t

VIL

VOL

VOH

VIH

Inputhigh level

Undefined

Inputlow level

Outputhigh level

Outputlow level

V

Table 140: Open-Drain Mode Bus Signal Levels (MLC e·MMC)

Parameter1 Symbol Min Max Unit Conditions

Output high voltage VOH VCCQ - 0.2 – V IOH = –100μA

Output Low voltage VOL – 0.3 V IOL = 2mA

Note: 1. The input levels are identical to those of the push-pull mode bus signal lines.

Table 141: Push-Pull Mode Bus Signal Levels (MLC e·MMC, VCCQ = 2.7–3.6V)

Parameter Symbol Min Max Unit Conditions

Output high voltage VOH 0.75 × VCCQ – V IOH = –100μA atVCCQ,min

Output low voltage VOL – 0.125 × VCCQ V IOL = 100μA at VCCQ,min

Input high voltage VIH 0.625 × VCCQ VCCQ + 0.3 V

Input low voltage VIL VSS - 0.3 0.25 × VCCQ V

Table 142: Push-Pull Mode Bus Signal Levels (MLC e·MMC, VCCQ = 1.65–1.95V)


Output high voltage VOH VCCQ - 0.45 – V IOH = –2mA

Output low voltage VOL 0.45 V IOL = 2mA

Input high voltage VIH 0.65 × VCCQ1 VCCQ + 0.3 V

Input low voltage VIL VSS - 0.3 0.35 × VCCQ2 V

Notes: 1. 0.7 × VCCQ for MMC4.3 and older revisions.2. 0.3 × VCCQ for MMC4.3 and older revisions.




DC Electrical Specifications – Device Power (MLC e·MMC)The device current consumption for various device configurations is defined in the pow-er class fields of the ECSD register.

During power-on (except during a BOOT operation), the current consumption of anydevice must not exceed 10mA before the host sends a valid OC register range.

VCC is used for the NAND Flash device and its interface voltage; VCCQ is used for thecontroller and the e·MMC interface voltage. The core regulator is optional and only re-quired when VCCQ is in the 3V range. A CREG capacitor must be connected to the VDDIterminal to stabilize regulator output on the system.

Figure 37: Device Power Diagram (MLC e·MMC)

NAND

control signalsNAND Flash

MMC controller

Core regulator

NA

ND

I/O b

lock

MM

CI/O

blo

ck

Corelogic block

CLKCMD

DAT[7:0]

VCC

VDDI

CREG

VCCQ

NAND

data bus

Table 143: Absolute Maximum Ratings (MLC e·MMC)

Parameters Symbol Min Max Unit

Voltage input VIN –0.6 4.6 V

VCC supply VCC –0.6 4.6 V

VCCQ supply VCCQ –0.6 4.6 V

Storage temperature TSTG –40 85 °C

Notes: 1. Voltage on any pin relative to VSS.2. Stresses greater than those listed under "Absolute Maximum Ratings" may cause perma-

nent damage to the device. This is a stress rating only, and functional operation of thedevice at these or any other conditions above those indicated in the operational sec-tions of this specification is not guaranteed. Exposure to absolute maximum ratingconditions for extended periods may affect reliability.

4GB, 8GB, 16GB, 32GB: e·MMCDC Electrical Specifications – Device Power (MLC e·MMC)



Table 144: Device Power Supply Voltages (MLC e·MMC)

Parameters Symbol Min Typ Max Unit

Supply voltage (controllerand I/O)

VCCQ 1.65 – 1.95 V

2.70 – 3.6

Supply voltage (NAND) VCC 2.70 – 3.6 V

Supply power-on for 3.3V tPRUH – – 35 ms

Supply power-on for 1.8V tPRUL – – 25 ms

VDDI capacitance value CREG1 0.1 – – µF

Note: 1. CREG is used to stabilize the internal regulator output to controller core logic voltages.Micron recommends using the following capacitor values:CVCC (capacitor for VCC) = 4.3µFCVCCQ (capacitor for VCCQ) = 4.3µFCREG = 1.0µF

4GB, 8GB, 16GB, 32GB: e·MMCDC Electrical Specifications – Device Power (MLC e·MMC)



DC Electrical Specifications – Power-On SequenceThe e·MMC bus power-on is handled locally in each device and in the host. The power-on sequence is shown in the following figure. Specific instructions regarding the power-on sequence are provided in “Power-On Guidelines.”

Figure 38: Power-On Sequence

VCCQ,min

VCCQ,max

VCCQ

VCC,max

VCC,min

Supply voltage

Power-up time Supply ramp-up time First CMD1 to device ready

CMD1 CMD1 CMD2CMD1NCC

1 NCC NCC

Optional repetitions of CMD1until the card is responding

with busy bit set

Power-on to CMD1 delay =the longest of 1ms, 74 clock cycles,

the supply ramp-up time,or the boot operation period.

Control logicworking

voltage range

Memory fieldworking

voltage range

Note: 1. See AC Electrical Specifications for NCC timing values.

4GB, 8GB, 16GB, 32GB: e·MMCDC Electrical Specifications – Power-On Sequence



The power-on sequence must adhere to the following guidelines:

• When power-on is initiated, either VCC or VCCQ can be ramped up first, or both can beramped up simultaneously.

• After power-on, the device enters the pre-idle state.

• The power-on time of each supply voltage should be less than the specified tPRU(tPRUH, tPRUL, or tPRUV) for the appropriate voltage range.

• If the BOOT_PARTITION_ENABLE bit is set, the device moves to the preboot stateand waits for the boot initiation sequence. Following the boot operation period, thedevice enters the idle state. During the preboot state, if the device receives any com-mand line transaction other than the boot initiation sequence (keeping the CMD lineLOW for at least 74 clock cycles or issuing CMD0 with an argument of 0xFFFFFFFAafter 74 clock cycles) and CMD1, the device moves to the idle state. If the device re-ceives the boot initiation sequence (keeping the CMD line LOW for at least 74 clockcycles or issuing CMD0 with the argument of 0xFFFFFFFA after 74 clock cycles), thedevice begins the boot operation. After the boot operation is terminated, the deviceenters the idle state and is ready to receive the SEND_OP_COND (CMD1) command.If the device receives CMD1 in the preboot state, it begins responding to the com-mand and moves to the card identification mode.

• While in the idle state, the device ignores all bus transactions until CMD1 is received.

• CMD1 is a special synchronization command used to negotiate the operation voltagerange and to poll the device until it has completed its power-on sequence. In additionto the operation voltage profile of the device, the response to CMD1 includes a busyflag, indicating that the device is still completing its power-on sequence and is notready for identification. This bit informs the host that the device is not ready, and thehost must wait until this bit is cleared. The device must complete its initialization with-in 1 second of the first CMD1 issued with a valid OC register range.

• If the device was successfully partitioned during the previous power-on session(ECSD register byte 155, bit 0, PARTITION_SETTING_COMPLETE successfully set),then the initialization delay is calculated from INI_TIMEOUT_PA (ECSD register byte241), instead of being 1 second. This timeout applies only for the first initializationafter successful partitioning. For all subsequent initializations, a 1-second timeout ap-plies.

• The power-on time and the supply ramp-up time depend on application parameterssuch as the bus length and the power supply unit. Therefore, the host must ensurethat power is built up to the operating level (the same level that is specified in the datasheet) before CMD1 is transmitted.

• After power-on, the host starts the clock and the device starts the initialization se-quence internally. The sequence period (power-on to CMD1 delay) is the longest of1ms, 74 clocks, the supply ramp-up time, or the boot operation period. An additional10 clocks (beyond the 64 clocks of the power-on sequence) are provided to eliminatepower-on synchronization problems.

• Every host must implement the SEND_OP_COND (CMD1) command.

4GB, 8GB, 16GB, 32GB: e·MMCDC Electrical Specifications – Power-On Sequence



DC Electrical Specifications – RST_n Signal During Power-On PeriodWhen the device powers on, the RST_n signal rises during power ramp-up. The devicemay detect the rising edge of the RST_n signal during one of the power-on periods (1, 2,3, or 4).

Figure 39: RST_n Signal During Power-On Period

VCC

VCCQ

RST_n 1 2 3 4

If the RST_n signal falls before VCCQ fully powers on, the rising edge of VCCQ is consid-ered the falling edge of the RST_n signal. In this case, the pulse width of the RST_nsignal should be measured between the rising edge of the RST_n signal and the time ittakes for VCCQ to power on.

During the device internal initialization sequence, right after power-on, the device maynot be able to detect the RST_n signal because it may not have completed loading theRST_n_ENABLE bits of the ECSD register into the controller. However, the device willalready have started the internal initialization sequence, which includes the reset se-quence initiated by assertion of the RST_n signal. The device may not need to performthe reset sequence again, but it should complete the internal initialization sequencewithin 1 second from the first CMD1 with a valid OC register range. In this case, the power-on to CMD1 delay should be the longest of 1ms, 74 clock cycles, 200µs after RST_n isasserted, or the supply ramp-up time (see Figure 38 (page 169) for a definition of power-on to CMD1 delay).

4GB, 8GB, 16GB, 32GB: e·MMCDC Electrical Specifications – RST_n Signal During Power-On

Period



DC Electrical Specifications – Power CyclingThe host can execute any sequence of VCC and VCCQ power-on/power-off. However, thehost must not issue any commands until VCC and VCCQ are stable within each operatingvoltage range. After the device enters sleep mode, the host can power down VCC to re-duce power consumption. The device must be ramped up to VCC before the host issuesthe SLEEP_AWAKE (CMD5) command to wake the device.

If VCC or VCCQ are below 0.5V for longer than 1ms, the device always returns to the pre-idle state to perform the appropriate boot operations. The device behaves as in astandard power-on condition after the voltages have returned to their functional rang-es. An exception to this behavior is if the device is in a sleep state in which VCC is notmonitored.

Figure 40: Power Cycle

VCC,min

VCCQ

VCC

Supply voltage

Command input prohibited Command input prohibitedSleep mode Time

VCCQ,min

4GB, 8GB, 16GB, 32GB: e·MMCDC Electrical Specifications – Power Cycling



AC Electrical Specifications

Table 145: Timing Values

Symbol Min Max Unit

NAC 2 10 × (TAAC × FOP + 100 × NSAC)1, 2 Clock cycles

NCC 8 – Clock cycles

NCD 56 – Clock cycles

NCP 74 – Clock cycles

NCR 2 64 Clock cycles

NID 5 5 Clock cycles

NRC 8 – Clock cycles

NSC 8 – Clock cycles

NST 2 2 Clock cycles

NWR 2 – Clock cyclestBA – 50 mstBD – 1 s

Notes: 1. See the following table for timing parameters.2. FOP = Operating frequency.

Table 146: Command Set Timing Parameters and Example Equation

Parameter Value1 Description

FOP 10 MHz Host e·MMC clock frequency2

TAAC 0x5E Asynchronous portion of the data access time

NSAC 0 Typical case for data access time-clock dependency

Example equation NAC = 10 × (5 × 10–3 × 10 × 106 + 0) = 500,000 clock cycles

Notes: 1. Values are provided as examples.2. Micron e·MMC supports the frequency shown in Table 148 (page 174) and Table 149

(page 175).

Table 147: Hardware Reset Timing Parameters

Symbol Description Min Max UnittRSTW RST_n pulse width 1 – μstRSCA RST_n to command time1 200 – μstRSTH RST_n high period (interval time) 1 – μs

Note: 1. 74 clock cycles required before issuing CMD1 or CMD0 with argument 0xFFFFFFFA.

4GB, 8GB, 16GB, 32GB: e·MMCAC Electrical Specifications



Table 148: Interface Timing (high-speed interface)


CLK1

Clock frequency data transfer mode (PP)2 FPP 0 523 MHz CL ≤30pF

Tolerance: +100 kHz

Clock frequency identification mode (OD) FOD 0 400 kHz Tolerance: +20 kHz

Clock high time tWH 6.5 – ns CL ≤30pF

Clock low time tWL 6.5 – ns CL ≤30pF

Clock rise time4 tTLH – 3 ns CL ≤30pF

Clock fall time tTHL – 3 ns CL ≤30pF

Inputs CMD, DAT (Referenced to CLK)

Input set-up time tISU 3 – ns CL ≤30pF

Input hold time tIH 3 – ns CL ≤30pF

Outputs CMD, DAT (Referenced to CLK)

Output delay time during data transfer tODLY – 13.7 ns CL ≤30pF

Output hold time tOH 2.5 – ns CL ≤30pF

Signal rise time5 tRISE – 3 ns CL ≤30pF

Signal fall time tFALL – 3 ns CL ≤30pF

Notes: 1. CLK timing is measured at 50% of VCCQ.2. Micron e·MMC devices support the full frequency range of 0–52 MHz.3. The device can also operate at a clock frequency of 26 MHz.4. CLK rise and fall times are measured by VIH,min and VIL,max.5. Rise and fall times for inputs CMD and DAT are measured by VIH,min and VIL,max. Rise and

fall times for outputs CMD and DAT are measured by VOH,min and VOL,max.




Table 149: Interface Timing (standard interface)

Parameter Symbol Min Max Unit Conditions1

CLK2

Clock frequency data transfer mode (PP)3 FPP 0 26 MHz CL ≤30pF

Clock frequency identification mode (OD) FOD 0 400 kHz

Clock high time tWH 10 – ns CL ≤30pF

Clock low time tWL 10 – ns CL ≤30pF

Clock rise time4 tTLH – 10 ns CL ≤30pF

Clock fall time tTHL – 10 ns CL ≤30pF

Inputs CMD, DAT (Referenced to CLK)

Input set-up time tISU 3 – ns CL ≤30pF

Input hold time tIH 3 – ns CL ≤30pF

Outputs CMD, DAT (Referenced to CLK)

Output set-up time5 tOSU 11.7 – ns CL ≤30pF

Output hold time5 tOH 8.3 – ns CL ≤30pF

Notes: 1. The device must always start with the standard interface timing. The timing mode canbe switched to high-speed interface timing by the host sending the SWITCH (CMD6) com-mand with the argument for high-speed interface selected.

2. CLK timing is measured at 50% of VCCQ.3. For compatibility with cards that support the v4.2 standard or earlier, the host should

not use >20 MHz before switching to high-speed interface timing.4. CLK rise and fall times are measured by VIH,min and VIL,max.5. tOSU and tOH are defined as values from the clock’s rising edge. However, there may be

devices that use the clock’s falling edge to output data in backward compatibility mode.Therefore, it is recommended that the host either sets the tWL value to be as long aspossible within the range defined by tCK through tOHmin, or that it uses a slow clockfrequency so that it can have a data setup margin for those devices. In this case, eachdevice that uses the clock’s falling edge may show a correlation between tWL and tOSU,or between tCK and tOSU, as a note in the device’s data sheet or as an application note.




Timeout ConditionsFor READ, WRITE, and ERASE operations, the time period after which a timeout condi-tion occurs is 10 times longer than the typical access and program time. If the devicedoes not complete the command within this time period, it terminates the commandand returns an error message. If the host does not get a response within the definedtimeout, it should assume that the device is not going to respond further and shouldattempt a recovery by by asserting the RST_n signal or initiating a power cycle.

Typical access and program times are defined as follows:

READ access time: READ access time is calculated from the two time values providedby the CSD register fields TAAC and NSAC. These device values define the typical delaybetween the end bit of the READ command and the start bit of the data block.

WRITE delay time: Typical WRITE delay time can be calculated using the R2W_FAC-TOR field in the CSD register multiplied by the read access time. This applies to allWRITE and ERASE commands (for example, SET_WRITE_PROT, CLR_WRITE_PROT,PROGRAM_CSD, PROGRAM_CID, and the block write commands).

ERASE/SECURE ERASE timeout: The duration of an ERASE command is the number oferase blocks to be erased, multiplied by the WRITE delay time. If ERASE_GROUP_DEF(ECSD register byte 175) is enabled, ERASE_TIMEOUT_MULT should be used to calcu-late the duration.

SECURE ERASE timeout is calculated based on the ERASE timeout and additionalSEC_ERASE_MULT factor (ECSD register byte 230).

TRIM/SECURE TRIM timeout: TRIM timeout is calculated based on the TRIM_MULTfactor (ECSD register byte 232). SECURE TRIM timeout is calculated based on theERASE timeout and additional SEC_TRIM_MULT factor (ECSD register byte 229).

FORCE ERASE timeout: The duration of the FORCE ERASE command using CMD42(LOCK_UNLOCK) is specified as a fixed timeout of three minutes.

High-priority interrupt (HPI): OUT_OF_INTERRUPT_TIME (ECSD byte 198) definesthe maximum time between the end bit of CMD12/13, arg bit 0 = 1 to the DAT0 releaseby the device.

Partition switch time: PARTITION_SWITCH_TIME (ECSD byte 199) defines the maxi-mum time between the end bit of the SWITCH (CMD6) command to the DAT0 releaseby the device, when switching partitions by changing PARTITION_ACCESS bits in thePARTITION_CONFIG field (ECSD byte 179).

4GB, 8GB, 16GB, 32GB: e·MMCTimeout Conditions



Bus and Device Interface Timing

Figure 41: Bus and Device Interface Timing

Clock

Input

Output

tOSUtODLY

tPP

tISU

50% VDD 50% VDD

tWH tWL

tIH tTHL tTLH

tOH

Data Invalid

Data Invalid Data

Data

VIH,min

VIL,max

VIH,min

VIL,max

VOH,min

VOL,max

Note: 1. Data must always be sampled on the rising edge of the clock.

4GB, 8GB, 16GB, 32GB: e·MMCBus and Device Interface Timing



Command Timing Symbols and DefinitionsAll command set timing diagrams use the command set symbols and definitions listedin the following table.

Table 150: Command Timing Symbols and Definitions

Symbol Definition

S Start bit (= 0)

T Transmitter bit (host = 1; device = 0)

P One cycle pull up (= 1)

E End bit (= 1)

L One cycle pull down (= 0)

Z High-Z state

X Driven value (1 or 0)

D Data bits

* Repetition

CRC Cyclic redundancy check bits (7 bits)

The difference between a P bit and a Z bit is that a P bit is actively driven HIGH by thedevice output driver, while a Z bit is driven (or kept) HIGH by the RCMD and RDAT pull-up resistors. Actively driven P bits are less sensitive to noise.

All timing values are defined in AC Electrical Specifications.

4GB, 8GB, 16GB, 32GB: e·MMCCommand Timing Symbols and Definitions



BOOT Operation TimingThe BOOT operations are only valid before the SEND_OP_COND (CMD1) command isissued (see Boot Mode for detailed information).

Figure 42: BOOT Operation Timing with Termination Between Consecutive Data Blocks

1

NAC

Z Z Z Z Z * * * * * *Z S 0 1 0 E S EP P * * *P P

CMD

DAT[7:0]

Z Z Z Z S L * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

NCP

tBAtBD

512 bytes + CRC S 512


Boot request recognized

1

NAC

* * *P P

CMD

DAT[7:0] S E512 bytes + CRC

NST

NCD1

P Z

EL Z S T CMD1

P P * * * * * * * *

Z * * Z* * * * * * * * * * * * * * * * * *

Boot operation complete

Note: 1. See also Figure 46 (page 182) in this section.

4GB, 8GB, 16GB, 32GB: e·MMCBOOT Operation Timing



Figure 43: BOOT Operation Timing with Termination During Transfer

1

NAC

Z Z Z Z Z * * * * * *Z S 0 1 0 E S EP P * * *P P

CMD

DAT[7:0]

Z Z Z Z S L

NCP

tBAtBD

512 bytes + CRC S


Boot request recognized

1

NAC

E * * *P P

CMD

DAT[7:0]

ZZL E

S EData

NST

NCD1

Z Z

ZZ Z Z Z * * * ** *

* *

Z

S T CMD1

Boot operation complete

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

* * * * * * * * * * * * * *

Note: 1. See also Figure 46 (page 182) in this section.




Figure 44: Alternative BOOT Operation Timing with Termination Between Consecutive Data Blocks

1

1

tBAtBD

CMD

DAT[7:0]

CMD

DAT[7:0]

Z Z * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

Z PSZ 0 1 0 E P S 512 bytes + CRC E


512 bytes + CRCP

* * * *

* * * * P S E P P P Z Z

Z Z Z * * *

Z * * *

Z Z S T CMD1

Boot operationcomplete

Note 2

Note 1

NSTNAC

CMD0

* * * * * * * * *

* * * * * * * * *

* * * * * * * * * * *

CMD0S ET

TS E

Notes: 1. CMD0 with argument 0xFFFFFFFA.2. See also Figure 46 (page 182) in this section.




Figure 45: Alternative BOOT Operation Timing with Termination During Transfer

1

NAC

Z * * * * * * * Z * * *Z EP P * *P P

Z Z * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

tBA OptionaltBD

Device activeHost active1

Z ZZ

NST Note 2

Note 1

Z

ZZ Z Z Z * * * * ** * *

* * *

Z

Boot operationcomplete

ES Data

S 512 bytes + CRCS 1 E0 0

T CMD0 ES

T CMD0 ES

S

S T CMD1

CMD

DAT[7:0]

CMD

DAT[7:0]

Notes: 1. CMD0 with argument 0xFFFFFFFA.2. See also Figure 46 (page 182) in this section.

Figure 46: Bus Mode Change Timing (push-pull to open drain)


CMD

DAT[7:0]

ZZE

EData

NSC

Z Z

ZZ Z * * * ** *

* *

Z

Z Z

Z* *

* *

Z

S T CMD1

Boot operation complete CLK ≤ 400 kHz




Command/Response TimingThe host command and the device response are both clocked out with the rising edge ofthe host clock.

SEND_OP_COND (CMD1) and ALL_SEND_CID (CMD2) TimingThe SEND_OP_COND (CMD1) (card operating condition) command and theALL_SEND_CID (CMD2) (card identification) command timing are processed in theopen-drain mode. The device response to the host command starts after exactly NIDclock cycles.

If the device does not respond to the ALL_SEND_CID (CMD2) command after NID + 1clock periods, the host concludes that no device is present on the bus.

Figure 47: SEND_OP_COND (CMD1) and ALL_SEND_CID (CMD2) Timing

S T Content CRC E

Host command

Z * * * Z

NID cycles

S T Content ZZZ

CID or OCR

ZCMD


SET_RCA (CMD3) TimingThe SET_RCA (CMD 3) (set relative card address) command timing is also processed inthe open-drain mode. The minimum delay between the host command and the deviceresponse is NCR clock cycles.

Figure 48: SET_RCA (CMD3) Timing

S T Content CRC E

Host command

Z * * *

NCR cycles

S T Content ECRC ZZZ

Device response

ZCMD


4GB, 8GB, 16GB, 32GB: e·MMCCommand/Response Timing



Data Transfer Mode TimingAfter a device receives its relative card address (RCA), it switches to data transfer mode.In this mode, the CMD line is driven with push-pull drivers. The command is followedby a period of two Z bits (providing time for direction switching on the bus), and thenby P bits pushed up by the responding device. The following figure is relevant for allhost commands that require a device response, with the exception of CMD1, CMD2,and CMD3.

Figure 49: Data Transfer Mode Timing

S T Content CRC E

Host command

Z Z P * * *

NCR cycles


Device response

PCMD


R1b Response TimingThe device may respond with R1 and then assert the BUSY signal when some com-mands, such as the SWITCH (CMD6) command, are issued. If the BUSY signal isasserted, it is asserted NST clock cycles after the end bit of the command. The DAT0 lineis driven LOW. DAT[7:1] lines are driven by the device; however, their values are notrelevant. This behavior changes for the case when CMD12 is issued during a data trans-fer from the host (see Figure 58 (page 190)).

Figure 50: R1b Response Timing

NST Device is busy

Host command

Z Z Z Z Z Z Z Z Z Z Z Z S L * * * * * * * * * * * * * * * * * * * * * * E Z Z Z

S T Content CRCCMD

DAT0DAT[7:1]

E Z Z P P* * * Z Z Z Z Z

Z Z Z Z Z Z Z Z Z Z Z Z X * * * * * * * * * * * * * * * * * * * * * * * * X Z Z Z

S T Content CRC E

NCR cycles Response





Last Device Response to Next Host Command TimingAfter receiving the last device response, the host can wait at least NRC clock cycles be-fore it starts the next command transmission. This timing is relevant for any hostcommand.

Figure 51: Timing Response End to Next Command Start (data transfer mode)

Host command

Z * * * Z

NRC cycles


Device response

ZCMD S T Content CRC E


Last Host Command to Next Host Command TimingAfter the last command has been sent, the host can continue sending the next com-mand after at least NCC clock cycles.

Figure 52: Command Sequences Timing (all modes)

S T Content CRC E

Host command Host command

Z * * * Z

NCC cycles

S T Content ZZZCMD

Host active




Data Read Timing

READ_SINGLE_BLOCK (CMD17) TimingThe host issues CMD7 to select a device for the data READ operation, then issuesCMD16 to set the valid block length for a block-oriented data transfer. The sequencestarts with the READ_SINGLE_BLOCK (CMD17) command, which specifies the start ad-dress in the argument field. The response is sent on the CMD line.

Data transmission from the device starts after the NAC access time delay, which beginsafter the end bit of the read command. After the last data bit, the CRC bits are suffixedto enable the host to check for transmission errors.

Figure 53: READ_SINGLE_BLOCK (CMD17) Timing

NAC cycles READ data

Host command Device responseNCR cycles

Z Z Z * * * * Z ZZ Z Z Z P * * * * * * * * * * P S D D D * * *

S T Content CRCCMD

DAT[7:0]

E Z Z P * * * P S T Content CRC E

* * *


READ_MULTIPLE_BLOCK (CMD18) TimingTo start a multiple-block read, the host issues CMD7 to select a device. The host thenissues the READ_MULTIPLE_BLOCK (CMD18) command to the selected device. Afterthe host issues CMD18, the device sends a continuous flow of data blocks during themultiple-block read. If the host didn’t set the block count prior to issuing CMD18, thedata flow must be terminated by a STOP_TRANSMISSION (CMD12) command. The da-ta transmission stops NST clock cycles after the end bit of CMD12. If the host set theblock count before issuing CMD18, then the operation is terminated after the blockcount number of data is transferred.

4GB, 8GB, 16GB, 32GB: e·MMCData Read Timing



Figure 54: READ_MULTIPLE_BLOCK (CMD18) Timing

1

1

NAC READ data

Host command ResponseNCR cycles

Z Z Z * * * * * Z Z Z Z P * * * * * * * P S D D D * * * * D E

S T Content CRCCMD

DAT[7:0]

E Z Z P * * P Z Z PS T Content CRC E

NAC READ data

D E P * * * * * * P S D D D D

CMD

DAT[7:0]

Z P P * * * * * * P P P P P P


READ data

Figure 55: STOP_TRANSMISSION (CMD12) Timing

NST

Host command

Valid READ data

Device response

D D D * * * * * * * * D D D E Z Z * * * * * * * * * * * * * * * * * * * *

S T Content CRCCMD

DAT[7:0]

E Z Z P * * * P S T Content CRC E


NCR cycles

4GB, 8GB, 16GB, 32GB: e·MMCData Read Timing



Data Write Timing

WRITE_BLOCK (CMD24) TimingTo start a single-block write, the host issues CMD7 to select a device for the data WRITEoperation, then issues CMD16 to set the valid block length for a block-oriented datatransfer.

The write sequence for a single-block write starts with the host issuing a WRITE_BLOCK(CMD24) command, which specifies the start address in the argument field. The hostwaits NWR clock cycles after the device responds on the CMD line, then starts transfer-ring data to the device.

The data is suffixed with CRC bits to enable the device to check for transmission errors.The device sends back the CRC result as a CRC status token on DAT0.

During programming, the device indicates it is busy by pulling the DAT0 line LOW. Thisbusy status is directly related to the programming state. As soon as the device com-pletes the programming, it stops pulling the DAT0 line LOW.

Figure 56: WRITE_BLOCK (CMD24) Timing

1

1

NWR WRITE data

Device responseHost command NCR cycles

Z Z * * * * * * Z Z * * * * * Z Z P * P S

S

Content

Content

CRC

CRC

E

E

Z

Z

Z

Z

S T Content CRCCMD

DAT0

DAT[7:1]

CMD

DAT0

DAT[7:1]

E Z Z P * * * * * * * * * * * * * * ZE Z P * P

Z Z * * * * * * Z

Z

Z Z * * * * * Z Z P * P

CRC status Busy

Z

Z

Z

Z

S

X

Status E S L * L

P P * * * P P P P P P PP

E

X

Z

Z* * * * * * * * * * * *


4GB, 8GB, 16GB, 32GB: e·MMCData Write Timing



WRITE_MULTIPLE_BLOCK (CMD25) TimingTo start a multiple-block write, the host issues CMD7 to select a device. The host thenissues the WRITE_MULTIPLE_BLOCK (CMD25) command to the selected device. Afterthe host issues CMD25, the device expects a continuous flow of data blocks from thehost during the multiple-block write. If the host didn’t set the block count prior to issu-ing CMD25, the data flow must be terminated by a STOP_TRANSMISSION (CMD12)command. If the host set the block count prior to issuing CMD25, the device terminatesthe operation after receiving the sector count number of data. The following figureshows the timing of the data blocks with and without the device BUSY signal.

Figure 57: WRITE_MULTIPLE_BLOCK (CMD25) Timing

1

1

CRC status Busy

Z S S L * L E Z P * P

X

Status

* * * * * * * *

E

X Z

CMD

DAT0DAT[7:1]

P P P * * * * P P PP* * * * *

Z

Z

Z P * P

NWR

WRITE dataNWR NWRWRITE data

Device response

Z Z Data + CRC ZS Z S

X

CMD

DAT0DAT[7:1]

Z Z P * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

Z Z Data + CRC Z

Z

Z

E

ES

Data + CRCS

Data + CRC

E

ES

StatusS

* * *

E

XX

P * P

P * P Z

Z

Z

Z

Z

P * P

P * P

CRC status


E




STOP_TRANSMISSION (CMD12) TimingThe STOP_TRANSMISSION (CMD12) command operates in a similar way for a write ora read. The timing of CMD12 is shown for different states in the following figures. Thefollowing figure shows the timing for CMD12 sent during a data transfer from the host.

The device treats a data block as successfully received and ready for programming onlyif the CRC data of the block was validated and the CRC status block was transmitted tothe host.

The data transfer must terminate with NST clock cycles following the end bit of the hostSTOP_TRANSMISSION (CMD12) command. Two high-Z clock cycles following host da-ta are used for switching the bus direction. In this scenario, the data block received isconsidered incomplete and will not be programmed.

Figure 58: STOP_TRANSMISSION (CMD12) Timing During Data Transfer From the Host

NST Busy (device is programming)

Host command Device response NCR cycles

D D D D D D D D D D E Z S L * * * * * * * * * * * * * * E Z

* * *

* * *

* * *

* * *

Z

S T Content CRCCMD

DAT0DAT[7:1]

E Z Z P P * * * P P * * * P

P * * * P

Z ZS T CRC EContent

D D D D D D D D D D E Z

Z

Z X * * * * * * * * * * * * * * * X Z Z

Host command

Z Z

CMD

DAT0DAT[7:1]

ZZ S T Content

Z Z

Z Z Z

Z Z Z

Z Z Z

Z Z Z


1

E

X

1

The following figure shows an example of a device transmitting the CRC status block tothe host, then being interrupted by a STOP_TRANSMISSION (CMD12) command sentby the host. This timing sequence is identical to all other STOP_TRANSMISSION timingexamples.




Figure 59: STOP_TRANSMISSION (CMD12) Timing During CRC Status Transmission to the Host

1

1

CRC status1Data block Busy (device is programming)


Data + CRC E Z Z S CRC E Z S L * * * * * * * * * * * * * * * * * * * * E

S T Content CRCCMD

DAT0DAT[7:1]

E Z Z P P * * * * * * P Z ZS T CRC EContent

Data + CRC E Z Z X * * * X Z

Z

Z X * * * * * * * * * * * * * * * * * * * * * X

Host command

E Z Z Z

CMD

DAT0DAT[7:1]

Z Z P P SE T Content

X Z Z Z

Z Z Z

Z Z Z

Z Z

Z Z


* * ** * *

Note: 1. The device CRC status response is interrupted by the host.

Previous STOP_TRANSMISSION (CMD12) timing examples showed the scenario of thehost stopping the data transmission during an active data transfer. The following figureshows a scenario where the device receives a CMD12 between data blocks when thedevice is busy programming the last block.




Figure 60: STOP_TRANSMISSION (CMD12) Timing After Last Data Block While Device is Programming

Busy (device is programming)


L * * * * * * * * * * * * * * * * * * * * * * * * * * * * * E Z

S T Content CRCCMD

DAT0DAT[7:1]

E Z Z P * * * P

Z * * * Z

Z * * * Z

P * * * * * * * * * * P

Z Z PP * *PS T CRC EContent

X

L

X * * * * * * * * * * * * * * * * * * * * * * * * * * * * * X

L

X Z

1

Host command

E Z Z Z

CMD

DAT0DAT[7:1]

P S T Content

X

L

X Z Z Z

Z Z Z

Z Z Z

Z Z

Z Z

1 Device activeHost active

The following figure shows a scenario where the host sends a STOP_TRANSMISSION(CMD12) command when the device is idle. However, there are still unprogrammed da-ta blocks in the input buffers. These blocks are programmed as soon as a CMD12 isreceived, and the device activates the BUSY signal.




Figure 61: STOP_TRANSMISSION (CMD12) Timing After Last Data Block When Device is Idle

1

NST Busy (device is programming)


Z Z Z Z Z Z Z Z Z Z Z S L * * * * * * * * * * * * * * * * E Z

S T Content CRCCMD

DAT0DAT[7:1]

E Z Z P P* * * Z Z PS T CRC EContent

Z Z Z Z Z Z Z Z Z Z Z X X * * * * * * * * * * * * * * * * X

L

X Z

1

E

CMD

DAT0DAT[7:1]

P

X

L

X


PP * *

P * * * * * * * * * * P

Host command

S T Content

Z * * * Z

Z * * * Z

Z Z Z

Z Z Z

Z

Z

Z Z Z Z

Z Z Z Z

In an open-ended WRITE_MULTIPLE_BLOCK operation, the BUSY signal between thedata blocks is considered to be a BUFFER BUSY signal. While no data buffer is available,the device pulls the DAT0 line LOW. The device returns DAT0 HIGH as soon as at leastone receiving buffer for the defined data transfer block length becomes available. Afterthe device receives the STOP_TRANSMISSION (CMD12) command, the next busy indi-cation is assumed to be a programming BUSY signal that is directly related to theprogramming state. As soon as the device completes the programming, it pulls theDAT0 line HIGH.

In a predefined WRITE_MULTIPLE_BLOCK operation, the BUSY signal between the da-ta blocks is considered to be a BUFFER BUSY signal, similar to the open-endedWRITE_MULTIPLE_BLOCK operation. After the device receives the last data block, thenext busy indication is assumed to be a PROGRAMMING BUSY signal that is directlyrelated to the programming state. The meaning of a BUSY signal (from BUFFER BUSYto PROGRAMMING BUSY) changes at the same time the state changes from receive da-ta to programming. The BUSY signal remains LOW throughout the process and is notreleased by the device between the state changes from receive data to programming. Assoon as the device completes the programming, it pulls the DAT0 line HIGH.




ERASE (CMD38), SET_WRITE_PROT (CMD28), CLR_WRITE_PROT (CMD29) TimingTo perform an ERASE operation, the host must first select the erase groups to be erasedusing the ERASE_GROUP_START (CMD35) and ERASE_GROUP_END (CMD36) com-mands. The host then issues the ERASE (CMD38) command, which erases all selectederase groups.

The SET_WRITE_PROT (CMD28) and CLR_WRITE_PROT (CMD29) commands start aPROGRAM operation in a similar way. The device asserts the BUSY signal by pulling theDAT0 line LOW for the duration of the ERASE or PROGRAM operation. The bus transac-tion timing is the same as that for the STOP_TRANSMISSION timing shown in Figure 61(page 193) in the previous section.

Reselecting a Busy DeviceWhen a busy device that is currently in the disconnect state is reselected, it reasserts theBUSY signal on the DAT0 line.




BUSTEST_W (CMD19) and BUSTEST_R (CMD14) TimingAfter reaching the transfer state, a host can initiate a bus test procedure by issuing theBUSTEST_W (CMD19) command. If the host receives no response, it should issue theSEND_STATUS (CMD13) command to read the device status. If there is no response toCMD19, the host can assume that the device does not support CMD19.

Figure 62: BUSTEST_W (CMD19) and BUSTEST_R (CMD14) Timing (example of 4-bit bus test)

1

Z Z * * * * * * * Z ZZ Z * * * * * * * Z Z 000000

Z Z * * * * * * * Z ZZ Z * * * * * * * Z Z 000000

Z Z * * * * * * * Z ZZ Z * * * * * * * Z Z 000000

Z Z * * * * * * * Z ZZ Z * * * * * * * Z Z 000000

Z Z * * * * * * * Z ZZ Z * * * * * * * Z Z Z Z * * * Z Z Z S 00 000000

NWR NRC NAC

CMD19 RSP19CMD

DAT0

DAT1

DAT2

DAT3

DAT[7:4]

CMD14 RSP14

X X X ES 10

X X X ES 01

X X X ES 10

X X X ES 01

S

S

01

01S

10

10S

1

CRC16 E Z Z * * * * * * *000000

CRC16 E Z Z * * * * * * *000000

CRC16 E Z Z * * * * * * *000000

CRC16 E Z Z * * * * * * *000000

* * Z Z

* * Z Z

* * Z Z

* * Z Z

* * Z Z CRC16 E Z Z * * * * * * *S 00 000000

NAC NRC

CMD

DAT0

DAT1

DAT2

DAT3

DAT[7:4]

CMD6

S

S

S

S

RSP14


01

01

10

10




Hardware Reset Timing

Hardware Reset Waveform

Figure 63: Hardware Reset Waveform

tRSTW tRSCAtRSTH

Host can issue bootinitiation or CMD1

Device starts a reset sequenceat the rising edge of RST_n

CLK

RST_n

DON'T CARE

Note: 1. The device detects the rising edge of the RST_n signal to trigger the internal reset se-quence.

Hardware Reset Noise Filtering TimingThe following are timing requirements for noise filtering during a hardware reset:

• The device must not detect 5ns or less of positive or negative RST_n pulse.

• The device must detect more than or equal to 1μs of positive or negative RST_n pulsewidth.

Figure 64: Hardware Reset Noise Filtering Timing

Device must not detectthese rising edges

RST_n

RST_n

≤5ns

≤5ns

4GB, 8GB, 16GB, 32GB: e·MMCHardware Reset Timing



Optional Features Not Supported by the DeviceThe following optional features are not supported in the device:

• High-priority interrupt (HPI) operation: Bit 0 in ECSD register byte 503 is set to 0.

• Background operation: Bit 0 in ECSD register byte 502 is set to 0.

• Enhanced reliable WRITE operation: Bit 2 in ECSD register byte 166 is set to 0.

• Double data rate (DDR) function: Bits[3:2] in ECSD register byte 196 are set to 0.

4GB, 8GB, 16GB, 32GB: e·MMCOptional Features Not Supported by the Device



Device Deviations From JEDEC v4.41 Specification (Errata)The devices include the following deviations from the JEDEC v4.41 specification.

Bus Test (CMD14/CMD19) at Low Frequency (<400 kHz)Bus testing should be done at the operating frequency. Bus testing below 400 kHz is notsupported.

Power Cycle Required for RST_n Signal EnabledAfter setting the RST_n _FUNCTION bit, a power cycle is required.

Cell Type of ERASE_GROUP_DEFThe cell type of ERASE_GROUP_DEF is RWE but not RWE_P. The device never clearsthe bit after a power cycle, hardware reset, and CMDO reset sequence.

No Erase Commands Supported in Boot PartitionsThe device does not support erase commands in boot partitions. Data can be overwrit-ten by write commands.

Limit to the Number of Step 1s in a SECURE TRIM Command Sequence (511 Max)In a SECURE TRIM operation, step 1 is used for marking sectors that need to be erased.This step can be executed for as many blocks as possible to improve the efficiency ofthe SECURE TRIM operation. Step 2 is the actual internal SECURE ERASE operation is-sued to the blocks specified by the sequences in step 1. However, the device supportsthis feature only when the host issues step 1 sequences less than 512 times before issu-ing the step 2 sequences.

RST_n SignalThe controller will reset only if there are at least 7 CLK pulses while RST_n is above VIH,after RST_n was below VIL. For example, a RESET operation will not occur under theconditions shown in Scenario 1 below. However, a RESET operation will occur (RST_nwill work properly) under the conditions shown in Scenario 2.

Figure 65: Scenario 1: e·MMC Device Fails to Reset

CLK

RST_n

CMD CMD174 clocks

4GB, 8GB, 16GB, 32GB: e·MMCDevice Deviations From JEDEC v4.41 Specification (Errata)



Figure 66: Scenario 2: e·MMC Device Resets

CLK

RST_n

CMD CMD174 clocks

>7 clocks

ECSD Values for Bytes[159:157] in ECSD Register (MLC e·MMC)The ECSD register (MLC e·MMC) shows an ECSD value of 0h for bytes[159:157]. Howev-er, the host can set any size of enhanced area within half of the original user area.

Boot Acknowledge Time (for MTFC8GKQxx and MTFC4GGQxx)tBAmax is 140ms for MTFC4GGQxx and 85ms for MTFC8GKQxx, instead of 50ms on adirty filled device.

CMD Line Kept LOW for BOOT Operation After Hardware Reset (RST_n) AssertedIf a hardware reset (RST_n) is asserted right after issuing CMD6 or CMD8 and then thehost uses boot mode (CMD line LOW for boot sequences), the device will send only onesector of data from the boot partition and will not send any more data, even though thehost toggles the clock signal. The workaround is to issue one of the following com-mands prior to asserting RST_n: CMD16, CMD17, CMD18, CMD24, or CMD25.

BUS_WIDTH and HS_TIMING Bits Not Reset by CMD0If PARTITION_ACCESS bits (ECSD[179] bits[2:0]) are not cleared by CMD6 after beingset, the next CMD0 or RST_n assertion will not clear BUS_WIDTH bits and HS_TIMINGbits. The workaround is to reset PARTITION_ACCESS bits (ECSD[179] bits[2:0]) withCMD6 before CMD0 is issued or RST_n is asserted.

CMD24 Interrupted by CMD12Interruption of a CMD24 operation by CMD12 can cause the device to hang during thenext CMD25 operation. The workaround is to use CMD25 + CMD12 or CMD23 +CMD25 instead of CMD24, or insert a READ command after CMD12 is issued.

Issuing ERASE Command to RPMB Partition ProhibitedThe device will not reject an ERASE command issued to the RPMB partition, eventhough an ERASE command can corrupt data in the RPMB partition. Therefore, do notissue an ERASE command to the RPMB partition.

SEC_BAD_BLK_MGMT (ECSD[134]) Not SupportedThe device does not support the functionality specified in SEC_BAD_BLKMGMT(ECSD[134]), even though the host sets the value to 1.

4GB, 8GB, 16GB, 32GB: e·MMCDevice Deviations From JEDEC v4.41 Specification (Errata)



Revision History

Rev. C, Production – 7/10

• CMD Line Kept LOW for BOOT Operation After Hardware Reset (RST_n) Asserted: Add-ed section.

• BUS_WIDTH and HS_TIMING Bits Not Reset by CMD0: Added section.

• CMD24 Interrupted by CMD12: Added section.

• Issuing ERASE Command to RPMB Partition Prohibited: Added section.

• SEC_BAD_BLK_MGMT (ECSD[134]) Not Supported: Added section.

Rev. B, Production – 6/10

• Figure: Power-On Sequence: Updated figure.

• DC Electrical Specifications – Power-On Sequence: Updated description.

• DC Electrical Specifications – RST_n Signal During Power-On Period: Updated descrip-tion.

• Device Deviations From JEDEC v4.41 Specification (Errata): Added Boot AcknowledgeTime (for MTFC8GKQxx and MTFC4GGQxx).

Rev. A, Production – 4/10

• Initial release.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900www.micron.com/productsupport Customer Comment Line: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

4GB, 8GB, 16GB, 32GB: e·MMCRevision History



Documents

4GB, 8GB, 16GB, 32GB: e·MMC - 4donline.ihs.com · e·MMC™ Memory MTFC4GGQDM, MTFC4GGQDI, MTFC8GKQDI, MTFC16GKQDI, MTFC32GKQDH Features • MultiMediaCard (MMC) controller and NAND