4-bit Shift Register

2-bit Register

Serial-in-serial-out Shift Register

Serial-in-parallel-out Shift Register

Synchronous Counter

Ring Counter

Up/down counterlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;-- up/down counterentity counterupdown is

port (load,reset, clk : in std_logic; -- control signaldir : in std_logic; --

directiond : in std_logic_vector (3 downto 0);q : out std_logic_vector (3 downto 0)

);end counterupdown;

architecture behave of counterupdown isbegina: process (clk,reset,d)

variable temp: std_logic_vector (3 downto 0);begin

if (clk'event and clk = '1') thenif (reset = '1') then

temp := "0000";elsif (load = '0') then

temp := d;else

if (dir = '1') thentemp := temp + "0001";

else temp := temp - "0001";end if; end if;

end if; q <= temp;end process a; end behave;

Waveform (up/down counter)

Binary counter

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity binarycounter is

port (clk : in std_logic;

q : out std_logic_vector (3 downto 0)

);

end binarycounter;

architecture behave of binarycounter issignal temp : std_logic_vector (3 downto 0);begina: process (clk)

beginif (clk'event and clk = '0') then

temp <= temp + "0001";end if;q <= temp;

end process a;end behave;

Waveform (binary counter)

Mod 2 counter

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity mod2 is

port (clk : in std_logic;

q : out std_logic_vector (3 downto 0)

);

end mod2;

architecture behave of mod2 issignal temp : std_logic_vector (3 downto 0);begina: process (clk)

beginif (clk'event and clk = '0') then

if (temp = "0010" ) thentemp <= "0000";

elsetemp <= temp + "0001";end if;

end if;q <= temp;

end process a;end behave;

Waveform (mod 2 counter)