Advanced Packaging

Antonio L. P. Rotondaro

Centro de Tecnologia da Informação Renato Archer

antonio.rotondaro@cti.gov.br++55-19-3746-6195

Outline/Agenda

� Introduction

� More Than Moore Era

� Challenges

� 2.5D and 3D Technologies

� SMT Trends

� Q & A

Looking Into the Future

“I think there is a world marketfor maybe five computers.”

Thomas Watson, chairman of IBM, 1943

“Computers in the future may weigh no more than 1.5 tons. ”

Popular Mechanics, 1949

“There is no reason anyone would want a computer in their home. ”

Ken Olsen, founder of DEC, 1977

“640K ought to be enough for anybody. ”

Bill Gates, 1981

“Prediction is difficult, especially about the future”

Yogi Berra

Moore´s Law

� Number of components for Minimum Cost doubles/year

� 50 in 1965; 1000 in 1970; 65000 in 1975…

Gordon E. Moore, Electronics, Vol.38, No.8 (1965)

Ongoing for 45 years...

Gordon E. Moore, Intel Seminar, (2005)

Market Pull

Advanced Packaging

� 3D Accelerates

� System-in-packaging (SiP) w/ stacking

� Package-on-package (PoP)

� Total package height (mm): 1.5 (2008) -> 1.2 (2012)

� Optical Accelerates

� Board, Module, Embedded -> Optics Ecosystem

� BW density (Gbps/cm2): 120 (2008) -> 400 (2012)

More Than Moore Era

R. R. Tummala, IEEE Spectrum, p. 44, (2006)

Packaging Technology Challenges

� Power Dissipation

� Thermal Issues

� Power Delivery

� Chip – Package – Interaction Crisis

� Larger Die + Organic Carrier + Pb-Free + Weak BEOL = CPI Crisis

� Bandwidth Demand

� I/O Density, Optical Interconnect, 3D Integration

Chip Carriers

� Glass Ceramic MCM

� Lines/spaces (µm): 125/60 (2008) -> 100/55 (2012)

� Flip-chip pitch (µm): 200 (2008) -> 170 (2012)

� Si Interposer

� TSV pitch (µm): 150 (2008) -> 20 (2012)

� Wafer Thickness (µm): 100 (2008) -> 10 (2012)

Interconnect & Assembly

� High Performance (Large Die, High I/O, High

Current)

� Pitch: 200µm Pb’d (2008) -> 185µm Pb-free (2012)

� Low Power (Small Die, Low I/O, Low Current)

� Pitch: 200µm Pb-free (2008) -> 125µm Pb-free (2012)

� Wire Bonding

� Bond pitch (µm): 110 (2008) -> 60 (2012)

� Wire diam (µm): Au/23 (2008) -> Au/15; Cu/19 (2012)

� BGA pitch (mm): 0.5 (2008) -> 0.3 (2012)

� Die thickness (µm): 60 (2008) -> 40 (2012)

2.5D and 3D Technologies

� Bandwidth ☺

� Power ☺

� Power �

� Cooling �

� Testing �

� KGD ☺

� Integration ☺

J.U. Knickerbocker et al., ECTC2012, pg.1068 (2012)

Terabit/sec 48-channel Optochip

� 20 Gb/s/ch

F.E. Doany et al., ECTC2012, pg.1499 (2012)

Coreless Substrate� Low z-height for mobile dev

� 4-4-4 cored vs 6+1 coreless

� 1.088mm vs 0.311mm

� Removal of PTH

� Removal of die side caps

M. Manusharow, et al., ECTC2012, pg.892 (2012)

� Re-design and optimization of the Power Distribution

� Total Copper thickness reduction

� Comparable IO performance

Solder Grid Array (SGA) vs BGA

� SGA by solder paste printing only

� BGA: h = 195µm

� SGA: h = 110µm

� Pitch: 0.5 mm

M.M Hossain, et al., ECTC2012, pg.43 (2012)

� SGA cored lower TCT than BGA cored

� Temp -40C to 100C at 1hr cycle time

� Solder Joint issues

Process Optimization

� Pb-Free -> Increase in reflow temp

� Reduced Yield margin

� Increase in paste volume

� Controlled by stencil opening

� Uniform collapse and good solder joint

� Reflow atmosphere

� N2 promotes wetting by reducing surface tension and prevents oxidation

� Coreless has higher reliability due to lower

effective shear strain

Potential of 3D IC Integration

C.-J. Zhan, et al., ECTC2012, pg.548 (2012)

Antonio L. P. Rotondaro, Ph.D.

Centro de Tecnologia da Informação Renato Archer

antonio.rotondaro@cti.gov.br++55-19-3746-6195

Thank You!

Boards & Interconnect

� Drilled via aspect ratio: 17 (2008) -> 21 (2012)

� Effective dielectric loss: 0.010 (2008) -> 0.005

(2012)

� BGA via pitch (mm): 1.0 (2008) -> 0.5 (2012) @

>900 I/O

� Pb-free

� Optics with embedded passives