An Integrated Silicon Photonics Technology for O-band Datacom

N. B. Feilchenfeld#1, F. G. Anderson#, T. Barwicz, S. Chilstedt#1, Y. Ding#1, J. Ellis-Monaghan#1, D. M. Gill, C. Hedges#1, J. Hofrichter*, F. Horst*, M. Khater, E. Kiewra, R. Leidy, Y. Martin, K. McLean#1, M. Nicewicz#1, J. S. Orcutt, B. Porth#1, J.

Proesel, C. Reinholm, J. C. Rosenberg, W. D. Sacher, A. D. Stricker, C. Whiting, C. Xiong, A. Agrawal, F. Baker, C. W. Baks, B. Cucci#1, D. Dang#1, T. Doan#1, F. Doany, S. Engelmann, M. Gordon#1, E. Joseph, J. Maling#1, S. Shank#1, X. Tian#1, C.

Willets#1, J. Ferrario#1, M. Meghelli, F. Libsch, B. Offrein*, W. M. J. Green, W. Haensch #IBM Systems & Technology Group, Microelectronics Division, 1000 River St., Essex Junction, Vermont 05452, USA

IBM T. J. Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, New York 10598, USA *IBM Research GmbH, Säumerstrasse 4, CH-8803 Rüeschlikon, Switzerland

1 to GLOBALFOUNDRIES, Essex Junction, Vermont, 05452, USA Tel: (802) 769-7014, Fax: (802) 769-9659, Email: feilchen@us.ibm.com

Abstract: A manufacturable platform of CMOS, RF and opto-electronic devices fully PDK enabled to demonstrate a 4x25 Gb/s reference design is presented. With self-aligned fiber attach, this technology enables low-cost O-band data-com transceivers. In addition, this technology can offer en-hanced performance and yield in hybrid-assembly for appli-cations at 25 Gbaud and beyond. Introduction: Monolithic CMOS silicon photonics technology promises single-chip integration benefits of unified design verification, wafer-level test and low-cost assembly [1]. However, to date this approach has not been used to manufacture O-band 25 Gb/s coarse wavelength division multiplexed (CWDM) transceivers at the center of standardization for datacom applications. Hybrid integration promises the advantages of CMOS manufacturing for optical components [2], but lacks full electro-optic device and system integration. Here, we present a manufacturable platform of CMOS, RF and optoelectronic devices fully PDK-enabled to demonstrate a 4x25 Gb/s reference design. With self-aligned fiber attach [3,4], this technology enables low-cost O-band datacom transceivers. In addition, this technology can offer enhanced performance and yield in hybrid-assembly for applications at 25 Gbaud and beyond. Technology features: The 90nm silicon-on-insulator (SOI) CMOS process is tailored to a manufacturable design point for applications up to 25 Gbaud with the addition of photon-ic and RF process modules (Figure 1). The standard FETs are built in a dual oxide process with parametrics in Table 1, and used for a standard cell logic library. To enable high-speed analog circuits the gate length of the standard FETs is reduced, and precision polysilicon resistors (8% tolerance), a bandgap diode, capacitors and inductors are added with hardware-based RF models. eFuses are also included to ena-ble design customization post-test. In addition to hardware-based models, the PDK includes design rule checking of layouts and layout verification tools. The photonics portion of the PDK includes device pcells, routing tools, and models which can be employed in industry standard CMOS design environments. The models include parameter statistics based on actual process line correlation. Parameters and equations used in the models are documented, as is the mod-el-to-hardware correlation, shown in Figure 2 for the power

coupling ratio in a standard optical directional coupler. The PDK of this technology also features an electrostatic dis-charge (ESD) design kit with fully modeled scalable RC-triggered power rail clamps, ESD diodes, ESD gg-NMOS FETs, self-protected FETs, as well as a bipolar ESD clamp. The technology's ESD reference guide helps the user to choose the desired protection level without adding unneces-sary parasitic capacitances and resistances into the signal path.

Figure 1: CMOS process flow with RF and photonic modules added. Ele-ments of the baseline process that have been optimized for photonic device performance are indicated with *

Table 1: FET parametrics for body contacted (BC) and floating body (FB) devices for 1.2V (nominal) and 3.3V operation. Ion measured |VD|=|VG|=1.2V/3.3V, VB=0V (includes self heating); Ioff measured at |VD|=1.2V/3.3V, |VG|=0V, VB=0V.

Shallow Trench*

Well Dual Gate

Precision Resistor

Spacer*-Halo

SilicideContact-Metals

S/D anneal

Photonic Trench

Modulator Implant

ModulatorModule

GeDetector

Thick Al Metal Optical

Connect

RF CMOS Photonic

Detector Implants

Lpoly (nm) Ion ( A/ m) Ioff (nA/ m) LVT FB NFET 55 815 100 LVT FB PFET 55 -390 -40 RVT FB NFET 55 770 30 RVT FB PFET 55 -340 -12 RVT BC NFET 55 700 3.5 RVT BC PFET 55 -310 -2 3.3V BC NFET 400 550 -0.02 3.3V BC PFET 400 -250 -0.15

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Figure 2: Model-to-hardware correlation for the optical power ratio at the outputs of a standard directional coupler, as a function of geometric coupl-ing length. Two independent measurements are included Manufacturing for photonic device optimization: Since the active device silicon layer also functions as an optical waveguide, several front-end process steps have been altered for photonic device performance. Examples include optimiz-ing the STI etch process for more vertical sidewalls, and improving the spacer etches to minimize erosion of the sili-con, reducing propagation loss by 1 dB/cm for fully etched waveguides compared to an earlier process. Moreover, a common module for the first level of contact vias was opti-mized to yield CMOS devices (with silicide) and germanium photodetector (without silicide/germanide). The via etch, wafer cleans, and thermal anneals within this contact module were optimized to maintain CMOS performance and to achieve a low germanium photodetector dark current. In addition, active thermal tuning of the CWDM multiplex-er/demultiplexer devices guarantees manufacturability for a wide variety of applications, Figure 3.

. Figure 3: CWDM transmission characteristics after thermal tuning for the (a) first-order multiplexer, and (b) second-order demultiplexer.

Fabrication of CMOS devices and silicon photonic compo-nents on the same substrate has been facilitated through the use of an integrated data preparation flow for generation of mask reticles. Control of critical dimensions for both elec-trical and optical devices has been enabled by data prepara-tion and optical proximity correction (OPC) algorithms spe-cifically refined to be compatible with printing the curved design shapes typically employed in photonic waveguides, simultaneously with the rectilinear shapes found in CMOS devices. Automated electro-optical test: Statistical optical data is obtained for a given device under test (DUT) by arranging the DUT in a cut back measurement, consisting of up to 4 geometrical lengths, Figures 4a-b). The histogram of repre-sentative measurements for both the fully and partially etched silicon optical waveguides over multiple mask de-signs and wafer lots is shown in Figures 4 c-d). Similar test structures are utilized to characterize modulator V L, ther-mo-optic phase shifter efficiency, detector responsivity, WDM passbands and crosstalk, directional coupler coupling length, and other active and passive device parameters.

Figure 4: (a) Schematic of in-line electro-optical test module with 1x4 opti-cal and 1x25 electrical pad sets for fully automated wafer level testing. (b) Example cut back measurement for the fully etched waveguide device under test (DUT) on five sites. Measurements of propagation loss on (c) 336 fully etched and (d) 326 partially etched waveguide test structures across 75 wafers in 8 lots, with mean and 3 sigma values as shown. The insets illu-strate the cross-section of the SOI waveguide core.

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Table 2: PN-junction phase shifter propagation loss, VπMZM doping dose, at a -0.5 V bias. * FOM = PN-junmeasured by the electro-optic automated tester) x Vπ-L

Prop Loss (dB/cm)

Vπ-L (V-cm)

Nominal MZM Dose

8.9 1.58

1.3*Nominal MZM Dose

11.1 1.48

Figure 5: (a) Micrograph of standalone monolithic MZMequivalent to the design TX 4 shown in Fig. 10. (b) CorrGb/s TX optical eye diagram.

Figure 6: Monolithic PAM-4 transmitter based on a twoThe 25 Gbaud (50 Gb/s) PAM-4 transmitter eye is showwith a 6.0 dB extinction ratio.

π-L, and FOM versus ction optical loss (as sensitivity

FOM (V-dB)* 14.0

16.4

M TX, which is responding 25.8

o-segment MZM. wn in the upper right

Germanium PIN diode: To imprthe germanium rapid-melt regrowimplants are introduced after the so1. Detector leakage is suppressed b-0.8V bias, Figure 7a. The electricshown in Figure 8 illustrates a 25 °99.5%. Responsivity across the strates TE/TM polarization dependthe range of 0.58-0.71 A/W, Figurefiber-coupled receivers.

Figure 7: (a) Temperature-dependent dark cuphotodiodes; (b) Average wavelength- and psivity for 4 germanium photodiodes.

Figure 8: Leakage histogram for germanileakage is 99.5%, with 992 diodes tested fro

Polarization management: Adiaband rotators (PSR) leverage the avlayers for WDM-required polarizimplementations exhibit insertion dB and cross-talk better than -20 dBFiber to chip coupling: V-grooveson-chip enable self-alignment to wof standard cleaved fibers to integfiber couplers are metamaterial spended over a silicon handle undersion beyond the limited buried oThe convertors were shown in [4]coupling efficiency to a standard cpenalty over a 100 nm bandwidth a

-1 0 110-9

10-8

10-7

10-6

10-5

10-4

Voltage (V)

Dar

k C

urre

nt (A

)

(a) (b

0

0

Res

pons

ivity

(A

/W) 0

0.0 0.2 0.40

45

90

135

180

Cou

nt

25°C Diode Leakage C

rove manufacturability of wth detectors, p+ and n+ ource-drain anneal, Figure below 2 μA at 125 °C and cal diode yield histogram °C <1 μA leakage yield of O-band window demon-

dence less than 0.5 dB, in e 7b. This enables directly

urrent curves for 10 germanium polarization-dependent respon-

ium detector. Yield for <1 μA om 19 wafers.

batic polarization splitters vailable CMOS structural zation diversity. Various loss between 0.3 and 1.5

B. s monolithically integrated within +/- 1.3 um (3 ) [3] grated fiber couplers. The spot-size convertors sus-rcut to allow mode expan-xide thickness, Figure 9. ] to offer a -1.3 dB peak cleaved fiber with 0.8 dB

and all polarizations.

b)

1265nm TE TM1310nm TE TM1350nm TE TM

-1 -0.5 00.5

0.6

Voltage (V)

0.7

0.6 0.8 1.0urrent @ 0.8V (μA)

OCZeatPN(FthdBed14mGintesuoptoan

Optical transmMOS driver ehnder modulation (bit-error N-junction phFOM), Table 2he simple multiB/cm), as mead tester, and th4 V-dB with a

monolithic standGb/s eye diagransertion loss aners are enableduch as PAM-4 ptical TX is baor that performnd operates at b

mitters: The trmonolithically

ator (MZM), anrate <10-12) o

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ased on a segmms the optical bit rates up to 5

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Figure 9: Top-view optical micrograph of a fiber to chip interface. The metamaterial fiber coupler is embedded in a suspended oxide membrane.

Reference design demonstration: A monolithic 4x25 Gb/s reference design was completed with a hardware-verified Foundry PDK. Support for industry-standard tools facilitated full circuit simulation for the complete electro-optic system. The hardware-based device models include temperature and wavelength dependence. The die was assembled using C4 attach and optical connection via vertical grating couplers for an on-chip loop-back link test. The transmit and receive subsystems, for which a design skew across channels was included, are shown in Figs. 10 and 11 respectively. Error-free transmission was verified for the TX1 to RX4 link at 25 Gb/s using a PRBS31 data pattern.

Figure 11: Receive side of loopback on-chip link for receivers 1-4 measured independently using channel TX 1 at 25 Gb/s. Due to TE input from the on-chip link, the TM path demux is not illuminated. The waveguide routing post-demux balances timing skew between channels. Conclusions: A monolithic CMOS photonic platform that is optimized for manufacturable O-band datacom transceivers is presented with 4x25 Gb/s link functionality demonstrated. The photonics process modules used to construct the photon-ic devices are transferable to other CMOS lithographic nodes directly when the SOI thickness is matched, either by the use of an identical SOI starting wafer, or by a hybrid substrate construction where the ‘photonic’ silicon thickness is maintained. The integration of the process modules would be unique to each CMOS process flow. Acknowledgements: The authors are grateful for support from the IBM Microelectronics PDK Enablement Group: Andrea Paganini and Yves Ngu (CMOS passive modelers), Jude Hankey and Steven Mixon (DRC), Derrick Kunze (LVS), and Jiansheng (Jason) Xu (PEX), as well as from the IBM Microelectronics Research Laboratory and Central Scientific Services. Tim Buchholtz, Ladd Freitag, Ray Ri-chetta, and the IBM Rochester team are recognized for their contributions to the development of the reference design. The authors also thank Daniel Kuchta for assistance with high-speed characterization, and Yurii Vlasov for his contin-ued support. References [1] S. Assefa, et al., IEDM, 2012, 33.8.1. [2] F. Boeuf, et al., IEDM 2013, 13-353. [3] T. Barwicz, et al., Proc of ECTC 2015, pp. 775-782. [4] T. Barwicz, et al., OFC 2015, Th3F.3. [5] D. M. Gill, et al., CLEO 2015, STuF-3. [6] C Xiong et al., IEEE OI 2015, MC3

Figure 10: Transmit side of loopback on-chip link for transmitters 1-4 measured independently using channel RX 4 at 25 Gb/s.

FiberV-groove 30 um

Metamaterialcoupler

Non-suspended region

Suspended region

Venting hole

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