2000-Jour-A Phase Tracking System for Three Phase Utility Interface Inverters

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 15, NO. 3, MAY 2000 431

A Phase Tracking System for Three Phase UtilityInterface Inverters

Se-Kyo Chung, Member, IEEE

Abstract—The analysis and design of the phase-locked loop(PLL) system is presented for the phase tracking system of thethree phase utility interface inverters. The dynamic behavior ofthe closed loop PLL system is investigated in both continuous anddiscrete-time domains, and the optimization method is consideredfor the second order PLL system. In particular, the performanceof the three phase PLL system is analyzed in the distorted utilityconditions such as the phase unbalancing, harmonics, and offsetcaused by the nonlinear load conditions and measurement errors.The tracking errors under these distorted utility conditions arealso derived. The phase tracking system is implemented in adigital manner using a digital signal processor (DSP) to verify theanalytic results. The design considerations for the phase trackingsystem are deduced from the analytic and experimental results.

Index Terms—Phase-locked loop, utility interface.

I. INTRODUCTION

A S increasing demands for the high quality, reliability, andusability of electric power source, the utility interface op-

eration of power converters is often used in advanced powerconversion and conditioning systems such as the static VARcompensators, active power filters, uninterruptible power sup-plies (UPS’s), and grid-connected photovoltaic or wind powergeneration systems [3]. Since the control of the power factor iscommon goal of these systems and requires the accurate phaseinformation of the utility voltages, the phase tracking system isone of the most important parts of these systems.

The phase-locked loop (PLL) technique has been used as acommon way of recovering and synthesizing the phase and fre-quency information in electrical systems [1], [2]. In the area ofpower electronics, the PLL technique has been adopted in thespeed control of electric motors [5], [6]. This is also availablefor synchronizing the utility voltages and the controlled currentsor voltages in utility interface operation of power electronic sys-tems. A simple method of obtaining the phase information is todetect the zero crossing point of the utility voltages [1]. How-ever, since the zero crossing point can be detected only at everyhalf cycle of the utility frequency, the phase tracking action isimpossible between the detecting points and thus the fast dy-namic performance can not be obtained. An improved method isthe technique using the quadrature of the input waveform shiftedby 90� [1]. This technique has been often employed in the var-

Manuscript received February 15, 1999; revised December 20, 1999. Recom-mended by Associate Editor, A. Kawamura.

The author is with the Department of Control and Instrumentation Engi-neering, Research Institute of Industrial Technology, Gyeongsang NationalUniversity, Kyungnam 660-701, Korea (e-mail: [email protected]).

Publisher Item Identifier S 0885-8993(00)03382-2.

Fig. 1. Block diagram of three phase PLL system.

ious applications for the phase or position detecting [7]. In thethree phase systems, thedq transform of the three phase vari-ables has the same behaviors with this technique and the PLLsystem can be implemented by using thedq transform and ap-propriate loop filter.

This paper describes the characteristics of the three phasePLL systems and discusses the proper design method. Espe-cially, the performance of the PLL system is analyzed and thetracking errors are derived for the distorted utility conditionssuch as the phase unbalancing, harmonics, and offset. Besidesthe analytic studies, the experimental verifications are carriedout using the digital signal processor (DSP) system under var-ious utility conditions. Through these analytic and experimentalworks, the important considerations are provided for the designof the phase tracking system in the three phase utility interfaceinverters.

II. THREE PHASE PLL SYSTEM

The block diagram of the three phase PLL system can be de-scribed as shown in Fig. 1. In this system, the three phase utilityvoltages can be represented as

vabcs = Vm �

0BBBB@

cos �

cos

��

2�

3

�

cos

�� +

2�

3

�

1CCCCA : (1)

wherevabcs = [vas vbs vcs]T . Under the assumption of the

balanced utility voltage, (1) can be expressed in the stationaryreference frame as

v�� = Ts � vabcs (2)

0885–8993/00$10.00 © 2000 IEEE

432 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 15, NO. 3, MAY 2000

Fig. 2. Linearized model of three phase PLL system.

wherev�� = [v� v�]T andTs denotes the transform matrixgiven by

Ts =2

3�

0@ 1 �1

2�1

2

0 �p3

2

p3

2

1A : (3)

These can be rewritten in the synchronous reference frame usingthe PLL output� as

vqde = Te(�) � v�� (4)

wherevqde = [vqe vde]T andTe(�) denotes the rotating matrixgiven by

Te(�) =

�cos � � sin �sin � cos �

�: (5)

The voltage of interest is thed-axis component and derived as

vde = Em sin �

= e (6)

whereEm = �Vm and� = � � �. The angular frequency ofthe PLL system can be represented as

! =d�

dt= Kf � e (7)

whereKf denotes the gain of the loop filter. If it is assumed thatthe phase difference� is very small, (6) can be linearized as

e �= Em�: (8)

Hence, the PLL frequency! and phase� can track the utilityfrequency! and phase angle�, respectively, by the proper de-sign of the loop filter.

III. CLOSED LOOPSYSTEM

A. Second Order Loop in Continuous-Time Domain

The linearized model of the three phase PLL system can bedescribed as shown in Fig. 2. The transfer function of the closedloop system can be represented as

Hc(s) =�(s)

�(s)=

Kf (s)Em

s+Kf (s)Em

(9)

H�(s) =�(s)

�(s)=

s

s +Kf (s)Em

(10)

where�(s); �(s), and�(s) denote the Laplace transform of�; �, and�, respectively. There are various methods in designingthe loop filter. The second order loop is commonly used as a

Fig. 3. Discrete-time domain model of three phase PLL system.

good trade-off of the filter performance and system stability [1].The proportional-integral (PI) type filter for the second orderloop can be given as

Kf (s) = Kp ��1 + s�

s�

�(11)

whereKp and � denote the gains of the PI type filter. Thetransfer functions of the closed loop system are rewritten in thegeneral form of the second order loop as

Hc(s) =2�!ns + !2

n

s2 + 2�!ns + !2n

(12)

H�(s) =s2

s2 + 2�!ns + !2n

(13)

where

!n =

rKpEm

�; � =

KpEm

2!n=

p� �KpEm

2:

B. Second Order PLL in Discrete-Time Domain

Since the PLL system is implemented in a digital mannerusing a digital signal processor (DSP), the discrete-time modelis more useful than the continuous-time one. The block dia-gram of the PLL system in the discrete-time domain is shown inFig. 3. The blockKdz is thez-transform of the loop filter andvoltage-controlled oscillator (VCO). The closed loop transferfunction can be represented as

Hc(z) =�(z)

�(z)=

EmKd(z)

1 +EmKd(z): (14)

For the second order loop using the PI type filter,Kd(z) can beobtained as

Kd(z) = Kp

z(z � �)

(z � 1)2(15)

where� = 1� T=� andT denotes the sampling period of thedigital system. The transfer function of the closed loop systemin the discrete-time domain can be derived by substituting (15)into (14) as

Hc(z) = Hcm �z(z � �)

z2 � az + b(16)

where

Hcm =EmKp

1 +EmKp

; a =2 +EmKp�

1 + EmKp

; b =1

1 +EmKp

:

CHUNG: PHASE TRACKING SYSTEM FOR THREE PHASE UTILITY INTERFACE INVERTERS 433

Fig. 4. Root loci of discrete-time PLL system with second order.

Fig. 4 shows the root loci of the closed loop system. WhenT >2� , the closed loop system is unstable in which the open loopzero� is located at the outside of unit circle.

C. Optimization of Closed Loop Performance

It should be considered in the design of the closed loop systemthat the dynamic performance satisfies the fast tracking andgood filtering characteristics. However, both requirements cannot be satisfied simultaneously because these two conditions areinconsistency. Therefore, a trade-off is required in designing ofthe dynamic behavior of the PLL system.

One of the most widely used techniques is the Wiener method[1], which is known as the best optimization method. For thesecond order loop, the transfer function is given as

Hc(s) =

p2!ns + !2n

s2 +p2!n + !2n

: (17)

From (12), the damping ratio can be derived as� = 0:707 in thisoptimization method. The closed loop bandwidth of the PLL canbe determined by using the stochastic information of the signaland noise, and can be given in the Wiener method as

!2n = �!�

r2PsWo

(18)

where�! is the deviation of the frequency,Ps is the input signalpower,Wo is the input noise spectral density, and� is the La-grangian multiplier that determines the relative proportions ofthe noise and transient error. However, because it is very diffi-cult to estimate the stochastic information of the noise and thisrelation does not provide the optimum results under the distortedvoltage waveform, the empirical trade-off is used as mentionedbelow.

The steady state performance of the PLL system is related tothe shape of the input and the order of the loop filter. The errorscan be derived from (10) and (13). In the second order PLL, theerrors for three types of input are summarized in Table I, where�_! denotes the deviations of the acceleration. It is shown inthis table that the PI type second order PLL has the steady stateerror, known as the tracking error, for the step change of theacceleration which the frequency varies in time.

TABLE ISTEADY STATE ERRORS FORTHREE TYPES

OF INPUT

Fig. 5 shows the simulated results of the proposed PLLsystem with the Wiener optimization when the naturalfrequency!n = 628 [rad=sec]. The gains of loop filter are cal-culated from (12) and (17) asKp = �2:85 and� = 0:002247for Vm = 311 [V]. In this case, the input is the step changeof the frequency from zero to 60 [Hz] and the error convergesto zero in the steady state. When the frequency varies in time,the second order PLL shows the tracking error. This errorcan be reduced by choosing the higher natural frequency thatgives the higher bandwidth as shown in Table I. However, theuse of higher bandwidth does not provide better results in allconditions. In some practical cases such as the distorted utility,the tracking error increases as the bandwidth increases. There-fore, the selection of the bandwidth is a compromise betweenvarious factors, which will be discussed in next chapters.

IV. ERRORANALYSYS FOR DISTORTEDUTILITY

In practice, the utility voltage is not pure sinusoid but dis-torted by the various external factors such as the nonlinearitiesof the load and measurement devices and the signal conversionerrors, which results in the phase unbalancing, harmonics, andoffset. The distorted utility waveform causes various types ofthe error in the PLL system, which degrade the control perfor-mance of the utility interface inverter system. The errors causedby the distortion of the utility voltage are derived in this chapter.

A. Phase Unbalancing

The utility voltage considering the unbalanced phase can begiven as follows:

vas =Vm cos � (19)

vbs =Vm(1 + �) cos

��

2�

3

�(20)

vcs =Vm(1 + ) cos

�� +

2�

3

�(21)

where� and are constants. These can be rewritten in the sta-tionary reference frame using (3) as

v� =Vm cos � + Vm

�� +

6cos � �

� �

2p3

sin �

�(22)

v� = � Vm sin � + Vm

��

2p3

cos � �� +

2sin �

�: (23)


Fig. 5. Simulated results of three phase PLL system (� = 0:707; !n = 628

rad/sec). (a) Angular position. (b)d-axis voltage. (c) Sine functions using� and�.

The second terms of the right hand side of (22) and (23) areproduced by the phase unbalancing. Thed-axis voltage after thedq transform using (5) can be derived as

vde = Em sin � �Em

��

2p3(cos � cos � � sin � sin �)

+� +

6(sin � cos � + cos � sin �)

�(24)

Under the assumption that the error� = �� is very small and� + � �= 2�, (24) can be simply represented as

vde �= Em� � Em

��

2p3

cos 2� +� +

6sin 2�

�(25)

or

vde �= Em� � EmEpu cos(2� + �pu) (26)

where

Epu =

s��

2p3

�2

+

�� +

6

�2

;

�pu = � tan�1�

1p3

� +

� �

�:

Since thed-axis voltage is controlled to zero by the PI typeloop filter, the resultant error caused by the phase unbalancingis given as

� �= Epu cos(2� + �pu): (27)

It is noted that the phase unbalancing produces the error with2! frequency component, where! is the frequency of the utilityvoltage as! = d�=dt.

B. Voltage Harmonics

The source of the voltage harmonics can be considered as thenonlinearities of the measurement devices and nonlinear loadsuch as the rectifier load. The utility voltage with harmonics canbe represented as follows:

vas =V1 cos � + V5 cos 5� + V7 cos 7� + � � � (28)

vbs =V1 cos

��

2�

3

�+ V5 cos 5

��

2�

3

�

+ V7 cos 7

��

2�

3

�+ � � � (29)

vcs =V1 cos

�� +

2�

3

�+ V5 cos 5

�� +

2�

3

�

+ V7 cos 7

�� +

2�

3

�+ � � � (30)

whereV1; V5; V7; . . . denote the magnitude of the harmoniccomponents. The stationary frame representations of (28)through (30) are given as

v� =V1 cos � + V5 cos 5� + V7 cos 7� + � � � (31)

v� = � V1 sin � + V5 cos 5� � V7 cos 7� + � � � (32)

Thed axis voltage can be derived by using (5) and the assump-tion of the small� as

vde = �V1 sin � + V5 sin(� + 5�) + V7 sin(� � 7�) + � � ��= �V1� + (V5 � V7) sin 6� + (V11 � V13) sin 12� + � � �(33)

Therefore, the error caused by the utility harmonics can be rep-resented as

� = Eh6 sin 6� + Eh12 sin 12� + � � � (34)


where

Eh6 =V5 � V7

V1; Eh12 =

V11 � V13

V1; � � � :

It is noted in (34) that the utility harmonics causes the errorwith the frequency components of6!;12!; . . . ; which is themultiples of six of the utility frequency.

C. Voltage Offset

The voltage offset is often produced by the offset of the signalmeasurement and conversion circuits. The utility voltage withthe offset can be expressed as

vas =Vm cos � + Vao (35)

vbs =Vm cos

��

2�

3

�+ Vbo (36)

vcs =Vm cos

��

2�

3

�+ Vco: (37)

These voltages can be transformed using (3) as follows:

v� =Vm cos � + V�o (38)

v� =Vm cos � + V�o (39)

where

V�o =2

3(Vao + Vbo + Vco); V�o =

1p3(Vco � Vbo):

Thed-axis voltage in the synchronous frame can be representedusing (5) and the assumption of small� as

vde = �Vm sin � + V�o sin � + V�o cos ��= Em� + Eo cos(� + �o) (40)

where

Eo =qV 2�o + V 2

�o; �o = � tan�1�V�o

V�o

�:

Therefore, the error caused by the voltage offset can be shownas

� �= Edo cos(� + �o) (41)

where

Edo = �Eo

Em

:

It is shown in this result that the error caused by the offset hasthe same frequency component with that of the utility voltage.

V. EXPERIMENTS

A. Implementation

Fig. 6 shows the experimental setup for the proposed threephase PLL system, which consists of the DSP TMS320C31system with a clock frequency of 40 [MHz] and the arbitrarythree phase voltage generator [8], [9]. The proposed PLLscheme is implemented in the software of the DSP and thesampling frequency is set as 15 [kHz]. The three phase voltagesare measured by the isolation transformer and the measuredsignals are converted to digital ones using the analog-to-digital

Fig. 6. Experimental steup for theree phase PLL system.

(A/D) converters with the resolution of 12 bits. The arbitraryvoltage generator can produce various conditions of the utilityvoltage such as the phase unbalancing, harmonics, and offset,which can be used to test the performance of the PLL system.

B. Experimental Results and Discussions

Fig. 7 shows the responses of the proposed PLL system whenthe closed loop bandwidth are chosen as 50 [Hz], 100 [Hz], and1 [kHz], i.e.!n = 314; 628, and6280 [rad/sec], respectively,where the damping ratio is chosen as� = 0:707 and the peakof the utility voltageVm is 311 [V]. Under these conditions, thegains of the loop filter are given asKp = 1:43; 2:85, and28:5,and � = 0:004506; 0:002247, and0:0002251, respectively.It is shown in Fig. 7 that the higher bandwidth gives the fasterdynamic response.

Fig. 8 shows the PLL errors under the phase unbalancing ofthe utility voltage. The voltages of the phasesb andc are givenas 90% and 110% of the phasea. As derived in (27), it is shownthat the errors caused the phase unbalancing have2! frequencycomponent. It can be also noted in this figure that the magnitudeof the error is reduced as the bandwidth decreases. The error in50 [Hz] bandwidth is about 50% of that in 1 [kHz] bandwidth.This is the low pass filtering effect of the loop filter and it isknown that the lower bandwidth is more effective to reduce theerror caused by the phase unbalancing.

The responses of the PLL system under the voltage harmonicsare shown in Figs. 9 and 10, where the fifth and seventh har-monics are given as 5% and 3% of the fundamental voltage,respectively. Figs. 9 and 10 show the time responses and fre-quency spectrums, respectively. It is shown in Fig. 9 that errorhas the frequency component of6! as shown in (34). The lowpass filtering effect is also shown and thus the magnitude of theerror decreases as the bandwidth decreases. Fig. 10 shows thefrequency spectrums of the utility voltage andcos � using thePLL output. It is noted that the fifth and seventh harmonics arereduced as the bandwidth decreases.

Fig. 11 shows the responses of the PLL under the voltageoffset. The dc voltage, which is 10% of the peak utility voltage,is added to the phasea. It is shown in this figure that the error hasthe same frequency component with that of the utility voltage asshown in (41). Since the frequency of the error is relatively low,the low pass filtering effect of the loop filter can not be expected.The extremely low bandwidth can provide the filtering effect.However, this degrades the dynamic performance.


Fig. 7. Resposens of three phase PLL system (va = Vm cos �; Vm = 311 V). (a) !n = 314 rad/sec,� = 0:707. (b) ! = 628 rad/sec,� = 0:707. (c)!n = 6280 rad/sec,� = 0:707.

VI. CONCLUSION

The analysis and design of the three phase PLL system for theutility interface inverter have been presented in this paper. Thedynamic modeling, characteristics, and optimization of the threephase PLL system have been discussed. Particularly, the errorscaused by the distorted utility voltage have been analyzed. Fromthe analytic and experimental studies, the design considerationsof the three phase PLL system can be deduced.

The PLL system consists of two major parts, the phasedetecting devices and loop filter. The phase detecting can bereadily implemented by using thedq transform in the threephase system without additional phase detecting devices. Thedesign parameters of the loop filter are the damping ratio�

and the natural frequency!n, which determines the dynamiccharacteristics. The damping ratio can be chosen by the Wienermethod that has been generally accepted as the best optimiza-


Fig. 8. Errors of three phase PLL system under phase unbalancing (va =

Vm cos �; Vm = 311 V). (a) !n = 314 rad/sec,� = 0:707. (b) !n = 628

rad/sec,� = 0:707. (c) !n = 6280 rad/sec,� = 0:707.

tion. The bandwidth of the loop filter is a trade-off betweenthe filtering characteristics and fast responses. While the higherbandwidth ensures the faster dynamic responses, the trackingerror is increased under the distorted utility conditions. The er-rors caused by the phase unbalancing and harmonics have thefrequency components of2! and multiples of6!, respectively,

Fig. 9. Errors of three phase PLL system under voltage harmonics (va =

Vm cos �; Vm = 311 V). (a) !n = 314 rad/sec,� = 0:707. (b) !n = 628

rad/sec,� = 0:707. (c) !n= 6280 rad/sec,� = 0:707.

and can be considerably reduced by using the loop filter withthe low bandwidth. The errors caused by the voltage offset arethe same frequency with that of the utility voltage. In order toreduce this error by the loop filter, the extremely low bandwidthis required. However, this degrades the dynamic performanceand is not acceptable.


Fig. 10. Frequency spectrums of utility voltage andcos � under utilityharmonics for various bandwidths.

Fig. 11. Errors of three phase PLL system under voltage offset(va = Vm cos �;Vm = 311 V, !n = 314 rad/sec,� = 0:707).

Consequently, the errors caused by the phase unbalancing andharmonics can be reduced by the appropriate design of the loop

filter and the bandwidth is a compromise between the filteringperformance and fast response. For more efficient filtering char-acteristics, the high order PLL system can be considered. Sincethe error caused by offset can not be handled in the loop filter,it should be eliminated in the stage of the voltage measurementand phase detection.

In order to more improve the PLL performance under thedistorted utility conditions, several techniques will be consid-ered such as the high order PLL and adaptive cancellation tech-niques. These are being considered as further works.

REFERENCES

[1] F. M. Gardner,Phaselock Techniques. New York: Wiley, 1979.[2] B. Razavi,Monolithic Phase-Locked Loop and Clock Recovery Cir-

cuit. New York: IEEE Press, 1996.[3] N. Mohan, T. M. Undeland, and W. P. Robbins,Power Elec-

tronics—Converters, Applications, and Design. New York: Wiley,1995.

[4] G. Boyes,Synchro and Resolver Conversion. Norwood, MA: AnalogDevices Inc., 1980.

[5] V. Blasko, J. C. Moreira, and T. A. Lipo, “A new field oriented controllerutilizing spatial position measurement of rotor end ring current,” inProc.PESC, 1989, pp. 295–299.

[6] F. Nozari, P. A. Mezs, A. L. Julian, C. Sun, and T. A. Lipo, “Sensorlesssynchronous motor drive for use on commercial transport airplanes,”IEEE Trans. Ind. Applicat., vol. 31, pp. 850–859, Aug. 1995.

[7] D. C. Hanselman, “Resolver signal requirements for high accuracy re-solver-to-digital conversion,”IEEE Trans. Ind. Electron., vol. 37, pp.556–561, Dec. 1990.

[8] TMS320C3x User's Guide, Texas Instruments, Dallas, TX, 1992.[9] G. Sitton,A Collection of Functions for the TMS320C30. Dallas, TX:

Texas Instruments, 1997.

Se-Kyo Chung (S’91–M’97) was born in Taegu,Korea, on November 26, 1966. He received the B.S.degree in electronics engineering from KyungpookNational University, Taegu, in 1989, and M.S. andPh.D. degrees in electrical engineering from theKorea Advanced Institute of Science and Technology(KAIST), Taejon, in 1992 and 1997, respectively.

Since 1997, he has been with the Departmentof Control and Instrumentation Engineering,Gyeongsang National University, Chinju,Kyungnam, Korea, where he is an Assistant

Professor. His research interests are in the areas on power electronics andcontrol which include high performance ac machine drives, switching powerconverters, DSP-based control applications, and nonlinear control applicationto power electronic systems.

Dr. Chung is a member of KIEE, IEEK, and KIPE.

Documents

2000-Jour-A Phase Tracking System for Three Phase Utility Interface Inverters