1EDI EiceDRIVER™ Compact 1EDI20N12AFfile.elecfans.com/...p7ABsB8tozau4363.pdf?filename=147850108483… · IN- inverted control signal for driver output if IN+ is se t to high. (Output

Industr ia l Power Control

Data Sheet Rev. 2.0, 2015-06-01

1EDI20N12AFSingle Channel MOSFET and GaN HEMT Gate Driver IC

1EDI20N12AF

1EDI EiceDRIVER™ Compact

Edition 2015-06-01Published byInfineon Technologies AG81726 Munich, Germany© 2015 Infineon Technologies AGAll Rights Reserved.

Legal DisclaimerThe information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party.

InformationFor further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com).

WarningsDue to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office.Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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1EDI EiceDRIVER™ Compact1EDI20N12AF

Data Sheet 3 Rev. 2.0, 2015-06-01

Trademarks of Infineon Technologies AGAURIX™, BlueMoon™, C166™, CanPAK™, CIPOS™, CIPURSE™, COMNEON™, EconoPACK™, CoolMOS™,CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™,EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™,MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PRIMARION™,PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™,SINDRION™, SIPMOS™, SMARTi™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™,TRENCHSTOP™, TriCore™, X-GOLD™, X-PMU™, XMM™, XPOSYS™.

Other TrademarksAdvance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSARdevelopment partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ ofHilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared DataAssociation Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ ofMathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor GraphicsCorporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc.,OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc.RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc.SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo YudenCo. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA.UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ ofDiodes Zetex Limited.Last Trademarks Update 2010-10-26

Revision HistoryPage or Item Subjects (major changes since previous revision)Rev. 2.0, 2015-06-01p17 dynamic parameter updateRev. 1.03, 2014-10-14all pages parameter completionRev. 1.02, 2014-02-14p 8 application diagram


Data Sheet 4 Rev. 2.0, 2015-06-01

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.2 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124.2 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124.3 Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134.3.1 Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134.3.2 Active Shut-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134.3.3 Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134.4 Non-Inverting and Inverting Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134.5 Driver Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145.2 Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155.3.1 Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155.3.2 Logic Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165.3.3 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165.3.4 Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175.3.5 Dynamic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175.3.6 Active Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6 Timing Diagramms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

7 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218.1 Reference Layout for Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218.2 Printed Circuit Board Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table of Contents


Data Sheet 5 Rev. 2.0, 2015-06-01

Figure 1 Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Figure 2 Block Diagram 1EDI20N12AF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Figure 3 PG-DSO-8-51 (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Figure 4 Application Example Bipolar Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 5 Application Example Unipolar Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 6 Propagation Delay, Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 7 Typical Switching Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 8 UVLO Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 9 PG-DSO-8-51 (Plastic (Green) Dual Small Outline Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Figure 10 Reference Layout for Thermal Data (Copper thickness 35 μm) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

List of Figures


Data Sheet 6 Rev. 2.0, 2015-06-01

Table 1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Table 2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Table 3 Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Table 4 Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Table 5 Logic Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Table 6 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Table 7 Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Table 8 Dynamic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Table 9 Active Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

List of Tables

ED- Compact

1EDI EiceDRIVER™ CompactSingle Channel MOSFET and GaN HEMT Gate Driver IC 1EDI20N12AF

Data Sheet 7 Rev. 2.0, 2015-06-01

1 Overview

Main Features• Single channel isolated Gate Driver• Input to output isolation voltage up to 1200 V• For high voltage power FETs• 4 A typical peak current at rail-to-rail outputs• Separate source and sink outputs

Product Highlights• Galvanically isolated Coreless Transformer Driver• Low input to output capacitive coupling• Suitable for operation at high ambient temperature• Wide input voltage operating range• ideally suited for driving cascoded or normally-off Gallium Nitride

HEMTs

Typical Application• AC and Brushless DC Motor Drives• High Voltage PFC, DC/DC-Converter and DC/AC-Inverter• Induction Heating Resonant Application• UPS-Systems• Welding• Solar MPPT boost converter

DescriptionThe 1EDI20N12AF is a galvanically isolated single channel FET driver in a PG-DSO-8-51 package that providesoutput currents of at least 2 A at separated output pins.The input logic pins operate on a wide input voltage range from 3 V to 15 V using CMOS threshold levels tosupport even 3.3 V microcontroller.Data transfer across the isolation barrier is realized by the Coreless Transformer Technology.The undervoltage lockout (UVLO) functions for both input and output chip and an active shutdown feature areincluded to always guarantee safe operation.

Product Name Gate Drive Current (min) Package1EDI20N12AF ±2.0 A MOSFET level optimized PG-DSO-8-51


Overview

Data Sheet 8 Rev. 2.0, 2015-06-01

Figure 1 Typical Application

OUT+

OUT+

Control

EiceDRIVERTM 1EDI20N12AF

EiceDRIVERTM 1EDI20N12AF

IN+

IN+

IN-

IN-

GND1

VCC1 VCC2,H

VCC2,L

GND2,L

GND2,HGND1

VCC1

OUT-

OUT-

DC

DC


Block Diagram

Data Sheet 9 Rev. 2.0, 2015-06-01

2 Block Diagram

Figure 2 Block Diagram 1EDI20N12AF

IN+

IN-

GND1

VCC1

2

3

4

1

6

7

5

8

VCC2

OUT-

OUT+

GND2

inputfilter

TX

UVLO

&active filter

inputfilter

GND1

VCC1

UVLO

RX&

Shootthrough

protection

VCC2


Pin Configuration and Functionality

Data Sheet 10 Rev. 2.0, 2015-06-01

3 Pin Configuration and Functionality

3.1 Pin Configuration

Figure 3 PG-DSO-8-51 (top view)

3.2 Pin Functionality

VCC1Logic input supply voltage with wide operating range (3.3 V o 15 V).

IN+ Non Inverting Driver InputIN+ non-inverted control signal for driver output if IN- is set to low. (Output sourcing active at IN+ = high and IN- = low)Due to internal filtering a minimum pulse width is defined to ensure robustness against noise at IN+. An internalpull-down-resistor favors off-state.

Table 1 Pin ConfigurationPin No. Name Function1 VCC1 Positive Logic Supply2 IN+ Non-Inverting Driver Input (active high)3 IN- Inverting Driver Input (active low)4 GND1 Logic Ground5 VCC2 Positive Power Supply Output Side6 OUT+ Driver Source Output7 OUT- Driver Sink Output8 GND2 Power Ground

1

2

3

4

8

7

6

5

VCC1

IN+

IN-

GND1

GND2

OUT-

OUT+

VCC2


Pin Configuration and Functionality

Data Sheet 11 Rev. 2.0, 2015-06-01

IN- Inverting Driver InputIN- inverted control signal for driver output if IN+ is set to high. (Output sourcing active at IN- = low and IN+ = high)Due to internal filtering a minimum pulse width is defined to ensure robustness against noise at IN-. An internalpull-up-resistor favors off-state.

GND1Ground connection of input circuit.

VCC2Positive power supply pin of output driving circuit. A proper blocking capacitor has to be placed close to this supplypin.

OUT+ Driver Source OutputDriver output pin sourcing current to turn on external switch transistor. During on-state the driving output isswitched to VCC2. Switching of this output is controlled by IN+ and IN-, resp.. This output will also be turned offat an UVLO event.During turn off the OUT+ terminal is able to sink approx. 100 mA.

OUT- Driver Sink Output)Driver output pin sinking current to turn off external switch transistor. During off-state the driving output is switchedto GND2. Switching of this output is controlled by IN+ and IN-, resp.. In case of UVLO an active shut down keepsthe output low.

GND2 Reference GroundReference ground of the output driving circuit.In case of a bipolar supply (positive and negative voltage with respect to switch source potential) this pin isconnected to the negative supply voltage.


Functional Description

Data Sheet 12 Rev. 2.0, 2015-06-01

4 Functional Description

4.1 IntroductionThe 1EDI EiceDRIVER™ Compact is a general purpose gate driver. Basic control and protection features supportfast and easy design of highly reliable systems.The galvanic isolation between input logic and driver output is achieved by utilizing on-chip Coreless TransformerTechnology. The wide input range supports the direct connection of various signal sources like DSPs andmicrocontrollers.The separated rail-to-rail driver outputs simplify gate resistor selection, save an external high current bypass diodeand improve dV/dt control.

Figure 4 Application Example Bipolar Supply

4.2 SupplyThe driver can operate over a wide supply voltage range, either unipolar or bipolar.With bipolar supply the driver is typically operated with a positive voltage of 12 V at VCC2 and a negative voltageof -8V at GND2 relative to the source potential as seen in Figure 4. Negative supply can help to prevent adynamic turn on.For unipolar supply configuration the driver is typically supplied with a positive voltage of 12 V at VCC2. In thiscase, careful evaluation for turn off gate resistor selection is recommended to avoid dynamic turn on (seeFigure 5).

Figure 5 Application Example Unipolar Supply

GND1

IN+

IN-

VCC1

OUT+

VCC2

GND2

OUT-

+5V

SGND

IN

+12V

10R1µ100n

3R3

-8V1µ0V

GND1

IN+

IN-

VCC1

OUT+

VCC2

GND2

OUT-

+5V

SGND

IN

+12V

10R1µ100n

3R3


Functional Description

Data Sheet 13 Rev. 2.0, 2015-06-01

4.3 Protection Features

4.3.1 Undervoltage Lockout (UVLO)To ensure correct switching the device is equipped with an undervoltage lockout for input and outputindependently. Operation starts only after both VCC levels have increased beyond the respective VUVLOH levels(see also Figure 8).If the power supply voltage VVCC1 of the input chip drops below VUVLOL1 a turn-off signal is sent to the output chipbefore power-down. The switch is turned off and the signals at IN+ and IN- are ignored until VVCC1 reaches thepower-up voltage VUVLOH1 again.If the power supply voltage VVCC2 of the output chip goes down below VUVLOL2 the switch is again turned off andsignals from the input chip are ignored until VVCC2 reaches the power-up voltage VUVLOH2 again.Note: VVCC2 is always referred to GND2; the output UVLO function thus depends on the total supply voltage.

4.3.2 Active Shut-DownThe Active Shut-Down feature ensures a safe off-state if the output chip is not connected to the power supply, Thegate is clamped at OUT- to GND2.

4.3.3 Short Circuit ClampingDuring short circuit the gate voltage tends to rise because of the feedback via the Miller capacitance. An additionalprotection circuit connected to OUT+ limits this voltage to a value slightly higher than the supply voltage. Amaximum current of 500 mA may be fed back to the supply through this path for 10 μs. If higher currents areexpected or tighter clamping is desired external Schottky diodes may be added.

4.4 Non-Inverting and Inverting InputsThere are two possible input modes to control the switch. In the non-inverting mode IN+ controls the driver outputwhile IN- is set to low. In the inverting mode IN- controls the driver output while IN+ is set to high, see Figure 7. Aminimum input pulse width is required to filter occasional glitches.

4.5 Driver OutputsThe output driver section uses MOSFETs to provide a rail-to-rail output. This feature permits that tight control ofgate voltage during on-state and short circuit can be maintained as long as the driver’s supply is stable. Due tothe low internal voltage drop, switching behaviour is predominantly governed by the gate resistor. Furthermore, itreduces the power to be dissipated in the driver.


Electrical Parameters

Data Sheet 14 Rev. 2.0, 2015-06-01

5 Electrical Parameters

5.1 Absolute Maximum Ratings

Note: Absolute maximum ratings are defined as absolute limits, i.e. exceeding them may lead to destruction of the integrated circuit.

Table 2 Absolute Maximum RatingsParameter Symbol Values Unit Note /

Test ConditionMin. Max.Power supply output side VVCC2 -0.3 40 V 1)

1) With respect to GND2.

Gate driver output VOUT VGND2-0.3 VVCC2+0.3 V –Positive power supply input side VVCC1 -0.3 18.0 V –Logic input voltages (IN+,IN-) VLogicIN -0.3 18.0 V –Input to output isolation voltage VISO -1200 1200 VJunction temperature TJ -40 150 °C –Storage temperature TS -55 150 °C –Power dissipation (Input side) PD, IN – 25 mW 2) @TA = 25°C

2) See Figure 10 for reference layouts for these thermal data. Thermal performance may change significantly with layout and heat dissipation of components in close proximity.

Power dissipation (Output side) PD, OUT – 400 mW 2) @TA = 25°CThermal resistance (Input side) RTHJA,IN – 145 K/W 2) @TA = 85°CThermal resistance (Output side) RTHJA,OUT – 165 K/W 2) @TA = 85°CESD capability VESD,HBM – 2 kV Human Body

Model3)

3) According to EIA/JESD22-A114-C (discharging a 100 pF capacitor through a 1.5 kΩ series resistor).



Data Sheet 15 Rev. 2.0, 2015-06-01

5.2 Operating Parameters

Note: Within the operating range the IC operates as described in the functional description. Unless otherwise noted all parameters refer to GND1.

5.3 Electrical Characteristics

Note: The electrical characteristics include the spread of values in supply voltages, load and junction temperatures given below. Typical values represent the median values at TA = 25°C. Unless otherwise noted all voltages are given with respect to their respective GND (GND1 for pins 1 to 3, GND2 for pins 5 to 7).

5.3.1 Voltage Supply

Table 3 Operating ParametersParameter Symbol Values Unit Note /

Test ConditionMin. Max.Power supply output side VVCC2 10 35 V 1)

1) With respect to GND2.

Power supply input side VVCC1 3.1 17 V –Logic input voltages (IN+,IN-) VLogicIN -0.3 17 V –Switching frequency fsw – 4.0 MHz 2) 3)

2) do not exceed max. power dissipation3) Parameter is not subject to production test - verified by design/characterization

Ambient temperature TA -40 125 °C –Thermal coefficient, junction-top Ψth,jt – 4.8 K/W 3) @TA = 85°CCommon mode transient immunity (CMTI)

|dVISO/dt| – 100 kV/μs 3) @ 1000 V

Table 4 Voltage SupplyParameter Symbol Values Unit Note /

Test ConditionMin. Typ. Max.UVLO threshold input chip

VUVLOH1 – 2.85 3.1 V –VUVLOL1 2.55 2.75 – V –

UVLO hysteresis input chip (VUVLOH1 - VUVLOL1)

VHYS1 90 100 – mV –

UVLO threshold output chip (MOSFET Supply)

VUVLOH2 – 9.1 10.0 V –VUVLOL2 8.0 8.5 – V –

UVLO hysteresis output chip (VUVLOH2 - VUVLOL2)

VHYS2 550 600 – mV –



Data Sheet 16 Rev. 2.0, 2015-06-01

5.3.2 Logic Input

Note: Unless stated otherwise VCC1 = 5.0V

5.3.3 Gate Driver

Quiescent current input chip

IQ1 – 0.65 1.0 mA VVCC1 = 5 VIN+ = High,IN- = Low=>OUT = High

Quiescent current output chip

IQ2 – 1.2 2.0 mA VVCC2 = 15 VIN+ = High,IN- = Low=>OUT = High

Table 5 Logic InputParameter Symbol Values Unit Note /

Test ConditionMin. Typ. Max.IN+,IN- low input voltage VIN+L,VIN-L – – 30 % of VCC1IN+,IN- high input voltage VIN+H,VIN-H 70 – – % of VCC1IN+,IN- low input voltage VIN+L,VIN-L – – 1.5 V –IN+,IN- high input voltage VIN+H,VIN-H 3.5 – – V –IN- input current IIN- – 70 200 μA VIN- = GND1IN+ input current IIN+ – 70 200 μA VIN+ = VCC1

Table 6 Gate DriverParameter Symbol Values Unit Note /

Test ConditionMin. Typ. Max.High level output peak current (source)1EDI20N12AF

IOUT+,PEAK

2.0 4.0

– A 1)

IN+ = High,IN- = Low,VVCC2 = 15 V

1) voltage across the device V(VCC2 - OUT+) or V(OUT- - GND2) < VVCC2.

Low level output peak current (sink)1EDI20N12AF

IOUT-,PEAK

2.0 3.5

– A 1)

IN+ = Low,IN- = Low,VVCC2 = 15 V

Table 4 Voltage Supply (cont’d)

Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.



Data Sheet 17 Rev. 2.0, 2015-06-01

5.3.4 Short Circuit Clamping

5.3.5 Dynamic CharacteristicsDynamic characteristics are measured with VVCC1 = 5 V and VVCC2 = 15 V.

Table 7 Short Circuit ClampingParameter Symbol Values Unit Note /

Test ConditionMin. Typ. Max.Clamping voltage (OUT+) (VOUT - VVCC2)

VCLPout – 0.9 1.3 V IN+ = High,IN- = Low,OUT = HighIOUT = 500 mA pulse test,tCLPmax = 10 μs)

Table 8 Dynamic CharacteristicsParameter Symbol Values Unit Note /

Test ConditionMin. Typ. Max.Input IN to output propa-gation delay ON

TPDON 90 115 137 ns CLOAD = 100 pFVIN+ = 50%,VOUT=50% @ 25°CInput IN to output propa-

gation delay OFFTPDOFF 100 120 143 ns

Input IN to output propa-gation delay distortion (TPDOFF - TPDON)

TPDISTO -15 5 25 ns

Input pulse suppression IN+, IN-

TMININ+,TMININ-

30 40 – ns –

IN input to output propagation delay ON variation due to temp

TPDONt – – 10 ns 1)CLOAD = 100 pFVIN+ = 50%,VOUT=50%

1) The parameter is not subject to production test - verified by design/characterization

IN input to output propagation delay OFF variation due to temp

TPDOFFt – – 10 ns 1)CLOAD = 100 pFVIN+ = 50%,VOUT=50%

IN input to output propagation delay distortion variation due to temp (TPDOFF-TPDON)

TPDISTOt – – 4 ns 1)CLOAD = 100 pFVIN+ = 50%,VOUT=50%

Rise time TRISE 5 10 20 ns CLOAD = 1 nFVL 20%, VH 80%

Fall time TFALL 4 9 19 ns CLOAD = 1 nFVL 20%, VH 80%



Data Sheet 18 Rev. 2.0, 2015-06-01

5.3.6 Active Shut Down

Table 9 Active Shut DownParameter Symbol Values Unit Note /

Test ConditionMin. Typ. Max.Active shut down voltage VACTSD

1)

1) Referred to GND2

– 2.2 2.5 V IOUT-/IOUT-,PEAK=0.1,VCC2 open


Timing Diagramms

Data Sheet 19 Rev. 2.0, 2015-06-01

6 Timing Diagramms

Figure 6 Propagation Delay, Rise and Fall Time

Figure 7 Typical Switching Behavior

Figure 8 UVLO Behavior

IN+

OUT

TPDON

50%

50%

TPDOFF

20%

80%

TRISE TFALL

OUT

IN+

IN‐

OUT

IN+

VCC2

VCC1

VUVLOH 2VUVLOL 2

VUVLOH 1VUVLOL 1


Package Outlines

Data Sheet 20 Rev. 2.0, 2015-06-01

7 Package Outlines

Figure 9 PG-DSO-8-51 (Plastic (Green) Dual Small Outline Package)


Application Notes

Data Sheet 21 Rev. 2.0, 2015-06-01

8 Application Notes

8.1 Reference Layout for Thermal DataThe PCB layout shown in Figure 10 represents the reference layout used for the thermal characterisation. Pin 4(GND1) and pin 8 (GND2) require each a ground plane of 100 mm² for achieving maximum power dissipation. The1EDI20N12AF is conceived to dissipate most of the heat generated through these pins.The thermal coefficient junction-top (Ψth,jt) can be used to calculate the junction temperature at a given top casetemperature and driver power dissipation:

Figure 10 Reference Layout for Thermal Data (Copper thickness 35 μm)

8.2 Printed Circuit Board GuidelinesThe following factors should be taken into account for an optimum PCB layout.• Sufficient spacing should be kept between high voltage isolated side and low voltage side circuits.• The same minimum distance between two adjacent high-side isolated parts of the PCB should be maintained

to increase the effective isolation and to reduce parasitic coupling.• In order to ensure low supply ripple and clean switching signals, bypass capacitor trace lengths should be kept

as short as possible.

Tj Ψth jt, PD Ttop+⋅=

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Documents

1EDI EiceDRIVER™ Compact 1EDI20N12AFfile.elecfans.com/...p7ABsB8tozau4363.pdf?filename=147850108483… · IN- inverted control signal for driver output if IN+ is se t to high. (Output