1D-814586 IMPLEMENTATION OF RN INTEL 8686 … · 1D-814586 IMPLEMENTATION OF RN INTEL 8686 MICROPROCESSOR-BASED 1/2 ... and the Intel 8080 library was desired and achieved by use

1D-814586 IMPLEMENTATION OF RN INTEL 8686 MICROPROCESSOR-BASED 1/2REALIZATION LIBRARY FOR THE CONTROL SYSTEM DESIGNLANGUAGE(U) NAYRL POSTGRADUATE SCHOOL MONTEREY CA

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cc NAVAL POSTGRADUATE SCHOOLMonterey, California

THESIS

IMPLEMENTATION OF AN INTEL 8086MICROPROCESSOR-BASED REALIZATION LIBRARY

FOR THE CONTROL SYSTEM DESIGN LANGUAGE

by

Alan Jeffrey Cetel

June 1984

Thesis Advisor: H. H. Loomis, Jr.j

Approved for public release; distribution unlimited

64; 12 06 (05

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SECURITY CLASSIICATIO* OF TWIS5 PAGE (Pfw. note Entered)_______________

REPORT DOCUMENTATION PAGE BEFRECMLEIN ORMIREPORT NUMBER 12I. GOVT ACCESSION NO. 3. RECIPIENT'S CATALOG MUMBER

4. TITLE (end ubtitle) 5. TYPE OF REPORT & PERIOD COVERED0

Implementation of an Intel 8086 Mse' hssMicroprocessor-based Realization Library Jue18for the Control System Design Language S. PERFORMING ORO. REPORT NUMBER .

7. AUTMORre) I. CONTRACT OR GRANT NUMBER4'a) --

Alan Jeffrey Cetel

9. PERFORMING ORGANIZATION NAME ANO ADDRESS 10. PROGRAM ELEMENT. PROJECT. TASK

Naval Postgraduate School AREA A WORK UNIT NUMBERS

Monterey, California 93943

If- CONTROLLING OFFICE NAIAE ANO ADDRESS 12. REPORT DATE

Naval Postgraduate School June 1984Monterey, California 93943 _1. NUMBER OF PAGES

___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ 17014. MONITORING AGENCY NAME A ADDRESS(I dlttoefro m Controlling Offlice) 1S. SECURITY CLASS. (of this report)

UNCLASSIFIED

ISDECLASSIFICATION/ DOWNGRADINGSCNEDU LE

IS. DISTRIBUTION STATEMENT (of tADO Renot)

Approved for public release; distribution unlimited___

17. DISTRIBUTION STATEMENT (of the abstract .mtteed in Steck 20, it different how Report)

1S. SUPPLEMENHTARY MOTES

III. Key WORDS (CotA..n -f'wee side It neessay an I*dify by bleck numbr)

Computer Aided Design; Microprocessor; 8086; Control SystemsDesign; Assembly Language Library

20. APOTRACT (Coeflaue -m revee side it asesem end Ideify' by Mae nueot)A library for use by the c _mputer aided design system, known as

the Control System Design Environment, made up of hardware andsoftware primitives of the Intel 8086 microprocessor family, waswritten to exctend the capabilities of the design system to morethan two microprocessor families. Compatibility between thislibrary and the Intel 8086 library was desired and achieved by

* use of designs originally realized with the 8080 library.

* DO ,'O W 43 EDInTo or I Nov as Is OSROLETRS/N 0102. LF-014-'6601 19CURITY CLASSIFICATION OF THIS PAGE Wohn Dee.SIrec 2r

d.

Approved for public release; distribution unlimited

,-.Implementation of an Intel 8086 Microprocessor-based

Realization Library for the Control Sy3tem Design Language

by

Alan Jeffrey CetelLieutenant Commander, United States NavyB.S., United States Naval Academy, 1975

Submitted in partial fulfillment of therequirements for the degree of

MASTER OF SCIENCE IN ELECTRICAL ENGINEERING

from the

NAVAL POSTGRADUATE SCHOOLJune 1984

Author:

Approved by: _-__

Thesis Advisor

Second Reader

airmad,-Departmdnt of•" :'

Electrical and Computer Engineering

l ean of Science and Engineering

2

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I...

ABSTRACT

A library for use by the computer aided design system,

known as the Control System Design Environment, made up of

hardware and software primitives of the Intel 8086

microprocessor family, was written to extend the

capabilities of the design system to more than two

microprocessor families. Compatibility between this library

and the Intel 8080 library was desired and achieved by use

of designs originally realized with the 8080 library.

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TABLE OF CONTENTS

I. INTRODUCTION------------------------------------------------

II. BACKGROUND -------------------- a--------------------------- 12

A. CONTROL SYSTEM DESIGN LANGUAGE------------------ 12

1. Design Environment--------------------------- 14

a. Example Problem Description ------------- 16

B. CURRENT IMPLEMENTATION--------------------------- 18

1. Primitive File------------------------------- 19

2. Timing File---------------------------------- 21

*III. REALIZATION LIBRARY---------------------------------- 23

A. LIBRARY FORMAT----------------------------------- 23

1. Primitive Title Line------------------------- 25

2. Comment Line--------------------------------- 29

3. Calculation Line----------------------------- 29

*4. Attribute Line------------------------------- 30

S. Call Line------------------------------------ 30

6. I clu e Li e - ---- --- ---- --- ---- --- - 3

6. Incud Line------------------------------------ 30

7. Beinx Line------------------------------- 32

8. enText Line------------------------------33

90. EnText Line---------------------------------- 33

IV. 8086 LIBRARY IMPLEMENTATION-------------------------- 36

A. MEMORY ORGANIZATION------------------------------ 36

1. Segment Registers---------------------------- 42

2. Input/Output Memory-------------------------- 46

4

3. Interrupt Handling ------------------------ 47

B. OPERATING SYSTEM CONSIDERATIONS --------------- 47

C. HARDWARE DESCRIPTION-------------------------- 48

1. 8086 Microprocessor and Support Chips ------ 48

2. Memory and Memory Support Chips ----------- 51

3. 8087 Numeric Data Processor --------------- 53

4. Other Hardware Support -------------------- 53

D. SOFTWARE DESCRIPTION -------------------------- 53

1. Monitor Section --------------------------- 56

2. Calculation Section ----------------------- 56

a. Arithmetic ---------------------------- 58

(1) Variations in SimpleArithmetic Routines --------------- 58

b. Floating Point ------------------------ 59

(1) Use of the 8087 NumericData Processor -------------------- 60

(2) Emulation of the 8087Numeric Data Processor ------------ 66

3. Logical Functions ------------------------- 68

4. Other Software Functions ------------------ 68

V. TESTING ------------------------------------------- 69

A. PRIMITIVE TESTING VEHICLE --------------------- 69

B. TESTING OF CONTROL LOGIC---------------------- 70

VI. RECOMMENDATIONS AND CONCLUSIONS ------------------- 71

A. RECOMMENDATIONS ------------------------------- 71

1. Universal High-Level Language RealizationLibrary ----------------------------------- 71

2. Hardware Wiring Diagrams ------------------ 72

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..-. .. .... * *****~*** %~**~********,**** .. o°

B. CONCLUSIONS------------------------------------- 72

APPENDIX A - DEFINITIONS OF PRIMITIVES-------------------- 75

APPENDIX B - LIST OF GLOBAL VARIABLES--------------------- 84

APPENDIX C - 8086 CPU REALIZATION LIBRARY ----------------- 87

LIST OF REFERENCES---------------------------------------- 169

INITIAL DISTRIBUTION LIST--------------------------------- 170

6

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LIST OF FIGURES

1. Flowchart of Design System ------------------------- 13

2. CSDL Design Example -------------------------------- 17

3. Example Primitive List ----------------------------- 20

4. Example Hardware Primitive Title Line -------------- 26

5. Example Software Primitive Title Line -------------- 27

6. Example Attribute Line Entry ----------------------- 31

7. Example If Line Entry ------------------------------ 34

8. Standard 8086 Memory Organization ------------------ 37

9. Memory Organization in the 8086 Library ------------ 39

10. Insertion of JUMP Instructions--------------------- 40

11. Overlapping of ROM and RAM Areas ------------------- 43

12. Definition of Base Addresses by Segment Registers-- 44

13. Constructing a 20-Bit Physical Address ------------- 45

14. 8086 in Maximum Mode --------------------------------- 50

15. Decoding Memory Banks ------------------------------ 54

16. 8087 Numeric Data Processor on Local Bus ----------- 55

17. Example Monitor Section ---------------------------- 57

18. Floating Point Variable Format --------------------- 61

19. Speed Comparison Between 8087 NDP and 8086 ---------- 63

20. Projective versus Affine Closure ------------------- 65

21. Use of ESC Codes in a Co-processing Environment-- 67,

22. Universal High Level Language Software LibraryImplementation ------------------------------------- 73

7

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S S. . . . .. . * . . . . .

ACKNOWLEDGMENTS

I would like to thank my advisor, Professor Herschel

Loomis, Jr., and second reader, Lieutenant Colonel Alan

Ross, for their guidance during this project.

ion.

8

I. INTRODUCTION

Computer Aided Design has seen an upsurge of use in

the past decade, providing assistance in the design and

eventual realization of everything from Very Large Scale

Integration circuits to complete systems. The use of

computers to simplify man's tasks is the chief motivating

factor to develop more powerful computing devices. Recent

trends in the development of Computer Aided Design (CAD)

tools are toward a more 'user friendly' environment. Some

CAD systems are so sophisticated that the user need not know

the underlying principles of design in order to take a given

concept, from its inception through actual realization in

terms of either hardware and/or software. Starting with the

simplest of descriptions, today's system or component

designers may very well spend all his/her time designing at

a computer keyboard or digitizing table.

What motivates the trend toward more efficient design

systems are threefold: 1) greater speed in producing a

viable design, 2) better use of scarce design system

resources, and 3) decreased cost to produce the desired

item. With the introduction of the microprocessor, it

became apparent that its uses were limitless. Any

conceivable electronic application spurred its use. From

general purpose computing to specialized repetitive

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functions the microprocessor found its way into industrial,

commercial and military applications. As more uses were

found, the ability to design with these devices lagged

behind the rising requests for these new designs. Since the

designs are labor intensive and design engineering expertise Op,.

is at a premium, the concept of computer aided design was

born. This technique helps to pare down the time it takes

to design a new system or component. Engineers were, of

course, not the only item in short supply. Computers needed

to aid in these designs were also a scarce commodity. This

led to the improvement of the design tools to see a design

to completion with the least amount of resources used (e.g.

time, computer use etc) [Ref. 1]. Once these major

impediments had been overcome, the ability for the computer

to help optimize the design was at hand. Factors to be

considered were to decrease the number of chips or silicon

acreage, decrease the power requirements, and decrease the

overall cost of the system.

The use of microprocessors for real time control is

just one of the applications that is seen in today's

electronic environment. As in the past, design of these

systems are a time consuming and complex process. In order

for digital computing systems to provide a design ft

environment, an examination of just how a design engineer

might approach the problem is justified. The designer must

10

-*l - -

rely on a certain amount of background knowledge of the

problem that is presented prior to his attempting its

design. The implementation of this knowledge may be by the

use of a database of design rules. These rules would apply

to both the hardware and software factors required to

realize a given problem. An extension of this idea would be

the creation of a sequential listing of all possible

combinations of circuit devices or software tasks that may

be necessary to construct a device and the tasking of the

digital computer to maintain a running list of attributes to

insure that all design criteria are being met in the

generation of a design realization.

This thesis will provide a library of hardware and

software primitives implemented using the Intel Corporation

iAPX 86/10 (8086) 16-bit microprocessor and its family of

support chips. Chapter II will discuss the origins of the

design environment in which this library will be used and

its current implementation. A description of the structure

of the realization library is presented in Chapter III.

Chapter IV introduces the 8086 microprocessor and

discusses its memory organization, the basic hardware design

of a system implemented in this library, and a complete

discussion of the software configuration including the use

of assemblers, control, and arithmetic processes. Chapter

V outlines the testing of this library. Finally, Chapter VI

offers some recommendations for system improvement,

observations and conclusions.

11I

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II. BACKGROUND

The system model proposed by Matelan [Ref. 2] for the

design of microprocessor based controllers contains a

concept of computer aided design whereby the specifications

are not initially linked to the type of technology that

might be used to implement a system. This binding of the

design to a particular hardware and software technology is

performed only after several intermediate processes are

executed. These intermediate functions build symbol and

timing tables, and prepare a table of the individual

primitive names required to realize the design. It is only

after this, that an implementation technology is chosen.

The technology is contained in a volume of hardware and

software primitives called the realization library.

A. CONTROL SYSTEM DESIGN LANGUAGE

Matelan's proposal suggests the use of a new high level

language which he developed, called the Control System

Design Language (CSDL), to support the definition of a

design. An environment to interpret the design language and

provide the necessary design system supervision and analysis

is shown in Figure 1 [Ref. 3].

12

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1. Design Environment

A CSDL description is written by the designer and

is used as input to the design system. The translator

decomposes the data from the description into two files: a

list of primitives and a timing file. Examples and an

explanation of these two files are presented later in this

chapter.

The Optimizer module is first to receive these files.

This module is tasked to control the overall execution of

the system, serve as the input routine, and make a

comparison of multiple realizations created by the system

and choose the one that meets the criteria as specified by

the designer. Following the optimizer is the Functional 4 "

Mapper. It is the task of this module to ensure that the

primitives required by the design are realized in the current

realization library. Once the Functional Mapper

successfully creates a listing of software titles, it

becomes the task of the Timing Analyzer to ensure that all -.-

necessary timing constraints are satisfied. With a

satisfactory timing analysis complete, the design is

considered successful and the final function performed is

the actual creation of the software and hardware listings.

This process is accomplished by the Formatter. This module

extracts from the current realization library all text that

14 ;"

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is contained in each primitive in the primitive list and

writes this text to the respective software and hardware

output files.

CSDL defines functions and their timing constraints

using the concept of contingency/task pairs. A contingency

is defined as a function of an input variable or variables.

The task associated with this contingency is executed only

after the contingency is satisfied. Any given design then, S

must be stated in terms of its contingency/task pairs.

Matelan's Control System Design Language is used as

the designer's interface to the overall design process. This

language supports the input of a design by problem specifi-

cation as follows: 1) an identification section, 2) an

environment section, 3) a listing of contingency/task

pairs, and 4) a procedures section.

The identification section is used as a header and

record of when and by whom the design was created. The

environment section describes the variables associated with

the input and output ports of the device, their electrical

characteristics, as well as the variables included in all

computations internal to the software implementation. It is

analogous to the variable declaration section of high level

languages such as FORTRAN or PL/I. The contingency list

describes the conditions that must be satisfied prior to the

execution of its associated task. This list must also

define the timing constraints that must be satisfied when

15

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executing the contingency/task pair. Timing analysis is

performed to insure that the time needed to execute a

contingency and task falls within the required maximum time

allowed by the designer prior to the execution of the next

contingency/task pair. Finally, the procedures section

contains the routines that make up each contingency/task.

a. Example Problem Description

An example CSDL listing is shown in Figure 2.

The identification section is self-explanatory, containing

the designers name, the date of file creation and the

project name. The environment section contains all the

input and output variable names and their bit length

(precision). In this example the input variable X and

output variable Y are both 16-bit values while the variable

DL is a single bit. All of these variables are also

identified as being TTL compatible. This section also

contains the variable M and it's 16-bits that is used

internally to the design. These variable descriptions are

contained in the Arithmetic portion of the environment

section. The function EXAMPLE that is contained in the

contingency list is executed every 10 milliseconds, and when

found to be true, the task RELIZE is performed. The final

section of this high level description of the problem is the

procedures section. It is in this section that the

contingency/task pairs are explicitly defined. The

contingency EXAMPLE is performed by sensing an external

16

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IDENTI FICAT ION

DESIGNER: "A. J. CETEL"1DATE: "114 MARCH 1984" SPROJECT: "DESIGN EXAMPLE"

ENVIRONMENT

INPUTf: X,16,TTL;DL,1,TTL;INAME,l,TTL;OUTPUTf: Y,16,TTL; IARITHMETIC: M,16;

PROCEDURES

FUNCTION EXAMPLE:EXAMPLE := 0:SENSE (INANE);IF INAME 1 THEN EXAMPLE:= 1; END IF;

END EXAMPLE;

TASK RELIZE;SENSE (X);Y CX * 10 M ;ISSUE CY);

END RELIZE;

CONTINGENCY LIST I~WHEN EXAMPLE 1 ONS DO RELIZE;

END

Figure 2. CSDL Design Example

17

variable INAME. If the value of this variable is equal to

one, then the value of EXAMPLE is also set to one. With the

value of EXAMPLE equal to one, the contingency is satisfied

and the task RELIZE is performed. The task RELIZE is a

simple arithmetic expression that senses the value of X,

then computes the value of Y using variables, as described

in the arithmetic portion of the environment section, as

well as any constants required, and latches or otherwise

makes the value of the variable Y available at a TTL

compatible output port. Had the variable INAE been another

value, then EXAMPLE would not be set to one, the contingency

therefore would not be satisfied and the task RELIZE would

not be performed.

B. CURRENT IMPLEMENTATION

Implementation of Matelan's design system was produced

as part of a dissertation by Ross [Ref. 4]. This

implementation however, does not support the input

translator to the system. A CSDL compiler (translator),

designed to be the input module, implemented in Pascal, is

under development by Carson [Ref. 5].

The description of the input specification in the

previous section is presented for continuity purposes only.

In order to relize a design as the system is currently

implemented, a number of intermediate files are required.

18

1-.:.N

1. Primitive File,

A list of primitives, implemented as the file

PRIMITIVE.DAT, contains a representation of all the required

primitives to realize a given system. It contains each

primitive to be extracted from a realization volume and the

information required to generate the hardware and software

listings. Variable names, data constants, and data size

descriptions are all contained in the primitive listing.

The order of primitives is directly related to the order

required to implement the device. An example of this file

is given in Figure 3. Each line in the primitive file is a

sequential list of the lines to be taken from a realization

library required to fulfill given design requirements.

A system primitive list is always required to initialize

pointers, include software heading or assembly language

directives, and call the processor primitives required to

eventually realize the design. This item is shown in the

first group of primitives labeled - t.generated for: system.

All of the above requirements are accomplished within the

primitive s.main(::). All arguements passed to the primitive

are included between the parenthesis and before the first

colon. The precisions of any variables passed are contained

between the two colons. No information is needed after the

second colon, however the second colon is required due to

the strict format of Ross' implementation.

19

..........................................................

T.GENERATED FOR: SYSTEMs.main (:T.GENERATED FOR: EXAMPLEs.proc (EXAMPLE::)

s.jmpf C@Tl,@1000:8:)s.assigncons (INAME,0:l,1:)s.assigncons (EXAMPLE,1:1,1:)s.loc (@1000:8:)s.exitproc (EXAMPLE,0::)s.cons (@C001,O:1,1:)s.var (EXAMPLE:1:)s.var (INAME:1:)s.var (@Tl:8:)T.GENERATED FOR: RELIZEs.proc (RELIZE::)s.assigncons (INAME,0:1,1:)s.anain (X,-10,10,5:16:)s.mul (Ml,X,C1:16,16,16:)s.add (Y,Ml,M:16,16,16:)s.anaout (Y,-10,10:16:)s.cons CC1,10:160)

Figure 3. Example Primitive List

20

-. . , - - - -. '.. - . - .

The first contingency, EXAMPLE, requires a procedure

beginning and end, shown by the software primitive s.proc

and s.exitproc. The argument passed for this primitive is

simply the contingency name. A primitive titled s.eq checks

for equivalence between the one-bit variables labeled iname

and @cOO1 and if true assigns the 8-bit variable @tl the

value of true (=l). The remaining primitives provide

constant assignments, establishment of variables, arithmetic

routines, and input and output software routines. Hardware

primitives are usually called from their software

counterparts.

It is from this file that the functional mapper selects

a primitive from the realization library that matches not

only the title, but also the number of arguments required

and the precisions of these arguments.

2. Timing File

A timing file to be used in the analysis of each

contingency/task pair must also be generated. This file, .

IADEFL.DAT, contains the timing constraints imposed by each

contingency/task pair. This file is used by the timing

analyzer, along with the previously built list of software

titles, to determine if the time constraints imposed by the

designer are met. Included in this file is the design

criteria section, added by Ross to provide a metric by which

to determine the optimal realization of a design. The

designer may choose one of three criteria to produce a

21

design realization: 1) first realization that is generated

2) most inexpensive and 3) the realization with the least

power consumption. A detailed description of this file is

not included here since is not directly concerned with the

construction of a realization library. It is mentioned to

provide the reader with a better overview of the design ...

environment in which the realization library exists.

22

22-2

-- . - 9. . . 9*9 * * 9 . . . . . .

III. REALIZATION LIBRARY .

Ross' original implementation provided a library of

hardware and software primitives using the Intel 8080

microprocessor. This library established the format

required to implement subsequent microprocessor libraries.

To date, the addition of a Zilog Z-80 library by Smith

[Ref. 6], and this thesis, using the Intel 8086, are the

only other libraries written. Chapter VI of this paper

outlines a method to eliminate the need to write individual

assembly code libraries for every microprocessor family.

A. LIBRARY FORMAT

The rigid structure of the realization library format

requires the writer to build a library using one of ten

possible formats for each line of the library. These

formats are:

1) primitive title line2) comment line3) calculation line4) attribute line5) call line6) include line7) if line8) begin text line9) endtext line

10) text line

23 .'

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Each line of a library begins with a 'v' in column one

followed by a four digit line number in columns two through

five, and text in columns six through eighty. A line may

not extend past column eighty in the current implementation.

The first digit of the four digit line number specifies the

volume number. If more than 999 lines are needed in a

library or more than nine volumes are written, alphabetic

characters can be used.

The first line of the library, line number vxOOO (where

the x is the volume number), identifies the microprocessor

family (intel 8086 cpu), the clock period, any additional

delays in accessing memory, and a monitor constant all used . -

in the timing analysisto determine if a particular design

is realizable. Each of these attributes are separated by

colons (see the first line of the realization library,

Appendix C). Following this line is the library index,

which is a copy of every primitive title line contained in

the library. Line numbers in the index are not consecutive,

but are the actual line numbers of the primitive title

lines' location in the body of the library. However, a

counter tracks each line listed in the index so the first

primitive title line in the body of the library contains its

actual line location from the beginning of the library,

including the index listing. The index of primitives is

followed by an '.end index' line starting in column seven.

24

L7

*. . . . . . . . . .. . . . . . . . . . . .*

1. Primitive Title Line

Title lines define either hardware or software

primitive types. A decomposition of a hardware and software

title line are shown in Figures 4 and 5, respectively. The

hardware title line starts with an 'h' in column 6, a period

in column 7, and the primitive title in column 8 through 17.

If the title is less than 10 characters in length, then

blanks are inserted through column 17. Column 18 contains a

left parenthesis followed by the parameters of the

primitive. These parameters are listed in three variable

length fields separated by colons. If any of these fields

are empty, the colons must still appear. The first field

specified the dummy argument names, followed by a colon,

with the selection criteria in the second field. Argument

names can be up to six characters in length and are

separated by commas. The arguments must appear in the same

order as the actual arguments in the primitive calls.

The selection criteria, in the second field, contains

the minimum and maximum size, in terms of bit count or

precision, of each argument. Each of these values are

separated by commas. These values are used by the

functional mapper to determine if the primitive realization

meets the requirements of the primitive being invoked. This

field is also followed by a colon.

The third field contains the attributes of the

realization. For a hardware primitive, these attributes are

25

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(in order, separated by commas): 1) latency of the device

(delay in accessing), 2) amount of power required by the

electronic components contained in the primitive (in

milliwatts), and 3) the number of chips contained in the

primitive. For a software primitive, these three attributes

are (again in order, separated by commas): 1) number of

8-bit bytes of storage required, 2) the number of clock

cycles required to execute the primitive, and 3) the number

of references to external memory made during the primitive.

Both hardware and software primitives use the next four

attributes as a flag to indicate whether any calculation

('calc') or include ('incl') lines are contained in the

primitive, and the line numbers of the first and last line

of the primitive within the body of the library. If no

'calc' or 'incl' lines are contained in the primitive, a

value of zero is given to these attributes. A primitive

that contains a 'calc' or 'incl' line has a value inserted

into this location that corresponds to the offset from the

first line of the primitive to the line where a 'calc' or

'incl' does occur. If any of these attribute values depend

on formal parameters passed by the calling primitive line,

the attribute is given a negative sign in the title line.

The offset to an attribute ('attr') line which calculates

the actual value of the corresponding attribute in the

absolute value of this negative attribute in the title line.

28

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2. Comment Line

Each comment line begins in column 6 with 'com'.

Columns 9 through 80 can be any desired text, numerals, or

special characters. This line is ignored by the system and

is therefore not written to any output file.

3. Calculation Line

Calculation or 'calc' lines are used in library

primitives to manipulate system global variables. This line

begins with 'calc' in columns 6 through 9. The list of

available system globals and the definition of each is

contained in Appendix B. This global list is a combination

of Ross' original implementation and Pollock's [Ref. 7]

additions for the Intel 8080 cpu, and the additions provided

by this paper. This universal globals list is generated to

provide the design environment with the ability to select

between microprocessor families in order to selected the

appropriate realization to meet timing and design criteria

- .without the need for a separate globals list for each

library. The 'calc' lines assign values to the global

variables during the generation of the design. Calculations

are performed using mathematic expressions with global names

and dummy parameters as variables. Arithmetic operators

available are +, -, , -, and ** and any number of pairs of

left and right parenthesis to force the order of execution

of operators. The operators are interpreted in the same way

as they would be in Fortran.

291-.,"-"2

4. Attribute Line

Similar to the 'calc' line, attribute lines begin

with 'attr' in columns 6 through 9 and are used to calculate

the value of the attributes contained in the first three

parameters of the third field of the primitive title line.

For example, depending on the value of a certain global

variable, a primitive may or may not add a new hardware

component to the hardware realization. This means that a

check would be required within the primitive to determine

whether to include a component or not. The title line would

show a chip count of zero, but following a check of a global

for a certain value signifying the need for the addition of

the component, the chip count would be increased by one

using the 'attr' line (see Figure 6).

5. Call Line

This line is used to provide control within the

library to invoke other primitives. As with other line

items, this line begins with 'call' in columns 6 through 9.

Prudent use of the 'call' line results in the reduction in

the overall size of the library. A 'called' primitive's

text is added to the output listing at the place where it is

called.

6. Include Line

An include line is similar to the 'call' line with

the difference being the included primitive text is placed

at the end of the output listing after all of the other

30 - ' ."

. . . . . . . . . . . . . . .. . . . ..,

Primitive with Flag

(Attributes computed within the primitive)

power number of chips

latency -

h. invert (in,out ,0,0,0,0,1i000,1i010) ..

corn primitive to define ttl invertorif flgnme .ne. 1 skip 2attr pwr = pwr + 60 Flag used to determineattr chips = chips + 1 if component is to be

added.(Body of primitive)

Equivalent Primitive with Attributes in Title Line

power number of chipslatency \/

h.invert (in,out: :0,60,1,0,0,1000,1007)com primitive to define ttl invertor

(Body of primitive)

Figure 6. Example Attribute Line Entry

31.

I-.

•~~~7 72, . .. . . .

primitives in the Formatter input primitive list are

finished. This line begins with 'incl' in columns 6 through

9. The 'incl' line is used mainly to add hardware to the

hardware output listing during the generation of the

software output. For example, the addition of a hardware

I/O port during the addition of the software text that

supports the checking of information at that port address.

Both the 'incl' and 'call' lines must contain the

actual arguments and selection criteria fields, if needed.

Spacing requirements are the same as for the primitive title

line and must be observed. Arguments must start in column

19 preceded by a left parenthesis in column 18 and must be

-' separated by commas and followed by a colon. Another colon

must follow the selection criteria field, if present, and

the line must end with a right parenthesis.

7. If Line

Conditional branching is accomplished within the

library by use of the 'if' line. This line begins with 'if'

in columns 6 and 7 followed by a mathematic expression, a

relational operator, .ne., .gt., .ge., .1t., or .le.

(meanings as in Fortran), another mathematic expression, and

a skip instruction to by-pass any number of lines forward or

backward from the 'if' line within a primitive.. The format

for this statement is:

if <math exp> <rel op> <math op> skip <# of lines>

32......................... ~ . ..... .... .*.*.. .- . • .

If a backward skip is required a negative value is used for

the "# of lines" argument. A skip backwards includes the

'if' line executing the branch and the line to be executed

upon completion of the skip. This process is shown in

Figure 7. An unconditional branch can be invoked by using

the skip portion of an 'if' line.

8. Begin Text Line

This line precedes the actual lines of text that

appear in the output listing andin combination with the

'endtext' line brackets the text of the primitive. The line

begins with 'begin htext' for a hardware primitive, and

'begin stext' for a software primitive, in columns 6 through

16. No other characters appear on a begin text line.

9. Endtext Line

This line begins with 'endtext' in columns 6

through 12, for both hardware and software primitives, and

in combination with 'begin text' marks the end of a text

listing that is destined for an output file. Any number of

'begin text' and 'endtext' lines may appear in a primitive,

but they must be used in pairs.

10. Text Line

A text line is free-form and allows the library

writer to format lines of text between 'begin text' and

'endtext' in any way that will later be compatible as

hardware and software output listings. These lines contain

33

.*. * * *.~. . **.* ~ . . *** ** .* .*** 'o~ ~ o° -

aa

' 4

0

44.4

~ 04

4J 04

a': 04

4' - - -I1.0,4 .1 I l

34

x%

.7.7 77- 7. w--v----- V

volume and line numbers, therefore the only restriction is

to limit the text to columns 6 through 80. All text

contained in text lines will be copied to the output listing

exactly as written with two exceptions. Variables enclosed

in pound signs (#) are interpreted as a call to a system

procedure or function. The corresponding procedure will be

implemented to generate character strings for the output

listing. An example of this is the use of the #IDSEC#

function in the primitive s.heading of Appendix C. This

copies the lines of the identification table from the input

file to the output listing. The other exception is the use

of dummy arguments enclosed in brackets '<' and '>'. Each

time a dummy argument is encountered in a text line enclosed

in brackets, the current value of that argument is written

to the output listing in the location specified in the text

line.

35

p' 35

* :.

IV. 8086 LIBRARY IMPLEMENTATION

The use of the Intel 8086 16-bit microprocessor is a

logical extension of the currently available realization

libraries to CSDL. Due to the similarities of the 8080 and

Z-80 microprocessor architecture and instruction sets, a

good comparison of execution speeds of a given design is

* easily done. In some cases, for example, a control system

realization may not be possible with the slower 8080 cpu,

but may easily be implemented by the Z-80 or 8086. The

variables of cost and power consumption must also be taken

into account to make a final decision as to the ?best'

*realization to be used (recall that these factors are part

* of the design criteria section' of CSDL).

A. MEMORY ORGANIZATION

Figure 8 shows the standard memory map of the 8086.

* Memory organization used in the 8086 realization library is

opposite from the previous two libraries. Whereas the 8080

* and Z-80 libraries build the ROM (instruction) area from low

to high memory locations and RAM (data and stack) area from

high to low memory locations, the 8086 builds RAM from low

to high with ROM stepping from high to low in 6'4K byte

steps. Stack RAM is isolated from data RAM by use of the

segment registers, discussed later in this chapter.

36

loiclexesino....u..tl..albl eaiato

FFFFFH

Rest Bottra FFFFOH -Starting Address on Reset

Reserved Locations forInterrupt Pointers(Addresses O0000H-OO3FFH)

64K ByteI/O Space

00O3FFH

~)OOH

L

Figure 8. Standard 8086 Memory Organization

37

Realization library memory organization is illustrated

in Figure 9. Stack memory occupies the lowest 1K of RAM•

followed by the data RAM which is allowed to increase in

size up to the lower limit of the ROM area. This

configuration chooses to take advantage of the instruction

pointer (IP) being set to address FFFFOH upon microprocessor

reset and the default value of the code segment register

set to the highest 64K byte block of memory. Instructions

are written into ROM by stepping to the lowest address of a

64K byte block and then incrementing addresses for each

I. succeeding instruction. At the highest address location in

any 64K byte block, a JUMP instruction is inserted to jump

to the lowest address of the next lower 64K byte block of

memory (see Figure 10). By keeping instructions in high

memory, there is no overhead associated with manipulating

segment register values that would be required to embed

instructions in the middle of what would otherwise be data

or stack memory addresses. Therefore, instruction ROM area

remains in the higher memory locations. However, this

method only allows for a code section 65516 bytes in length

in this library's implementation. This is due to the

inability of the design system to check for the current ROM

pointer value during software file generation and evaluate

the 'stuffing' of a jump instruction in the last three bytes

of the current 64K byte memory block. A method to evaluate

38

I-............... .. ~..-...... ........ ....

. . . . . . . . . . . . . . . . . . .. . . . . . . . . .*. .°

VSee Figure 10. for explanation of JUMPS

______________FFFFFH

4 Starting Address at CPU RESET(FFFFOH)

4 Code Segment (ROW) growsdownward

64K Blocks

I Data Segment (RAM) growsupward

I-.. 1KStak Sace1K /O pac

Figure 9. Memory Organization in the 8086 Library

39

~bid"

FFFFFH

- . JUMP FFFFOF StartingJUMP Address

Instructions !Vincrease inaddress. Atthe top of each

-jump 64K block, a

JUMP is insertedto force code

to sart in theI lowestaddressof the preceding

64K Blocks JUMP 64K block.

-JUMP

Figre10.Inertonof U1P Istucton

0

40Z 2

- - .*"- --. -.7

a primitive's assembly code line by line is necessary to

execute this procedure, since a primitive may exceed a 64K

byte memory boundary partially through that primitive's

code. An alternative to this method would be to allow the

system to delay the binding of ROM addresses until the

entire instruction code has been generated. The appropriate - *:number of 64K blocks of memory could then be generated for

the hardware output listing. Once this is done, the address

of the lowest block of memory may be inserted into the JUMP

instruction located at FFFFOH using the system equates (e.g.

sysl4) found at the beginning of the assembly heading. This

would then allow an uninterrupted, linear address space for

use by the IP without the associated overhead of adding jump

instructions at the high address of each 64K byte memory

block. A third alternative would be to arbitrarily

partition memory into two 512K byte segments, one for code

and one for data/stack.

With program code in high memory, the stack and data

RAM sections are put into the lower addresses. A stack area

of 1K is established in the first 1K of memory. Immediately .

following the stack area is the data area. This area is

allowed to grow to any size, up to the ROM area. For very

large programs where data RAM and instruction ROM addresses

approach each other, a scheme must be incorporated to ensure

that neither of these areas will occupy a portion of the

141

same 16K byte block of memory. Figure 11 shows how this

conflict is resolved. Current implementation does not .

consider this possible error condition.

1. Segment Registers

Addressing the one megabyte of memory available to

an 8086-based system does not follow the standard

microprocessor addressing convention. A 20-bit address bus

is required to support the entire address space. Register

structure within the 8086 is only 16-bits wide. To

accomplish the construction of a 20-bit address, a second

summer is used in conjunction with one of four segment

registers. These segment registers define a base address

within a 64K byte block of memory which allow code, data,

and stack values to be separated in physical memory. The

capability exists to fully or partially overlap segments

within the physical memory space by storing the appropriate

values in the respective segment registers. As is shown in

Figure 9, the stack and data 64K byte segments overlap with

the exception of the lowest 1K of memory. An "extra"

segment can also be defined for whatever purpose the

programmer deems necessary. This extra segment is not used

in the construction of this library. Figure 12 illustrates

how segment registers define base addresses. Figure 13

shows how these registers are used for computing address.

A 16-bit address in the IP, called the logical address, is

42

**" * . .. .""2

",.Wse porti . .. -

ROM (High to LowAddresses)

Wase portion of.-. o

16K Block Last Line ofBoundries - Program

Last 16K, Block ofROM

Highest AddressAvailable to RAM

RAM (Low to HighAddresses)

S

Figure 11. Overlapping of ROM and RAM Areas4

'.---.>-T

43 *- -_.-

FFFFFH

-Code Segment

-Stack Segment

Data Segment

Segment Registers

Code

-Extra Segment

________________I OOOOOH

Figure 12. Definition of Base Addresses by Segment Registers

44

*,'.** .0

15 0

Base Address/(Segment Register) -i/

/ Shift

194 4/

16 x 0 0

(Isruto Pontr I

Locical Address

FIsrcinr Pointer)nga20Bi hyialAdrs

I I 45

7 ii- ~- °-."...

added to the value contained in one of the segment

registers, the base address. Prior to the addition, the

base address is multiplied by sixteen, which effectively .-.--

performs four left shifts and 'stuffs' zeros in the least

significant nibble. The result of this addition produces a

20-bit real address that is subsequently placed on the

address bus. On microprocessor reset, default values for

the segment registers are loaded, but may be changed at any

time by the program or upon assembly if the code, data, or

stack regions extend beyond their respective 64K byte

boundaries.

Changing the values of these registers within the

primitives of this library is not done, with the exception

of stack and data segment initialization. As program size

increases, there exists a requirement to change the values

in the segment registers as code or data cross 64K byte

boundaries. The process of determining when to load a new

base address into a segment register is transparent to the

programmer, since this task is accomplished by the

assembler.

2. Input/Output Memory

Input/Output memory is implemented in the 8086 as a

separate 64K byte block of memory located in the lowest

address space. In this implementation, I/0 memory is

restricted to the lowest 1K byte of memory. Although

46

%! %....:

.. .T.. 7

arbitrarily chosen, this amount of I/0 should accommodate

even the most I/0 oriented design. Any requirement to

increase I/0 memory can easily be accomplished by

substituting a new base address for data RAM, thus allowing

the stack to grow into the current data address space.

3. Interrupt Handling Considerations

Current implementation of CSDL does not support an

interrupt driven, real-time controller. Therefore, the 3

interrupt (INTR) and non-maskable interrupt (NMI) pins are

tied to ground. Memory space that is normally reserved for

interrupt handling in low memory of the 8086 is ignored and

has been designated as the lower quarter of stack memory.

If further research allows for interrupts in controller

system generation, all that is required to alter the current

memory map convention is to shift both the stack base

address and the data base address values to an address area

above the highest interrupt address. Without changing the

data segment, a configuration allowing all 256 interrupts

and a stack size of 768 bytes could be implemented by only

shifting the stack base address to 256D. @

B. OPERATING SYSTEM CONSIDERATIONS

The system monitor constructed from library primitives

forms the operating system of the design realization (more

on the monitor later). No outside intervention in the

operation of controllers produced by this CAD system is

147

" ° °. P.

I°

anticipated. Therefore, all memory is available for use

by the code, data, and stack only.

C. HARDWARE DESCRIPTION

A large memory space combined with a high speed

microprocessor makes even the simplest of hardware

configurations generated from this library chip intensive.

The composition of the library is based on individual IC's

and their eventual integration onto a printed circuit or

wire-wrap board. This follows the convention of the

original 8080 library. It becomes possible then, to make a

direct comparison between the two libraries when attempting

to make a design criteria check. This differs from the -7

prototyping scheme used by Smith in the generation of the

Z-80 library.

1. 8086 Microprocessor and Support Chips

To allow for faster performance at the hardware

level, the Intel 8086-2 8MHz microprocessor is used.

Although a faster version, the 8086-1, is available which

runs at 10MHz, the choice to remain at 8MHz is based on two

requirements. First, and foremost, is memory compatibility.

The option to obtain memory devices from other manufacturers

was available, but for power requirements and overall system

integrity, the use of Intel produced memory chips was made

(discussion of memory follows later in this chapter).

Secondly, the choice to proceed with the 8MHz version is

4~8 • -C8"'"

* * ***~a**% .- *.* *** * ~ ~ ***~ /* -. * . . . .*- :. -'

cost. In the long term, however, with the cost of most

popular integrated circuitry decreasing, this point may be

of little consequence.

Two modes of operation are available with the 8086 cpu.

These are the minimum and maximum modes. The minimum mode

is used for single processor, minimum chip count applica-

tions. The maximum mode allows multiprocessing and

I attLached co-processor systems. All that is required to

configure the processor into one or the other of these modes

is to tie the MN/MX pin to + 5 volts for minimum mode, or

.tie the same pin to ground for maximum mode. Depending on

the mode chosen, the 8086 will issue all control signals

*(minimum mode) directly to memory and peripheral devices, or

issue status signals to a bus controller (maximum mode)

which, in turn, are decoded into the appropriate control

signals. The status signals issued by the maximum mode 8086

provide the information necessary for a local bus. This

local bus is used to provide the needed information and

control to attached co-processors in a multiprocessing

Lenvironment. Figure 14 illustrates the 8086 configured in

the maximum mode. The maximum mode is the mode chosen to be

implemented in this library. This is done to allow the use

of an attached numeric data processor (ND), the 8087. To

implement the 8087 ND?, current procedure requires the

system designer to change the value of the fit flag in the

sGLOBALS.DAT file from a zero (0) to a one (). This flag,

49

whci un r ecddit h prpraecnrl"1-[

~"...-Y,

Ili r"8 mo

&iEEE01'

C4a...LLLLLL aU)N

N3

OD ID

00 >

LE- -4C

ALx

C.CD

500

in turn, calls the 8086 CPU primitive that is configured for

exchanging request/grant and queue status signals from/to

the 8087.

Timing for the system is provided by an Intel 828,4

clock generator, running at 8MHz. This device requires an

external 3-times, or 24MHz, crystal for proper operation. In

case the option to use the 8087 NDP is chosen, the clock

generator must provide a 5MHz frequency using a 15MHz

crystal. This is provided for, within the structure of the

hardware primitive.

To ensure the proper power levels are available at the

data ports of memory, two Intel 8286 octal bus transceivers

are used as line drivers. Each transceiver provides 2-way

drive for the upper and lower bytes of the 16-bit data word.

Due to the multiplexing of addresses and data on the

external pins of the 8086, a requirement exists to latch the

address to some other device to allow the data to be made

available at some of these same pins. Three Intel 8282

octal latches provide this latching mechanism.

2. Memory and Memory Support Chips

Two types of memory are required to support any

system generated. First is some form of ROM -hat will

subsequently receive the instruction code from the software

listing. Second is the RAM to be used for data storage and

as stack memory as well as RAM for the I/0 memory space.

51

, , , , - !,., ..°% ,. ,°•• - .. , - ', , •".'."• . - , . " .' , , ' .,,' ' ,' ,% .•, • -°° 51." .%

.. ., , ... . .° • ° o °o "e". " °. °e ° % ° ° 0 . .o. ,.e , oo o . .. ..

I

The ROM used in this library are two Intel 27128 16K

by 8-bit ultra-violet EPROM's, one for the upper byte, one .

for the lower byte for every 16K block of memory needed for

the sy stem.

Data and stack RAM use sixteen Intel 2167-10 16K by .

1-bit static RAM, again, for every 16K block of memory

required. This particular memory device is selected to

meet the memory access speed requirements of an 8MHz CPU .

without the necessity for the insertion of wait states.

Although the instruction queue in the bus interface unit of

the 8086 contains prefetched instructions and data, thereby

eliminating most of the requirements to insert wait states,

a fast memory has been chosen to meet any immediate memory

access requirement (e.g. those imposed by jumps or branches).

No other memory options are available, even if the slower

5MHz clock is selected for use with the 8087 NDP.

Input/Output RAM use four Intel 2142 1K by 4-bit

static RAM as direct I/0 addresses that are available in

the 8086.

All ROM and RAM chips are supported by AMD 74LS244

octal three-state buffers as address line drivers integrated

into the design to ensure that no single address line has a

fan-out of more than 15.

Since 16K blocks of ROM, and data and stack RAM are

used, only address lines 1 through 14 (Al - A14), are needed

to select any one byte or word. The full memory is made up

52

"-o'.....

of 32 of these 16K blocks. Therefore, a memory decoding

scheme has been implemented to select i-of-32 16K memory

banks. Eight Intel 8205 l-of-8 binary decoders are used in

banks of four to select the even and odd byte of the

address. The decoders are all driven by address lines A15

through A19 and address zero (AO) for the odd address byte,

BHE for the even address byte, with both AO and BHE active

for an aligned 16-bit word (see Figure 15).

3. 8087 Numeric Data Processor

When used, the 8087 NDP extends the register and

instruction sets of the 8086 CPU for the purpose of

high-speed floating point operations. The hardware

implementation of the 8087 NDP is the standard local bus

arrangement as shown in Figure 16.

4. Other Hardware Support

Hardware support to meet various possible design

requirements is included in the library. Many of the

discrete components were taken from Ross' and Pollock's

original works and are included in the 8086 library for

continuity. A complete list and description of the

conponents are contained in Appendix A.

D. SOFTWARE DESCRIPTION

A listing of the software primitives and their-..o -

descriptions are contained in Appendix A. Items of particular

interest are discussed in more detail in this section.

53

~. . . .. . . . . . .- -... *--- ----- --.--- ,--*- .. % .. "

A17__ _ _ _

A18 _ _ _ - _ _ _ _ _

A19______ _

Chip Select Chip Select(upper) (lower)

8205 8205

32 32

A9 B9l

54 42

READY - - Interface IRESET - -2 Support

j IC's

p(See Figure. 14)

8086NPU

AO-A15

READY/

RT

Loca Bus

S/gnal

FigureQS 16. 807NmrcDt roesro oa u

55T

* . * *.. .*:~*~** . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . .

1. Monitor Section

The control or monitor section of the software

primitive list follows the convention found in the 8080

library. As shown in Figure 17, the monitor consists of a

pointer, a table and a section used to test each contingency

prior to the execution of its associated task.

A pointer is used to direct the checking of every

contingency described in the system's input file. Each

contingency is listed in the monitor table in order of

actual execution. The pointer's value is the address

associated with the current instruction being executed in _

the monitor table. After each contingency/task check and-

possible task execution, the value of the pointer is

increased to point to the next address in the monitor table.

Once the monitor table has been traversed completely, the

supervisor is executed, thereby resetting the v&lue of the

pointer to the address of the first instruction in the

monitor table. This process continues indefinitely until a

fatal error occurs or power is turned off to the controller.

2. Calculation Section

Most arithmetic primitives are straight-forward

applications of the available 8086 mneumonics. Unlike this

libraries predecessor's, where multiply and divide routines

contained many lines of code, the 8086 has nmemonics that

made these otherwise rigoruos tasks, a simple, single line

of code using the various types of the multiply (MUL) and

divide (DIV) instructions.

56

monitor section-

@spvsr: mov AX,@table ;initalize table pointermov @pntr,AX ;to beginning

@mlop: mov BX,@pntr ;monitor loopinc BXinc BXinc BXmov @pntr,BXimp BX

-data section -

org 1000 ;ram address pointer@pntr: dw 0 ;table entry address pointer

org 984171 ;rom address pointer@table: dw @pntr ;table header (define top)

imp @texl ;test for contingency exlimp @tex2 ;test for contingency ex2imp @tlstc ;test for contingency lstcimp @spvsr ;go to start of table

@texl: call @exl ;execute contingency code exlcmp exl,l ;compare contingency result to.-

,true flag (1)jnz $ + 5 ;if false do not execute stflgimp @stflg ;execute task stflg if trueimp @mlop ;return to monitor

@tex2: call @ex2 ;execute contingency code ex2cmp ex2,1 ;compare contingency result to

,true flag (1)jnz $ + 5 ;if false do not execute flag2imp @flag2 ;execute task flag? if trueimp @mlop ;return to monitorend ;software listing complete

Figure 17. Example Monitor Section

57

-- '7:I7"'-'L';'-'I'L--;'-° '-'- ".'-5"-"-- ..- ..- ............"...-.-..- ...... .....".................--...,.-.....-....--......-.-. . ..... " ....-j ..--

a. Arithmetic

All simple arithmetic operations, add, subtract,

multiply, and divide, are implemented for 8- and 16-bit

integer arguments.

(1) Variations in Simple Arithmetic Routines.

Along with the simple arithmetic operations, several error

checking primitives are available. These are currently used

by the system designer as line items in the intermediate

primitive list. Once listed in the intermediate file, that

specific primitive will be taken from the realization

library and used in the software output listing provided

that all timing requirements are met. In the future, the

designer that uses this system will be queried by the input

program whether to incorporate error checking in any or all

routines. In all cases, primitives that contain error

checking require more memory and take longer to execute than

those which have no checking. Many circumstances that arise

in the use of a fixed length word or byte as the storage.

size, provide more than enough bits to cover the range of

values of possible arguments. If the designer believes

that, for example, an 8-bit add would not cover the possible

values of the addends, and the actual result is an important

value, as opposed to selecting just the most significant

byte for example, then the 16-bit addition without error

checking could be used without a penalty of memory used or

execution time to implement the addition. An important

58

..... ... * *.. ....* **,.*

point here is that error checking and subsequent correcting,

in most cases, substitutes the largest value, either

negative or positive depending on whether overflow or

underf low occurred, as the value of the result of the Sarithmetic operation.

Multiplication operations provide several

options for the designer's use. These options include 8- by

8-bit or 16- by 16-bit multiplies with options to return an

unchecked 8- or 16-bit result, respectively. Also 8- by

8-bit or 16- by 16-bit multiplies, returning a 16- or 32-bit

result. Another option is the multiplication of the same

size values and returning an unchecked upper or lower byte

or word as the result. Appendix A contains a listing of

the software primitives as implemented in the realization

library of Appendix C.

b. Floating Point

All floating point operations use the Intel

short real format. This format is composed of 32-bits with

the sign of the mantissa in the most significant bit,

followed by an 8-bit signed exponent, and finally followed

by a 23 bit normalized mantissa, where the most significant

bit of the mantissa is implied to always contain a one. The

range available in this format is 8.43E-37 to 3.37E38 [Ref.

8]. To be used as data within a floating point primitive,

the library assumes that the 32-bits of the floating point

variable passed from the primitive list will be in the

59

.p..

proper double word format, as described above, with the most

significant word in the lower storage address and the least

significant word in the next higher address. For

compatibility with the 8080 library, this data is labeled in

byte format, from MSB to LSB, as exponent (exp), high .

mantissa (hmant), middle mantissa (mmant), and low mantissa

(lmant). This method of storing a floating point variable

is also compatible for use with the 8087 NDP. Figure 18

illustrates the composition of a floating point variable

using this format.

(1) Use of the 8087 Numberic Data Processor.

Current implementation of floating point arithmetic makes

use of the 8087 NDP only. No stand alone software for

floating point manipulations are included in the library.

However, provisions have been made to incorporate software-

only floating point operation by writing primitives to pack

and unpack floating point variables into and out of the short

real format for ease of manipulation within the arithmetic

routines. The unpack primitive separates the mantissa sign

bit, the exponent, and the mantissa into individual bytes,

words or double words and is then stored into a designated

scratchpad area in RAM. Upon completion of a floating

point operation, the values are packed into the proper format L

prior to being stored as the result. The current implemen-

tation must pack and unpack variables each time they are

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used, since there is no method to keep track of variables

that have been previously used during the execution of a

systems design.

The choice for using the 8087 NDP for all

floating point operations, as shown in Figure 19 [Ref. 9],

is speed. Without the 8087, a single precision floating

point addition would require about 6.2 milliseconds to

complete in an optimized environment. This takes into

account two single precision loads, one floating point

addition, and one single precision store. This is in

comparison to 53 microseconds that an 8087 NDP would require

to accomplish the same operation. This is a betier than a

100 times improvement over the 8086 software floating point

addition. In many cases, for a real-time controller design,

6.2 milliseconds will not satisfy speed requirements for

multiple floating point computations.

Prior to any 8087 floating point operation,

the NDP must be initialized by the loading of a control word.

The control word provides programming options for allowing

or disallowing the recognition of interrupts, precision

specification (data type selection), rounding control,

infinity control and exception handling options. The '

control word used in the initialization of the 8087 NDP in

the library are selected as follows:

62

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7. 7 .7 7

• .

APPROXIMATE EXECUTION TIMEINTRUCTION (MICROSECONDS)

Aon

ADD SIGN-MAGNITUDE 14 1600SUBTRACT SIGN-MAGNITUDE 18 1600MULTIPLY (SINGLE PRECISION) 19 1600MULTIPLY (DOUBLE PRECISION) 27 2100DIVIDE 39 3200COMPARE 9 1300LOAD (DOUBLE PRECISION) 10 1700STORE (DOUBLE PRECISION) 21 1200SQUARE ROOT 38 19600TANGENT 90 13000EXPONENTIATION 100 17100

Figure 19. Speed Comparison Between 8087 NDP and 8086

63

4771

~~* * * * . * * ... . X . .. * .. * * *** * -*** * ~*** *.* , - +.::.

1) interrupts disabled2) short real data type (24 bits of precision)3) round to nearest value or even4) projective infinity control ""

Items 1 through 3 are self explanatory.

Item 4, projective infinity control, provides the control

necessary to close the system of numbers in the 8087.

Although affine closure provides more information than

projective, there is a greater chance for misinformation

by using the affine closure mode if, for example, the

reciprocal of plus or minus zero is computed. Figure 20

shows that the result of this computation would give two

different results for the same values in the operation.

The projective mode never returns misinformation and is

therefore the suggested mode for use when the values of an

operation are not known in advance. [Ref. 10]

Due to the serial nature of the processing

environment of CSDL and the 8086/8087 structure within the

environment, optimal use of the processing group is

sacrificed for the stand-alone speed capabilities of the 8087.

As shown in Figure 21a [Ref. i], the 8086 in a co-processing

environment with the 8087 is afforded the ability to

continue fetching and executing its instruction stream while

the 8087 is performing a more involved floating point

operation. Once the 8087 has completed its task, it

interrupts the 8086 just long enough to store the result of

its previous computation. In this library implementation,

614

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Projective closure provides a completely closedset of numbers, thereby never providing omisinformation.

variables are not always known

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65

. .. . .

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as the environment of system design forces serial

calculations, the 8086 is immediately dependent on the

outcome of the 8087's current calculation. This requires

the 8086 to enter an unproductive idle state as shown in

Figure 21b. The overall calculation speed of this system is

increased, however, at the expense of adding 8087 NDP

hardware for floating point operations. A tradeoff in

overall system speed must be made when the 8087 NDP is used,

since the 8086 CPU must be slowed to a 5MHz rate with the

addition of the 8087 hardware.

(2) Emulation of the 8087 Numeric Data Processor.

If speed is unimportant in a particular realization which

contains floating point operations, and the decision not to

use the 8087 NDP is made, an alternative to creating complete

software-only primitives for floating point calculations is

the use of the 8087 emulation package that provides the

software equivalent of the 8087. With this package installed,

no difference exists between a routine that will run on the

8087 or 8086 emulation of the NDP. The decision to use the

8087 hardware is made at link time, with no further re-assembly

required to produce the proper 8086 code [Ref. 12]. All that

is required, in this case, would be to substitutethe values

for execution cycles in the software primitives of the library

to ensure an accurate timing analysis is performed prior to.o * S***-

the generation of the system design listings.

66

77-",-

Figure 21a. Normal Co-processing Environment

*T . .* ,_

ESCape codes signal co-processors that the next .I

several bytes of instruction is co-processorexecutable code.

8087 Exit 8087 completes its

process and signalsE Cwaiting 8086 --:

8086 continues 8086 continuesprocessing in processing inco-processing singleenvironment processor

environment

Figure 21b. Co-processing Environment in 8086Library

88Ext 8087 signals 8086•.-.

-.. :':" ~of its completion '":":-.

8086 immediately 8086 continuesgoes into wait state in single

processorenvironment

"- Figure 21. Use of ESC Codes in a Co-processing Environment

67

. .- .----,..

3. Logical Functions

Included in this library is a complete set of

software primitives to perform logical operations. These

include 8- and 16-bit and, or, not, xor, eq, it, le, gt, ge,

and ne. All of these primitives are compatible with those

in the 8080 and Z-80 libraries.

4. Other Software Functions

Among the remaining primitives contained in this m.library are program control and input/output control.

Program control includes those primitives required to

establish storage areas for constants, set up variable

storage areas, define line labels to be used for conditional

jumps, jump on true or false, as well as primitives to set

up for-loops, while-do loops, and establish and call

procedures. A fixed-length delay primitive allows the

designer to specify a delay, to wait for an input for

example, in increments of 5 microseconds for both the 8MHz

and 5MHz design versions.

Input/Output control provides for 8- or 16-bit

input/output bytes or words. The software primitives are

taken from the original 8080 library.

68

, "o °

V. TESTING OF SOFTWARE PRIMITIVES

& A. PRIMITIVE TESTING VEHICLE jSoftware primitives for this library were developed and

tested on the Naval Postgraduate School Mathematics

Department's North Star Computer, Inc., "Horizon" computer

system, augmented with an Octagon Computer System's "Octagon

Board 8/16" plug in processor board. This S-100 board gives

to the normally Zilog Z-80 based "Horizon" an 8086/8087

processor capability. The 8087 Numeric Data Processor is

not currently installed on th 8/16 board. Those primitives

that make use of the 8087 NDP are, therefore, not

operationally tested. Primitives that use 8087 code are

taken in part from examples given in the book, 8087 by

Richard Statz [Ref. 13]. Although these 8087 primitives may

not function properly, if implemented, they are included as

a starting point for future investigation.

In conjunction with the use of the "Horizon" computer,

the testing environment operated under CP/M-86. Ai.I

programs written for verification purposes to be used as

primitives in this library were assembled using ASM-86. It

should be noted that other assemblers may have directives

that do not equate to those directives used in this library,

L' and any assembly errors may be due to the incompatability of

these directives.

69

B. TESTING OF CONTROL LOGIC

All primitives that contain 'if' lines, and therefore

have conditional branches, have been tested for all possible

branches. For example, the addition of an 8087 NDP requires

that the clock period attribute be changed from 0.125

microseconds to 0.2 microseconds, the crystal used with the

8284 clock generator be changed from 24MHz to 15MHz, and

all the associated changes be made to accommodate the slower .,

overall system speed. In this example, the FLT global

variable is used as a flag to signify the addition of the

8087.

70

....................................................

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*"°

VI. RECOMMENDATIONS AND CONCLUSIONS

, A. RECOMMENDATIONS

1. Universal High-Level Language Realization Library

A large scale reproduction of basic software 7

primitives required to create another realization library is

far too labor intensive to be performed for each new

microprocessor family. The following paragraphs explain how

this section of library creation may be avoided.

A single high-level language library created by

developing software primitives, would provide instant

compatibility between different microprocessor families.

Once a high-level language library is written, the use of a

cross compiler/assembler could be used to construct the

actual library used by the timing analyzer and formatter.

Cross compilers are currently available to convert C

language programs to any number of target microprocessor

machine code programs [Ref. 141. The hardware portion of

the new library would still be constructed component by

component. After the cross compiler produces an assembly

language/machine code file for timing analysis, the

appropriate hardware primitives are appended to the assembly

language file. Another volume of timing and size primitives,

constructed to match the microprocessor, would provide the

number of cycles and bytes required to realize a given

71

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design. This timing/size companion volume would simply be

a rewritten version of the new microprocessor's index of

mnemonics, usually provided in the processor programming

guide. An example of this process is shown in Figure 22.

2. Hardware Wiring Diagrams

The current method to implement hardware components

is left to the realization library author. Although pin-out

descriptions are simple, several areas in the hardware text

section is free-form. With the potential to diagram the

hardware realization to a high resolution graphics terminal,

a more structured format in the hardware section is suggested.

B. CONCLUSIONS

The integration of the Intel E086 microprocessor

realization library into the overall design capabilities of

CSDL offers comparable primitives to that of the original

works by Ross and Pollock. A universal globals file

(globals.dat), as constructed in this paper, must be

maintained to allow the design criteria section of CSDL to

migrate from microprocessor to microprocessor library to

generate the desired system by meeting the design

specifications. This option was not maintained by Smith in

his prototyping scheme for the Z-80 realization library, and

therefore, his specialized globals are not included in the

universal globals file. Libraries constructed for use by 75

this design system should continue to be produced in order

72

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choose. With the eventual integration of a "user friendly" .

input method, CSDL will provide an advanced environment in

which to design and implement real-time microprocessor-based

controllers.

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APPENDIX A

DEFINITIONS OF PRIMITIVES

List of hardware and software primitive functions. Theprimitive definitions preceded by an (*) are from the 8080library that are also used in the 8086 library.

h.adc. * Defines an 8-bit analog to digitalconverter

h.adc2 * Defines a 8-bit processor-controlled analogto digital converter.

H.bufframp * Defines a buffer input amplifier.

h.capac-cer * Defines any value ceramic capacitor.

h.clckctrs * Defines a 16-bit TTL counter for a freerunning clock.

h.conn-al * Defines dip socket used as an analogconnector.

h.conn26sep * Defines a 26 pin flat cable connector.

h.dac * Defines a 8-bit digital to analogconverter.

h.diode-sw * Defines a silicon switching diode.

h.diode-znr * Defines a zener diode.

h.drvr Primitive to implement address line driversas more 16K banks of memory are added tothe hardware realization.

h.eprom Defines the pin-out of an Intel 27128 128kultra-violet erasable programmable read-only memory.

h.ffjk * Defines a TTL flip-flop.

h.follower * Defines a voltage follower.

h.herr Performs a simple check to determine ifROM space overflows into RAM space andprints a warning message if an overflowoccurs.

75

55. C.

h. invert Defines a TTL inverter.

h.ioram Defines the pin-out of an Intel 2142 4kstatic RAM for input/output memory.

h.issuecond ' Defines an 8- or 16-bit condition-typeoutput hardware.

h.issuesepcd * Defines a single bit output. 0

h.issuevent * Defines event-type output hardware.

h.memory Calculates the required read-only andread-write(ram) memory chips requiredto implement the current design. .-

It also assigns the chip select linenumbers generated by the address decoderhardware primitive that is contained in theprocessing unit primitive, h.processor.

h.nand2 * Defines a 2 input discrete nand gate.

h.nand3 *Defines a 3 input discrete nand gate.

h.nand4 * Defines a 4 input discrete nand gate.

h.nand8 * Defines an 8 input discrete nand gate.

h.ndp Defines the pin-out of the Intel 8087Numeric Data-Processor for high speedfloating-point calculations.

h.nprocessor Defines the pin-out of the Intel 8086-28MHz microprocessor for use with an Intel8087 Numeric Data Processor.

h.oneshotl * Defines a TTL edge triggered, retriggerable

one shot.

h.opamp * Defines operational amplifier hardware.

h.opisol2 * Defines a slow photo darlington opticalisolator.

h.optoisol * Defines optically isolated logic device.

h.oscxtal * Defines a modular crystal oscillator.

h.peripdrivr * Defines peripheral driver hardware.

76

* . . . .. . . .~~ % -. %;. *..• .. **..-°-.*.|

h.processor Defines the pin-out of the Intel 8086-28MHz microprocessor for use without anyattached coprocessor.

h.ram Defines the pin-out of the Intel 2167 16k - .static read/write(ram) memory chip.

h.relaydpdt * Defines a double-pole double-throw relay.

h.resmfqtrwt * Defines 1/4 watt metal film 1% resistor.

h.rpack-18b * Defines 8 resistor, 180 ohm each, resistorpackage in a 16 pin dip.

h.rs232conn * Defines rs-232c input/output connection.

h.rs232rx * Defines an rs-232c receiver.

h.rs232tx * Defines an rs-232c transmitter.

h.sensecond * Defines 8- or 16-bit condition-type inputhardware.

h.sensepcond * Primitive to define a single bit inputdevice.

h.sensevent * Primitive to define an event-type input

hardware.

h.striginvrt * Defines a TTL schmidt trigger inverter.

h.support Defines the support IC's required for usewith both variations of the 8086 processor.This includes the following chips:

1. Intel 8284 Clock Generator and driver.2. Intel 8286 Bus Transceiver.3. Intel 8288 Bus Controller.4. Intel 8282 Octal Latch. -4

5. Intel 8205 l-of-8 Decoder.

h.trimpot * Defines a variable resistor of (r) ohms witha 1/2 watt trimpot.

h.uart * Primitive to define a UART.

s.8087cw Routine to load the 8087 control word priorto the first 8087 NDP operation. Thecontrol word specifies:1. Intel short form for floating point

data representation.

77

/.°'

2. Rounding to nearest or even value.

3. Projective infinity control.

s.add Primitive to add two 8- or 16-bit integernumbers.

s.addck Primitive to add two 8- or 16- bit integernumbers with overflow and underflow checks.If an overflow error exists the largestpositive number is stored as the result.On an underflow condition, the largestnegative number is then stored as theresult.

s.anain ' Primitive to define a processor-controlledanalog input.

s.analogin * Primitive to define an analog inputcondition.

s.anaout * Primitive to define an analog outputchannel.

s.and Primitive to perform a logical 'and' of two . -

8- or 16- bit numbers.

s.assign f Primitive to assign an 8- or 16-bit valueof one variable to another variable.

s.assigncons * Primitive to assign an 8- or 16-bitconstant to a variable.

s.clock * Primitive to define a free running timeclock.

s.cons Primitive to define a data constant to beused at program assembly time.

s.div Divide routine for 8- or 16-bit unsigneddivision.

s.end Defines the end of the output assemblylanguage listing.

s.eq Primitive to determine if two 8- to 16- bitintegers are equal.

s.eventmark * Primitive to establish interrupt handlerfor event.

78- .1

s.every Primitive to define dummy function forevery-period statement.

s.exitproc Closes a procedure and resets the associatedcontingency.

*s.fadd Routine to perform floating point addition.

s.fassign Routine to assign the value of one floatingpoint variable to another floating pointvariable.

s.fcons Routine to define storage for a floatingpoint constant in short real form.

s.fdiv Routine to perform non-numeric dataprocessor floating point divide.

s.f ix Routine to convert a floating point valueto an integer value.

s.fixedwait Routine to delay a fixed period of time in-5 microsecond increments for an 8MHz clock.

s.fixedwait5 Routine to delay a fixed period of time in5 microsecond increments for a 5MHz clock.

s.float Routine to convert an integer value intoa short real format floating point value.

s.fmul Routine to perform non-numeric dataprocessor floating point multiply.

s.forcons Defines the start of a constant bounds loop.

s.forend Defines the end of a constant bounds loop.

s.fpack Routine to pack an unpacked floating pointresult of a non-numeric data processorfloating point operation. This puts theresult of a non-numeric data processorfloating point operation back into memoryin short real form. (See s.funpack).

s.fesub Routine to perform a non-numeric data Lprocessor floating point subtraction.

79

• .r - .. - .* ..s .asg-Ruiecoasg. evle-foeflaigd

s.funpack Routine to unpack a floating point argumentprior to a non-numeric data processorfloating point operation. The argument is -stored in short real form prior to -

unpacking. (See s.fpack).

s.fvarset Primitive to establish a scratch-pad inmemory to handle non-numeric data processorfloating point operations.

s.ge Determines if argumentl is greater than orequal to argument2 for 8- or 16-bitnumbers.

s.gt Determines if argumentl is greater than 5argument2 for 8- to 16-bit numbers.

s.heading Primitive to define assembly languagesoftware heading.

s.imull6 Primitive to multiply two 16-bit signedinteger numbers without overflow checkingand returns a 16-bit' result.

s.imul8 Primitive to multiply two 8-bit signedinteger numbers without overflow checkingand returns an 8-bit result.

s.imulexl6 Primitive to multiply two 16-bit signedinteger numbers and returning a 32-bitresult.

s.imulex8 Primitive to multiply two 8-bit signedinteger numbers and returning a 16-bitresult.

s.imuloml6 Primitive to multiply two 16-bit signedinteger numbers with overflow and under- .flow checks. On overflow, the maximumpositive 16-bit signed number is returnedas the result. On underflow, the maximumnegative 16-bit signed number is returnedas the result.

s.imulom8 Primitive to multiply two 8-bit signed !Linteger numbers with overflow and under-flow checks. On overflow, the maximumpositive 8-bit signed number is returnedas the result. On underflow, the maximumnegative 8-bit signed number is returnedas the result. b

80

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s.imulul6 Primitive to multiply two 16-bit signedinteger numbers returning the upper 16bits as the result.

s.imulu8 Primitive to multiply two 8-bit signedinteger numbers returning the upper 8 bitsas the result.

s.in Routine to set the timed block flag.

s.issuecond Routine to send condition-type output.

s.issueopcnd * Primitive to define an optically isolateddigital output.

s.issuevent * Primitive to send event-type output.

s.jmpf Routine to branch on false condition.

s.jmpt Routine to branch on true condition.

s.le Determines if argumentl is less than orequal to argument2 for 8- or 16-bitnumbers.

s.loc Routine to define a label.

s.lt. Determines if argumentl is less thanargument2 for 8- or 16-bit numbers.

s.main Primitive for software initialization.Sets event, port, rom and ram pointers and -calls hardware processor primitive andsoftware heading primitive.

s.monitor Primitive to define the p2 monitor ascontroller supervisor.

s.mul Primitive to multiply two 8- or 16-bitunsigned integer numbers without errorchecking. Returns 8- or 16-bit results.

s.ne Determines if argumentl is not equal toargument2 for 8- or 16-bit numbers.

s.nfadd Routine to perform numeric data processorimplemented floating point addition.

s.nfdiv Routine to perform numeric data processorimplemented floating point divide.

81*1 .- '

'. -MMIT1717-. -

s.nfmul Routine to perform numeric data processorimplemented floating point multiplication.

s.nfsub Routine to perform numeric data processorimplemented floating point subtraction.

s.ni Primitive to clear timed block flag.

s.nopck Routine to handle overflow and underflowconditions resulting from 8087 NDParithmetic operations.

s.not Performs 8- or 16-bit logical 'not'.

s.or Performs 8- or 16-bit logical 'or'.

s.perform Routine to invoke a procedure.

s.proc Used to define a procedure entry point.

s.relayout * Primitive to define a relay output.

s.restans * Primitive to define a resistance transducer.

s.senscontac * Primitive to sense a contact closure.

s.sensecond Primitive to detect condition-type input.

s.sensevent * Primitive to detect an event-type input.

s.senshotct * Primitive to detect a hot contact.

s.sensopcond * Primitive to define an optically isolatedcondition input.

s.sensopevt * Primitive to define an optically isolatedevent input.

s.start Dummy start primitive.

s.sub Primitive to subtract two 8- to 16-bitnumbers.

s.tabaccp2 Subroutine to add routine access for

contingency/task pair. "

s.tabend Defines the end of the monitor table.

s.tabent Primitive to add an entry to the monitor

table.

82 v.'.'

-------------------:-:.

s.temp * Primitive to define temperature measurementchannel.

s.var Routine to define storage for 8- or 16-bitinteger variable.

s.whend Primitive marking the end of a while-dostatement.

s.whilecon Primitive to generate a while-do conditionsection head.

s.xor Perform 8- or 16-bit logical 'exclusive or'.

, . ...

83

% -%-"-

. . . . . . . . . . . . . . . . . .. . ... '-. . ....-. . . . . . . . . . ': -. . . .. .

APPENDIX B

LIST OF GLOBAL VARIABLES

The following global variables list is used by therealization library given in Appendix C. This list incor-porates all the global variables used in the 8080 and 8086libraries, allowing compatibility between the two and thusnot requiring any user intervention in system choice ofmicroprocessors selected during system generation. The valuein parenthesis following each variable is its initial value.

CN (0) Counter for capacitor reference designator.

CNT (0) Counter for use during calculation in thefixed wait primitive.

CRN (0) Counter for diode reference designator.

CWORD (0) Flag for loading 8087 NDP control word(8086 Library bnly).

DIV (0) Flag indicating inclusion of divisionsubroutines.

EVADDR (0) Event address.

EVPNT (0) Event pointer.

FLT (0) Flag indicating the use of floating pointprocessor.

ICN (0) Counter for integrated circuit referencedesignator.

INE (1) Element counter for multi-element invertor.

INN (0) Reference designator for multi-elementinvertor.

INPORT (0) Pointer to next available input port.

ISCE (1) Element counter for bit slice output port.

ISCN (0) Reference designator for bit sliced outputport IC.

ISCP (0) Pointer to bit sliced output port.

84

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ISNE (1) Element counter for multi-element Schmitt-trigger invertor.

ISNN (0) Reference designator for multi-elementSchmitt-trigger invertor.

JAASE (1) Element counter for bit sliced I/Oconnector.

JAASN (0) Reference designator for bit sliced I/Oconnector.

JKE (1) Element counter for multi-element JfKflip-flop.

JKN (0) Reference designator for multi-element J/Kflip-flop.

JN (1) Counter for connector reference designator.

KN (1) Counter for relay reference designator.

LATFLG ('0) Flag for pulse event inputs requiringlatching.

MEM (0) Pointer used in ROM/RAM partition.

MPRTA (0) Pointer to data I/0 port of hardwarefloating point processor.

MPRTB (0) Pointer to control I/O port of hardwarefloating point processor.

MUL (0) Flag indicating inclusion of multiplicationsubroutines.

NBE (1) Element counter multi-element 2 inputnand gate.

NBN (0) Reference designator for multi-element 2input nand gate.

NCE (1) Element counter for multi-element 3 inputnand gate.

NCN (0) Reference designator for multi-element 3input nand gate.

NDE (1) Element counter for multi-element 4 inputnand gate.

85

°. . " . -\- . - . - X .-. . .. °. ° .* . . . ,*. '

NDN (0) Reference designator for multi-element 4input nand gate.

ODT (0) Flag for use of debugging package

(8080 Library only).

OUTPRT (-I) Pointer to next available output port.

PDE (1) Element counter for multi-elementperipheral driver.

PDN (0) Reference designator for multi-elementperipheral driver.

RABE (1) Element counter for multi-element resistor

pack.

RAMPTR (0) Pointer to next address in RAM.

RN (1) Counter for resistor reference designator.

ROMPTR (0) Pointer to next address in ROM.

RPN (1) Counter for resistor pack referencedesignator.

RSDE (1) Element counter for multi-element RS-232Cdriver.

RSIC (0) Reference designator for multi-elementRS-232C driver.

RSRIC (0) Reference designator for multi-elementRS-232C receiver.

RSRE (1) Element counter for multi-element RS-232Creceiver.

SCRTCH (0) Scratch register.

SSCHE (0) Element counter for bit sliced input port.

SSCP (0) Pointer to bit sliced input port.

ZMBLCK (0) Flag for timed block.

TOTEVT (0) Total count of event type inputs.

86

APPENDIX C

8086 CPU REALIZATION LIBRARY b

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LIST OF REFERENCES

1. Daniel, M.E. and Gwyn, C.W., "CAD Systems for IC Design", .IEEE Transaction on Computer-Aided Design of IntegratedCircuits and Systems, v. CAD-l, pp. 2-3, Jan 1982.

2. Matelan, M.N., "Automating the Design of DedicatedReal Time Control Systems", Preprint UCRL-78651,Lawrence Livermore Laboratories, 21 August 1976.

3. Heilstedt, M.R., Automated Design of Microprocessor-Based Digital Filters, MS Thesis, Naval PostgraduateSchool, Monterey, California, p. 23, 1983.

4. Ross. A.A., Computer Aided Design of Microprocessor- S.Based Controllers, Ph.D. Thesis, University ofCalifornia, Davis, 1978.

5. Carson, T.H., An Input Translator for a Computer AidedDesign System, MS Thesis, Naval Postgraduate School,Monterey, California, 1984.

6. Smith, T.J., Implementation of a Zilog Z-80 BasedRealization Library for the Control System Designnvironment, MS Thesis, Naval Postgraduate School,Monterey, California, 1984.

7. Pollock, G.G., Further Development and Investigationof Computer-Aided Design of Microprocessor Systems,MS Thesis, University of California, Davis, 1980.

8. iAPX 86/88,186/188 User's Manual, v. 2, p. 6-5, IntelCorporation, 1983.

9. Ibid., p. 6-3.

10. Ibid., p. 6-18.

11. Ibid., p. 4-5.

12. Ibid., p. 6-6.

13. Statz, R.J., 8087, Prentice-Hall, 1983.

14. Kern, C.O., "Five C Compilers for CP/M-80", Byte,v. 8, pp. 123-124, 1983.

16..

169 ."-°.%.."

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•-- Z I N7. - ..- . - .- -- - -

INITIAL DISTRIBUTION LIST

No. Copies

1. Defensd Technical Information Center 2Cameron StationAlexandria, Virginia 22314

2. Library, Code 0142 2Naval Postgraduate SchoolMonterey, California 93943

3. Professor H. H. Loomis, Jr., Code 62Lm 4.. Department of Electrical and

Computer EngineeringNaval Postgraduate SchoolMonterey, California 93943

4. Lieutenant Colonel A. A. Ross, USAF, Code 52Rs 2Department of Computer ScienceNaval Postgraduate SchoolMonterey, California 93943

5. LCDR Alan Cetel, USN 2Naval Sea Systems Command HeadquartersWashington, D.C. 20362

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1D-814586 IMPLEMENTATION OF RN INTEL 8686 … · 1D-814586 IMPLEMENTATION OF RN INTEL 8686 MICROPROCESSOR-BASED 1/2 ... and the Intel 8080 library was desired and achieved by use