14_AIC Interrupt- Register Ownership

8/10/2019 14_AIC Interrupt- Register Ownership

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TM

Freescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarks

of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006.

AIC Interrupts and Registers

Ownership/Distribution across PAand DSP cores

Alok Saxena


2/22

Agenda

Interrupt distribution/ownership between SDOS and Linux

Register ownership between SDOS and Linux

TMFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarks

of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006. 1


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AIC Interrupts

Maple Block



AIC Block

Programmable RegistersFor Interrupt Re-Direction

Interrupts to Maple only

Common Interrupt Sources

Interrupts to DSP only Interrupts to PA only


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ipi_aic_error_int Transmit IQ (DMA) Underrun Interrupt

Sources from AICDMAnISR Register bit 19 --- Transmit IQ (DMA) Underrun

Interrupt due to AIC not having received enough bandwidth on the internal MBusand therefore it cannot read the data from the antenna buffers in the systemmemory

Should be owned by DSP

Receive IQ (DMA) Overrun Interrupt




Sources from AICDMAnISR Register bit 3 --- It indicates that the AIC has notreceived enough bandwidth on the MBus bus and therefore it can not write the IQdata to system memory

Should be owned by DSP

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ipi_sniff_frame_int[1:0] Dedicated interrupt line from each of the 2 Sniffer Blocks

Sources from AICSNIFFnFRMINT Register --- Once the reference counter

running on the reference clock reaches to 0, this interrupt starts again at periodictime interval

Should be owned by PA as PA Is required to drive the iterative processing across theDSP and Sniff logic --- will be required to support Synchronization of Femtocell from aMacro overlaid which is being sniffed by this block --- not required to be supported for




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ipi_si_prg_pretimed_dl_int[3:0] programmable pre-timed DL interrupt for the DSP from AIC lanes

Obviously irrelevant to PA and meaningful for DSP only on the DL transfer in the

context of NCDMA ( MAXPHY Lanes 1,2, 3 on one pin) and WCDMA (ADI Lane1, 2 and 3 corresponding to interrupts 0, 1 and 2/3)




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ipi_tti_ul_int[4:0] This is a timing interrupt for DSP. The source of this interrupt is AICs

internal RF Timer in each lane Very dedicated timing interrupt for DSP for L1 UL Receive chain processing

ipi_aic_int Various sources of this interrupt are from DMA based on the threshold

crossings within the FIFOs . These sources are per lane. Upto six such lanes



are concen ra e on e s ng e p _a c_ n p n Obviously needed by DSP alone for UL/DL data transfers

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ipi_sniff_capt_comp[1:0] AIC Sniff Capture complete interrupt from each of the 2 sniffer blocks

At sniff capture completion, this interrupt will be processed by the PA and PA will

then initiate the processing of Sniff algorithm in DSP




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ipi_frame_int[3:0] This interrupt implements the frame count based on counting the number of

chips that would have been transmitted/recieved on the RF interface since

the RF interface is up Obviously required by the CDMA, WCDMA L1 processing in DSP

ipi_nxt_rx_sym_int[4:0] This is a timing interrupt generated from the RF Timer.



or mo e, e n errup m ng n ca es e arr va o an sym o on e

Baseband RF interface.

For WDCMA and NCDMA mode, this interrupt comes every 16 chips

Symbol ticks directly required by DSP for L1 processing in any RAT type

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ipi_nxt_tx_sym_int[5:0]

ipi_maple_rx_riqt_int[1:0]

ipi_maple_tx_tiqt_int[1:0]

ipi_wcdma_frame_int

ipi_tti_dl_int[5:0]

Required set of interrupts directed to Processing Engines in MAPLE for UL/DL processing in

---



agnostic to core type

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This is actually a sub-set of the overall interrupt set that is directedtowards DSP and Maple in the previous foils ipi_aic_adin/max_int

This is a common interrupt for the sources mentioned below. ipi_frame_interrupt[n] : Frame interrupt from RF Timer ADI Lane n / MAXPHY Lane 1-3

ipi_sfn_int[n] : Superframe interrupt from RF Timer ADI Lane n / MAXPHY Lane 1-3

ipi_tti_ul_int[n] : UL TTI Interrupt from RF Timer ADI Lane n / MAXPHY Lane 1-3

ipi_tti_dl_int[n] : DL TTI Interrupt from RF Timer ADI Lane n / MAXPHY Lane 1-3



ipi_si_prg_pretimed_dl_int[n] : Programmable DL TTI interrupt from RF Timer ADI Lane

n / MAXPHY Lane 1-3

ipi_pps_out_int[n] : PPS out from the RF Timer ADI Lane n / MAXPHY Lane 1-3

Except for ipi_tti_dl_int[n] and ipi_pps_out_int[n] , the other interrupts as notedbefore should be handled by DSP

The requirement for PA processing of ipi_tti_dl_int[n] is still being discussed as

from the viewpoint of PA being the timing master for L1/L2 interface timing is notour case however this may be needed for the TTI awareness of L2 while weswitch the RAT for Network Sniff

ipi_pps_out_int[n] is required for PA filtering the timing corrections for VCTCXO

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PA dedicated Interrupt Set ipi_aic_sniff_int

This is a common interrupt line which concentrates all the following fourinterrupts from the two sniffer modules ipi_sniff_capt_comp[0] ipi_sniff_capt_comp[1]

ipi_aic_sniff_frame_int[0]

ipi_aic_sniff_frame_int[1]



required to support the sniff operation for clock synchronization with an overlaid Macroetc, PA should own interrupt handling to drive the required initializations of sniffalgorithm in DSP core

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Receive IQ MBus Transaction Size (AICDMAnRIQMTS) Should be owned by DSP as it is on the CLASS bus and it is more

appropriate for it to define the Write IQ Mbus Transaction size

Transmit IQ MBus Transaction Size (AICDMAnTIQMTS) Should be owned by DSP as it is on the CLASS bus and it is more

appropriate for it to define the Read IQ Mbus Transaction size

Receive IQ MBus Priority Level 1 (AICDMAnRIQMPL1)



----

number of valid bytes in the RIQMPL1 field

Receive IQ MBus Priority Level 23 (AICDMAnRIQMPL23) Should be owned by DSP ---- same reason as above in defining the

number of valid bytes in the RIQMPL2/3 field

Transmit IQ MBus Priority Level 1 (AICDMAnTIQMPL1) Should be owned by DSP ---- same reason as above in defining the

number of valid bytes in the TIQMPL1 field

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Maximum Symbol Size (AICDMAnMSS) Should be initialized by PA as it configures the Network mode and

hence in a better position to define the corresponding MSS

Receive IQ Base Address m (AICDMAnRIQBAm) Should be initialized by DSP as it is the one that is handling the run-time

received data in the buffer

Receive IQ Buffer Size (AICDMAnRIQBS)



---

Receive MAPLE Base Address (AICDMAnRMBA) Anyone can do it ---- but being on the CLASS bus it may be more

appropriate for DSP to do it

Receive MAPLE Buffer Size (AICDMAnRMBS) Anyone can do it ---- but being on the CLASS bus it may be more

appropriate for DSP to do it

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Transmit IQ Base Address m (AICDMAnTIQBAm) Should be initialized by DSP as it is the one that is handling the run-time

transmitted data in the buffer

Transmit IQ Buffer Size (AICDMAnTIQBS) Should be initialized by DSP --- same reasoning as above

DMA Mode Select Register(AICDMAnDMSR) Both can do it in general however we cannot change the fields of this



permitted --- we can let PA own the configuration of this register

DMA Control Register (AICDMAnDCR) Should be owned by DSP as activation/deactivation of the receive and

transmit pipes of the DMA can be changed during normal operation so

the DSP can do error handling on FIFO under-run/over-run scenarios

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Receive IQ Threshold Register (AICDMAnRIQT)

Receive IQ First Threshold (AICDMAnRIQFT)

Receive IQ Second Threshold (AICDMAnRIQST)

Transmit IQ Threshold (AICDMAnTIQT) Transmit IQ First Threshold (AICDMAnTIQFT)

Transmit IQ Second Threshold (AICDMAnTIQST) Should be owned by DSP for obvious run-time reasons



Interrupt Enable Register (AICDMAnIER) Should be owned by DSP as most of the above interrupts are handled

by DSP

Interrupt Status Register (AICDMAnISR)

Should be owned by DSP as it can poll the status of receive IQ eventany time during the operation

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MAPLE Interrupt Acknowledge Register (AICDMAnMIAR) Maple-AIC DMA flow control ---- closer to DSP to own it

DMA Status Register (AICDMAnDSR) Good for DSP to own it as it will help DSP in determining the status of

transmit/receive DMA

Receive IQ Buffer Displacement Register (AICDMAnRIQBDR)

Transmit IQ Buffer Displacement Register (AICDMAnTIQBDR)



ore re evan or as po n s o e curren sp acemen n y esof the receive/transmit data in the IQ data buffers in system memory

AIC Frame structure Configuration register (AICFRAMCONF) PA should own as it is one time configuration of the Frame structure of

the RAT type in use

AIC Network Mode Configuration Register 1 (AICNETWCONF1) PA should own it --- same reasoning as above

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AIC Symbol Configuration register n (AICSYMnCONFm) PA should own it --- same reasoning as above

AIC Interrupt Pretiming Register (AICnINTPRETIME)



s ou own t --- same reason ng as a ove

AIC UP Link and Down Link delay Register (AICDLULDELAY) PA should own it --- same reasoning as above

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AIC Timer Control Register AICLANEnTMCTRL PA should own it --- basic one time Lane Timer control data like GPS

enabled or not, Network Mode type etc

AIC Sniff Reference Counter (AICSNIFFnREFCNT) PA should own it --- part PA initializations in Sniff Algorithm initiliazation

AIC Sniff Reference Counter Offset(AICSNIFFnREFCNT_OFF) PA should own it --- same reasoning as above



n ap ure se n _ PA should own it --- same reasoning as above

AIC Sniff Chip Capture Duration(AICSNIFFnCAPT_DUR) PA should own it --- same reasoning as above

AIC Sniff Control (AICSNIFFnCNTRL)

AIC Sniff Interrupt Status(AICSNIFFnINT_STAT) PA should own it --- same reasoning as above

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AIC Interrupt Mux Control Register(AIC_INTERRUPT_MUX_CTRL_REG)

This register controls the muxing of the various interrupts from thedifferent sub-blocks inside the AIC and also controls the gating of thevarious interrupts Ownership is more relevant to DSP for the various fields in this register

RF Timer Interrupt Control Register (RFTIMER_INTR_CTRL_REG)



RF Timer Block. RF Timer Interrupt Status Register (RFTIMER_ISR)

Both PA and DSP should own this register

PPC Interrupt Control Register (PPC_INTERRUPT_CNTL_REG)

PA should obviously own this register as it controls the gating of variousinterrupts to the PPC

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PPC Interrupt Status Register (PPC_INTERRUPT_STATUS_REG) PA should own it

AIC DSP LTE Interrupt Control Register

(DSP_LTE_INTERRUPT_CTRL_REG) DSP to own the above register which is used to control the muxing of

LTE interrupts to DSP




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14_AIC Interrupt- Register Ownership