1377 file wrapper

PART B- FEE(S) TRANSMITTAL

form, together .applicable fee(s), to: Mail Mail Stop Iss&E ·~ C"' Commissioner for Patents ,. / (CL __ 6--.) P.O. Box 1450

3 'n\US 1.1:' 0 r- 0 Alexandria, Virginia 22313-1450 !:' or EilX (703) 746-4000

should be used for transmitting the ISSUE FEE and PUBLICATION FEE (if required). Blocks I through 5 should be completed wh appropn ' '/':, 1 furthe spondence including the Patent, advance orders and notification of maintenance fees will be mailed to the current lcorrespondence address indicated ~~ elow or directed otherwise in Block 1, by (a) specifying a new correspondence address; and/or (b) indicating a sep:trate "FEE ADDRESS" maintenance ee utiflcations.

24739 7590 OU04/2005

CENTRAL COAST PATENT AGENCY PO BOX 187 AROMAS, CA 95004

01/19/2005 KBETEKA2 00000017 10390194

01 FC:2501 02 FC:1504 700.00 OP

300.00

Note: A certificate of mailing can only be used for domestic mailings of Fee(s) TransmittaL This certificate cannot be used for any other accompany papers. Each additional paper, such as an assignment or formal drawing, m have its own certificate of mailing or transmissiOn.

Certificate of Mailing or Transmission I hereby certify that this Fee(s) Transmittal is being deposited with the Un States Postal Service with sufficient postage for first class mail in an envel addressed to the Mail Stop ISSUE FEE address above, or being facsim transmitted to the USPTO 703 746-4000, on the date indicated below.

(DepOiiito~s na

(Signat

(D

APPLICATION NO. FILING DATE FIRST NAMED INVENTOR CONFIRMATION NO.

10/390,194 03/1412003 Ajay Janami Daga Pl377

TITLE OF INVENTION: AUTOMATED APPROACH TO CONSTRATh.'T GENERATION IN IC DESIGN

:t APPLN. TYPE SMALL ENTITY ISSUE FEE

nonprovisional YES $700

EXAMINER ART UNIT

LIN, SUN J 2825

I. Chanl!.e of correspondence address or indication of "Fee Address" (3 7 CFR Lf63).

0 Change of corresJlondence address (or Change of Correspondence Address form PTO/SB/122) attached.

PUBLICATION FEE TOTAL FEE(S) DUE

$300

CLASS-SUBCLASS

716-001000

2. For printing on the patent front page, list (I) the names of up to 3 registered patent attorneys or agents OR, alternatively,

$1000

3209

DATE DUE

04/04/2005

,, " 0 "Fee Addres~" indication (or "Fee Address" Indication form

• PTO/SB/47; Rev 03-02 or more recent) attached. Use of a Customer

(2) the name of a single fum (having as a member a registered attorney or agent) and the names of up to 2 registered patent attorneys or agents. If no name is listed, no name will be printed. · - Number is required.

\ASSIGNEE NAME AND RESIDENCE DATA TO BE PRINTED ON THE PATENT (print or type)

PLEASE NOTE: Unless an assignee is identified below, no assignee data will appear on the patent. If an assignee is identified below, the doCument has been filed recordation as set forth in 37 CFR 3.1 L Completion of this form is NOT a substitute for filing an assignment.

(A) NAME OF ASSIGNEE (B) RESIDENCE: (CITY and STATE OR COUNTRY)

F/ shfa-,· I Des;1// AIL.f~maf;~/} Irt~. J_~05v..>e.jD) D {{..

~oration or other private group entity 0 Govemm Please check the appropriate assignee category or categories (will not be printed on the patent) : 0 Individual

4a The following fee(s) are enclosed: 4b. Payment ofFee(s):

~ue Fee 13-A: checiZ in the amount of the fee( s) is enclosed.

~ication Fee (No small entity discount permitted) 0 Payment by credit card. Form PT0-2038 is attached.

0 Advance Order- # of Copies ld-rhe' Director is hereby authorized b c Deposit Account Number ,

e the required fee(s), or credit any ovell'ayment (enclose an extra copy of this form).

5. Change in Entity Status (from status indicated above)

0 a. Applicant claims SMALL ENTITY status. See 37 CFR 1.27. 0 b. Applicant is no longer claiming SMALL ENTITY status. See 37 CFR L27(g)(2).

The Director of the USPTO is requested to apply the Issue Fee and Publication Fee (if any) or to re-apply any previously paid issue fee to the application identified above. NOTE: The Issue Fee and Publication Fee (if required) will not be accepted from anyone other than the applicant; a regtstered attorney or agent; or the assignee or other part interest as shown by the records of the ·ted States ent and rademark Office.

Typed or printed name __Jbo.a.a~rJL..!..!!t>-=...l...!od~_._R~-_"?:2~~0~'1q....5.L_ ___ _ This collection of information is required by 3 7 CFR 1.311. The information is required to obtain or retain a benefit by the public which is to file (and by the USPTO to proc an appl\cation. Confidentiality_is governed by 35 U.S.C. 122_and 3? CFR 1.14. TIJ,is collection \s e~t\mated to take 1~ minutes to complete, includi_ng gathering,_preparmg, submitting the completed applicatiOn form to the USPTO. Time Will vary depending upon the mdivJdual case. Any co=ents on the amount of time you reg_urre to comp this form and/or suggestions for reducing this burden, should be sent to the Chief Information Officer, U.S. Patent and Trademark Office, U.S. Department of Co=erce, 1> Box 1450, Alexandria, Virginia 22313-1'150. DO NOT SEND FEES OR COMPLETED FORMS TO THIS ADDRESS. SEND TO: Commissioner for Patents, P.O. Box 14 Alexandria, Virginia 22313-1450. Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it displays a valid OMB control number.

PTOL 85 (Rev 12/04) Approved for use through 04/30/2007 OMB 0651 0033 US Patent and Trademark Office; US DEPARTMENT OF COMMER

Certificate of Express Mailing

"Express Mail" Mailing Label Number: EV584080300US Date of Deposit: 01/13/2005 Ref: Case Docket No.: P1377 Application of: Ajay Janami Daga Serial Number: 10/390,194 Filing Date: 03/14/2003 Title of Case: Automated Approach to Constraint Generation in IC Design

I hereby certify that the attached papers are being deposited with the United States Postal Service "Express Mail Post Office to Addressee" service under 37 C.F.R. 1.10 on the date indicated above and addressed to the Commissioner for Patents, Alexandria, VA 22313-1450.

1. Part B of issue fee transmittal. 2. Check for fees in the amount of$1000.00 ($700/Issue fee and $300/Pub. fee).

C., 3. Certificate of express mailing. 4. Postcard listing contents.

Mark A. Boys

UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Offi(e Address: COMMISSIONER FOR PATENTS

P.O. Box 1450 Alexandria. Virginia 22313-1450 www.usptn.go\'

NOTICE OF ALLOWANCE AND FEE(S) DUE

24739 7590 Ol/0412005


EXAMINER

LIN,SUNJ

ART UNIT PAPER NUMBER

2825

DATE MAILED: 0 1/04/2005

APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.

10/390,194 03/14/2003 Ajay Janami Daga Pl377 3209

TITLE OF INVENTION: AUTOMATED APPROACH TO CONSTRAINT GENERATION IN IC DESIGN

APPLN. TYPE SMALL ENTITY ISSUE FEE PUBLICATION FEE TOTAL FEE(S) DUE DATE DUE

nonprovisional YES $700 $300 $1000 04/04/2005

THE APPLICATION IDENTIFIED ABOVE HAS BEEN EXAMINED AND IS ALLOWED FOR ISSUANCE AS A PATEN PROSECUTION .QN IHE MERITS IS CLOSED. TIDS NOTICE OF ALLOWANCE IS NOT A GRANT OF PATENT RIGHT TIDS APPLICATION IS SUBJECT TO WITHDRAWAL FROM ISSUE AT THE INITIATIVE OF THE OFFICE OR UPO PETITION BY THE APPLICANT. SEE 37 CFR 1.313 AND MPEP 1308.

THE ISSUE FEE AND PUBLICATION FEE (IF REQUIRED) MUST BE PAID WITIDN THREE MONTHS FROM TH MAILING DATE OF TIDS NOTICE OR TIDS APPLICATION SHALL BE REGARDED AS ABANDONED. .IH._ STATUTORY PERIOD CANNOT BE EXTENDED. SEE 35 U.S.C. 151. THE ISSUE FEE DUE INDICATED ABOV REFLECTS A CREDIT FOR ANY PREVIOUSLY PAID ISSUE FEE APPLIED IN TIDS APPLICATION. THE PTOL-85B (0 AN EQUIVALENT) MUST BE RETURNED WITIDN TIDS PERIOD EVEN IF NO FEE IS DUE OR THE APPLICATION WIL BE REGARDED AS ABANDONED.

HOW TO REPLY TO TIDS NOTICE:

I. Review the SMALL ENTITY status shown above.

If the SMALL ENTITY is shown as YES, verify your current SMALL ENTITY status:

A. If the status is the same, pay the TOTAL FEE(S) DUE shown above.

B. If the status above is to be removed, check box 5b on Part B -Fee(s) Transmittal and pay the PUBLICATION FEE (if required} and twice the amount of the ISSUE FEE shown above, or

If the SMALL ENTITY is shown as NO:

A. Pay TOTAL FEE(S) DUE shown above, or

B. If applicant claimed SMALL ENTITY status before, or is n claiming SMALL ENTITY status, check box 5a on Part B- Fee Transmittal and pay the PUBLICATION FEE (if required) and I the ISSUE FEE shown above.

II. PART B- FEE(S) TRANSMITTAL should be completed and returned to the United States Patent and Trademark Office (USPTO) w your ISSUE FEE and PUBLICATION FEE (if required). Even if the fee(s) have already been paid, Part B - Fee(s) Transmittal should completed and returned. If you are charging the fee(s) to your deposit account, section "4b" of Part B - Fee(s) Transmittal should completed and an extra copy of the form should be submitted.

III. All communications regarding this application must give the application number. Please direct all communications prior to issuance Mail Stop ISSUE FEE unless advised to the contrary.

IMPORTANT REMINDER: Utility patents issuing on applications filed on or after Dec. 12, 1980 may require payment maintenance fees. It is patentee's responsibility to ensure timely payment of maintenance fees when due.

Page 1 of 3

PTOL 85 (Rev 12/04) Approved for use through 04/30/2007

PART B- FEE(S) TRANSMITTAL

Complete and send this form, together with applicable fee(s), to: Mail Mail Stop ISSUE FEE Commissioner for Patents P.O. Box 1450 Alexandria, Virginia 22313-1450

or fix (703) 746-4000 INSTRUCTIONS: This form should be used for transmitting the ISSUE FEE and PUBLICATION FEE (if required). Blocks I through 5 should be completed wh !IJlpropriate. All further corresponden~ including tb,e P!Uent. advance orders ll!ld. notification of maintenance fees will be maile_d (? tb,e current co~ondence addre~.s mdicated unless corrected below or directed otherwiSe m Block I, by (a) spec1fying a new correspondence address; and/or (b) mdicatmg a separate "FEE ADDRESS maintenance fee notifications.

l

CURRENT COAAESPONDENCE 1\DDRESS (Note: Use Block I for any ehange of ad~ .. )

24739 7590 OU0412005


APPLICATION NO. I FILING DATE I

Note: A certificate of mailing can only be used for domestic mailings of Fee(s) Transmittal. This certificate cannot be used for any other accompany papers. Each additional paper, such as an assignment or formal drawing, m have its own certificate of mailing or transmission.

Certificate of Mailing or Transmission I hereby certify that this Fee(s) Transmittal is being deposited with the Un States Postal Service with sufficient postage for firSt clilss mail in an envei addressed to the Mail S~ ISSUE FEn address above, or be~ facsim transmitted to the USPTO 03) 746-4000, on the date indicated OW.

(Dep06ito~• na

(Signal

CD

FIRST NAMED INVENTOR I ATTORNEY DOCKET NO. I CONFIRMATION NO.

10/390,194 03114/2003 Ajay Janami Daga PJ377 3209

TITLE OF INVENTION: AUTOMATED APPROACH TO CONSTRAINT GENERATION IN IC DESIGN

APPLN.TYPE SMALL ENTITY ISSUE FEE

nonprovisional YES $700

EXAMINER ART UNIT

LIN, SUN 1 2825

I. Change of correspondence address or indication of "Fee Address" (37 CFR I.363).

PUBLICATION FEE TOTAL FEE(S) DUE

$300

CLASS-SUBCLASS

7I6-00IOOO

2. For printing on the patent front page, list

(I) the names of up to 3 registered patent attorneys or agents OR, alternatively,

$1000

DATE DUE

04/04/2005

0 Change of correspondence address (or Change of Correspondence Address form PTO/SB/I22) attached.

0 "Fee Address" indication (or "Fee Address" Indication form PTO/SB/4 7; Rev 03-02 or more recent) attached. Use of a Customer Number is required.

(2) the name of a single firm (having as a member a 2. ____________ _ registered attorney or agent) and the names of up to 2 registered patent attorneys or agents. If no name is 3 listeQ, no name will be printed. -------------

3. ASSIGNEE NAME AND RESIDENCE DATA TO BE PRINTED ON THE PATENT (print or type)

PLEASE NOTE: Unless an assignee is identified below, no assignee data will appear on the patent. If an assignee is identified below, the document has been filed recordation as set forth in 37 CFR 3.11. Completion of this form is NOT a substitute for filing an assignment.

(A) NAME OF ASSIGNEE (B) RESIDENCE: (CITY and STATE OR COUNTRY)

Please check the appropriate assignee category or categories (will not be printed on the patent) : 0 Individual 0 Corporation or other private group entity 0 Governm

4a The following fee(s) are enclosed: 4b. Payment ofFee(s):

0 Issue Fee 0 A check in the amount of the fee(s) is enclosed.

0 Publication Fee (No small entity discount permitted) 0 Payment by credit card. Form PT0-2038 is attached.

0 Advance Order- #of Copies 0 The Director is hereby authorized by charge the required fee(s), or credit any ovel'J?ayment Deposit Account Number (enclose an extra copy of this form).

5. Change in Entity Status (from status indicated above)

0 a. Applicant claims SMALL ENTITY status. See 37 CFR 1.27. 0 b. Applicant is no longer claiming SMALL ENTITY status. See 37 CFR 1.27(g)(2).

The Director of the USPTO is requested to apply the Issue Fee and Publication Fee (if any) or to re-apply any previously paid issue fee to the application identified above. NOTE: The Issue Fee and Publication Fee (if required) will not be accepted from anyone other than the apphcant; a regrstered attorney or agent; or the assignee or other part interest as shown by the records of the United States Patent and Trademark Office.

Authorized Signature----------------------Date ________________ _

Typed or printed name--------------------- Registration No.--------------

This collection of information is required by 3 7 CFR I.3II. The information is required to obtain or retain a benefit by the public which is to file (and by the USPTO to l'roc an application. Confidentiality is governed by 35 U.S.C. I22 and 37 CFR 1.14. This collection is estimated to take 12 minutes to complete, including gathering, preparmg, submrtting the completed applicatiOn form to the USPTO. Time will vary depending upon the individual case. Any co=ents on the amount of time you require to comp this form and/or suggestions for reducing this burden, should be sent to the Chief Information Officer, U.S. Patent and Trademark Office, U.S. Department ofCo=erce, 1> Box I450, Alexandria, Virginia 22313-1450. DO NOT SEND FEES OR COMPLETED FORMS TO THIS ADDRESS. SEND TO: Commissioner for Patents, P.O. Box 14 Alexandria, Virginia 223I3-1450.

Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it displays a valid OMB control number.

PTOL 85 (Rev I2/04) Approved for use through 04/30/2007 OMB 065I 0033 US Patent and Trademark Office; US DEPARTMENT OF COMMER

UNITED STATES PATENT AND TRADEMARK OFFICE

APPLICATION NO. FILING DATE

10/390,194 03/14noo3

24739 7590 01/04/2005


FIRST NAMED INVENTOR

A jay Janami Daga

UNITED STATES DEPARTME.NT OF COMMERCE United States Patent and Trademark. Office Add=<: COMMISSIONER FOR PATENTS

P.O. Box 1450 1\leundria, Vuginia 22313-1450 www.usptt>.gov

ATTORNEY DOCKET NO. CONFIRMATION NO.

P1377 3209

EXAMINER

LIN,SUNJ


2825

DATE MAILED: 01/04/2005

Determination of Patent Term Adjustment under 35 U.S.C. 154 (b) (application filed on or after May 29, 2000)

The Patent Term Adjustment to date is 102 day(s). If the issue fee is paid on the date that is three months after t mailing date of this notice and the patent issues on the Tuesday before the date that is 28 weeks (six and a h months) after the mailing date of this notice, the Patent Term Adjustment will be 102 day(s).

If a Continued Prosecution Application (CPA) was filed in the above-identified application, the filing date th determines Patent Term Adjustment is the filing date ofthe most recent CPA.

Applicant will be able to obtain more detailed information by accessing the Patent Application Information Retriev (PAIR) WEB site (http://pair.uspto.gov).

Any questions regarding the Patent Term Extension or Adjustment determination should be directed to the Office Patent Legal Administration at (571) 272-7702. Questions relating to issue and publication fee payments should directed to the Customer Service Center ofthe Office ?! P~t~nt P_ubli_c~ti~n_ at (703) 30~-~283. _ _ __

Page 3 of 3

PTOL 85 (Rev 12/04) Approved for use through 04/30/2007

Application No. Applicant(s)

Notice of Allowability 10/390,194 DAGA, AJAY JANAMI Examiner Art Unit

Sun J Un 2825

-- The MAILING DATE of this communication appears on the cover sheet with the correspondence address-All daims being allowable, PROSECUTION ON THE MERITS IS (OR REMAINS) CLOSED in this application. If not included herewith (or previously mailed), a Notice of Allowance (PTOL-85) or other appropriate communication will be mailed in due course. THIS NOTICE OF ALLOWABILITY IS NOT A GRANT OF PATENT RIGHTS. This application is subject to withdrawal from issue at the initiative of the Office or upon petition by the applicant. See 37 CFR 1.313 and MPEP 1308.

1. [gl This communication is responsive to Amendment & Remarks filed on 1111712004.

2. [gl The ·allowed claim(s) is/are 1.3-13 and 15-24. renumbered (37CFR 1.126!.

3. [gJ The drawings filed on 03/1412003 are accepted by the Examiner.

4. D Acknowledgment is made of a claim for foreign priority under 35 U.S. C.§ 119(a)-(d) or (f).

a) D All b) D Some* c) D None of the:

1. D Certified copies of the priority documents have been received.

2. D Certified copies of the priority documents have been received in Application No. __ .

3. D Copies of the certified copies of the priority documents have been received in this national stage application from the

International Bureau (PCT Rule 17.2(a)).

*Certified copies not received: __ .

Applicant has THREE MONTHS FROM THE "MAILING DATE" of this communication to file a reply complying with the requirements noted below. Failure to timely comply will result in ABANDONMENT of this application. THIS THREE-MONTH PERIOD IS NOT EXTENDABLE.

5. 0 A SUBSTITUTE OATH OR DECLARATION must be submitted. Note the attached EXAMINER'S AMENDMENT or NOTICE OF INFORMAL PATENT APPLICATION (PT0-152) which gives reason(s) why the oath or declaration is deficient.

6. D CORRECTED DRAWINGS ( as "replacement sheets") must be submitted.

(a) D including changes required by the Notice of Draftsperson's Patent Drawing Review ( PT0-948) attached

1) D hereto or 2) D to Paper No./Mail Date __ .

(b) D including changes required by the attached Examiner's Amendment I Comment or in the Office action of Paper No./Mail Date __ .

Identifying indicia such as the application number (see 37 CFR 1.84(c)) should be written on the drawings in the front (not the back) of -~AcJ!.sJ!e.!!:_~~lac..!!!!._ent sheet{&) should be labeled as such in the header according to 37 CFR 1.121(d). · - ----------~--- --...- - ---- - -----~ ........ ----------- ---- -- ---~--

7. 0 DEPOSIT OF and/or INFORMATION about the deposit of BIOLOGICAL MATERIAL must be submitted. Note the attached Examiner's comment regarding REQUIREMENT FOR THE DEPOSIT OF BIOLOGICAL MATERIAL.

Attachment( s) 1. D Notice of References Cited (PT0-892)

2. D Notice of Draftperson's Patent Drawing Review (PT0-948)

3. D Information Disclosure Statements (PT0-1449 or PTO/SB/08), Paper No./Mail Date __

4. D Examiner's Comment Regarding Requirement for Deposit

of Biological Material

5. D Notice of Informal Patent Application (PT0-152)

6. D Interview Summary (PT0-413), Paper No./Mail Date __ .

7. D Examiner's AmendmenVComment

8. D Examiner's Statement of Reasons for Allowance

9. D Other

U.S. Patent ard Trademar1< Office

PTOL-37 (Rev. 1-04) Notice of Allowability Part of Paper No./Mail Date 1221200

iii r::: u:

1

Application No.

Issue Classification 10/390,194

II II II I Ill II~ Ill Examiner

Sun J Lin

in the same order as b~

~ 1

1

1

11 Ti II·] Hlllll iii 01 I :::, c (§ 1::::::. u:

Applicant(s)

DAGA, AJAY JANAMI Art Unit

2825

I DCPA ~~T\ .!: :§1 u. ....

0

D R1.47

iii c u:

a 9 1// 1 39 69 : 99 129 ·• · ··· 159 r : 189

l-...:...111~...:..::...._12_r:::::::::::I--+-....:..=.._42F::::::::::I--+-...:....=....72LL'::'''::'''::''::':I--+-1.:...::10.=2 ..... r;. ::::::: 132 162l H 132 _12 13_ 43 73 j H 103 • 133 163~ I 1

~! ~~ ~==:=:= ......... 1-----f-~i-'--l: :--+--=--=-~;E.=......t==•.==.... ~E ~E1 '~==:~~~~ 1s 11 47 n 1 < 101 137 167 _1 rr 16 18 48 78 I H 1 o8 1381 .. 168 ~ 17 19 49 79 I H 109 ,,,. · 139 IT 169 199

7•

27 I HI 57 : I

1

U.S. Patent and Trademark Office Part of Paper No. 12212004

Index of Claims Application No. Applicant(s)

IIIIIIIIIIIIIIIW II 2825

DAGA, AJAY JANAMI 10/390,194 Examiner Art Unit

Sun J Lin

_ (Through numeral) Cancelled

..J Rejected N Non-Elected A Appeal

= Allowed + Restricted I Interference 0 Objected

Claim Date Claim Date Claim Date

"iii ~ "iii "iii "iii c: "iii c: "iii c: c: 'ii> c;:; c: 'ii> c: 'ii> u: ·c: i'l u: ·c: u: (5 0 0

1 = 51 101 2 - 52 102 3 = 53 103 4 = 54 104 5 = 55 105 6 = 56 106 7 = 57 107 8 = 58 108 9 = 59 109 10 = 60 110 11 = 61 111 12 = 62 II 112 13 = 63 Ll 113 14 - 64 I I 114 15 =

11 1 1~ 65 115

16 = 66 116 17 = 67 117 18 = 68 118 19 = 1:::1 69 II 119 20 = II 70 IHI 120 21 = II 71 121 22 = JU 72 122 23 = Ll 73 123 24 = 74 124 25 75 125 26 76 II 126 27 77 127 28 II 78 128 29 II 79 129

· · -3o·· •·. -. ~ .. .. - .. . .. -~80. - .

130 31 81 131 32 82 132 33 83 133 34 84 134 35 85 135 36 86 136 37 87 137 38 88 138 39 89 139 40 90 140 41 91 141 42 92 142 43 93 143 44 94 144 45 95

11111:~ 145

46 HI 96 146 47 IHI 97 147 48

*J 98 148

49 99 Ll 149 50 100 IH 150


·search Notes Application No. Applicant(s)

1111111111111 Ill II II 10/390,194 DAGA, AJAY JANAMI Examiner Art Unit

Sun J Lin 2825

SEARCHED SEARCH NOTES

(INCLUDING SEARCH STRATEGY)

Class Subclass Date Examiner DATE EXMR

716 1 12/21/2004 JSL EAST [USPAT;US- 12/21/2004 JSL PGPUB;UPO;JPO;DERWENT;IBM_ T DB]

716 6 12/21/2004 JSL

IEEE 12/21/2004 JSL

'

GOOGLE 12/21/2004 JSL

I

-- ....._.. _____ -

INTERFERENCE SEARCHED

Class Subclass Date Examiner

716 1 12/21/2004 JSL

716 6 12/21/2004 JSL


.:..

Application or Docket Number

PATENT APPUCATION FEE DETERMINATION RECORD. p 131/ · Effective January 1 , 2003

CLAIMS AS FILED - PART I

TOTAL CLAIMS

FOR

TOTAL CHARGEABLE ClAIMS

MULTIPLE DEPENDENT CLAIM PRESENT ·o * If the difference in column 1 is less than zero, enter ·od in column 2

CLAIMS AS AMENDED • PART II

12/02)

PRESENT EXTRA

PRESENT. EXTRA

PRESENT ·EXTRA

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X$9=

X42=

+140=

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.X42=

+140=

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ADD I· RATE TIONAL

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X$-9=

X42=

+140=

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ADDI· RATE TIONAL

FEE

X$9=

X42=

+140=

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OTHER THAN OR SMALL ENTilY

0

OR X$18=

OR X84=

OR +280;;

OR TOTAL

OTHER THAN OR SMALL ENTITY

RATE

OR X$18=

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£PDF] Focus: The Automatic Generation of Golden Timing Constraints Fih:.: Format: PDF/Adobe Acrobat- View as HTML ... ·collectively referred to as exceptions to single-cycle clocking .•.• Figure 4: Golden timing constraint file for example design •.. W\1\'W.saros.co.uk/focus/whitepaper.pdf- $.i.m\!~LP~9~§.

[PDFJ Designing the Low-Power M ·CORE Architecture File Fonnat PDF/Adobe Acrobat- View as HTML ... Architecture (ISA), the custom datapath design, and the clocking. methodology . ... single cycle find-first-one instruction (FF1), a hardware loop ..• www.ece.umd.edu/courses/enee759m.S2000i papers/scott1998-lowpower.pdf- .$l.mH~L!~~.9~.§.

[PDFJ XAPP640 "Timing Constraints for Virtex-11 Pro Designs" v1.1 (01/03) File Format: PDF/Adobe Acrobat- View as HTML ... processor is in single-cycle mode. Multi-cycle mode occurs when the ..• timing constraint used is the PERIOD constraint, the clocks are related back to .•. direct.xilinx.com/bvdocs/appnotes/xapp640.pdf- Si;ni!ar pages

TechXclusives- Timing Closure- 6.1 i ... Exception: Spartan-3. Can reduce multiplexer delays Omprove •.. synchronous elements driven by a single clock ... Based on these two facts, multi-cycle constraints can ... direct.xilinx.com/xlnx/xweb/xil_tx_display. jsp?sTechX_ID=r.v_tim_closure_61i&iLanguageiD=1 - 69k-

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FPGA FAQ comp.arch.fpga archives- messages from 73725 ... a slow clock and it would be best if I could put a timing constraint on the fast signals .... If you have a DCM available just for clocking in the data, ... W'<.vw.fpga-faq.corn/archives/73725.htrn! - 61 k- Cached - Sirnilar oaaes

FPGA FAQ comp.arch.fpga archives- messages from 52075 ... Timing constraint: TS_clk2x_int = PERIOD TIMEGRP "clk2x_int" ts_clk_in I> 2.000000 ... sounds like the result of over-clocking a > systolic processor! .•• www.fpga-faq.com/archives/52075.html - 75k - G~.!.<.tl~Q - .S.i.r.nU5;1LP.~.9.~-~ __ ~- __________ _

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Synopsys Design Compiler - Whitepaper ... By default, Design Compiler calculates single cycle timing for .•. allows designers to define multi-cycle paths, false .•. point-to-point timing exception commands are ... WW'N.synopsys.corn/products/!ogic/dc_wp97.htrnl- 39k- Cached- Simi!ar pages

[PDFJ Designing the Low-Power M • CORE Architecture Filt:.: Format: PDF/Adobe Acrobat -View as HTML ... shift (ASR), and rotate operations (ROTL), a single cycle find-first ••. to select either register file for exception processing with no cycle penalty [20 ..• davinci .sn u .a c. kr/courses/emb/2000/doc/34 .pdf - §i.mH~r..p~g~_;?

[PDFJ Microcontrollers File Fonnat PDF/Adobe Acrobat- View as HTML ... normal CPU operation provided that it can be completed in a single cycle .••• The BDM serial interface uses a clocking scheme in which the external host ••• vV\.V\"'.freescale.cornlfiles/microcontrollers/ doc/ref_rnanuaVS12BDMV4.pdf- .$.!m.i.!~.L~~-9-~§

[PDFJ Microcontrollers

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1 Fast and practical false-path elimination method for large SoC designs Chul Rim; Soo-Hyun Kim; Joo-Hyun Park; Myung-Soo lang; Jin-Yong Lee; KyuMyong Choi; Jeong-Taek Kong; SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip] , 17-20 Sept. 2003 Pages: 397 - 400

[Abstract] [PDF Full-Text (355 KB)] IEEE CNF

2 A protocol for timed atomic commitment Davidson, 5.; Lee, I.; Wolfe, V.; Distributed Computing Systems, 1989., 9th International Conference on , 5-9 June 1989

[Abstract] [PDF Full-Text (664 KB)] IEEE CNF

3 A 4-GHz effective sample rate integrated test core for analog and mixedsignal circuits Hafed, M.M.; Abaskharoun, N.; Roberts, G. W.; Solid-State Circuits, IEEE Journal of, Volume: 37 , Issue: 4 , April 2002 Pages:499- 514

[Abstract] [PDF Fu II-Text (714 KB)] IEEE JNL

4 Asynchronous processor survey Werner, T.; Akella, V.; Computer, Volume: 30 , Issue: 11 , Nov. 1997 Pages:67- 76

[Abstract] [PDF Full-Text (352 KB)] IEEE JNL

I .2-21-ot/.

s A picosecond-accuracy, 700-MHz range, Si bipolar time interval counter LSI

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0 (timing adj constraint) and (synthesiz$) and ((single adj cycle) adj clock$)

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PAGE 01

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NOV 1 7 2004 1377

PTOISB/97 (12-n\ Appi'UWI!d far ll5a lhrougll 11130100. OMB 0861o003t

Pablnt and Tmdel!'lalf< Offlca: U.s. DEPAR'I"MEHT 01'" COMMERCE ID a ~on of nfannaiiGn un~eaa H carlalna • var OMB cordJDI numbllr.

In re: Ajay Janaml Daga Caee; P1377 Appllcatloi1No.; 10/390.194 Filing date: 03/14/2003 Att Unit 2825 Elcaminer. Sun J. lin Subject

An Automated Approach to Constraint Generation In IC Design

Certificate of Transmission under 37 CFR 1.8

Attention: Sun J. Lin , Examiner

Fax No.: (703) 872-9306

I hereby certify that. this correspondence is being facsimile transmitted to the Patent and Trademark Office

on 11/17/2004 Date

Sheri Beasley Typed or j:)rtnted name of person signing Certificate

Note: Each paper must have Its awn certificate of transmission, or this csrtifieate must IdentitY each submitl:sd paper.

Total Sheets Transmitted - 10

1. Amendment Transmittal - 1 sheet 2. Duplicate Amendment Transmittal- 1 sheet 3. Response A - 7 sheets 4. Certificate of Transmission - 1 sheet

Please call (831) 726-1457 if you have any questions.

Burden Hour Statement: Thl& farm Is .... ~m..t~Jd ID lake 0.03 hauns to a.~m!J(ate, Time will 1181}' _d'*cndlng 1111011 llle Reed& of lh" Individual CBBB. A.rry CQtnmaniB on the amount a1 time ralllllred to comJIIo!la tl'lls fOnn allould ba aant lo Ole Cl1iaf lnformallon Olllcet, Patent and Trademark Office, Washington. DC 20231. DO NOT SEND FEES OR COMPLETED fOF!MS TO THIS ADDRESS. SEND TO; Asalatanl Commlaaiii~W~r for Patenla, WllahlngiDII, DC 20231.

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11/17/2004 i5:29 8317263475 CCPA PAGE 02

Method ofTransm.ission: Facsimile CA.SE DOCKET NO. P1377

In q:ference to application of Ajay Janami Daga

Serial No. 10/390,194

For AD Automated Approach to Constraint Generation in IC Design

Sir. Transmitted herewith is and an amendment in the abovc-idattifiro application, under 37 C.F.R. 1.312.

Ill No additional fee is required. 121 Applicant claims Small entity status under 37 CFR 1.27. 0 The fee has been calculated as sbown below.

•••• CLAIMS AS AMENDED **** ~

(1) (2) (3) (4) (5) {6) (7)' (8)

Claims Remaining Highest No. Paid Present Rate Rate Additional After Amendment For PteViously Extra Small Large Fcc

Entitv Entitv

Total 22 Minus .... 24 0

Claims s 9 $ 18 $ 0.00

Jndep 2 Minus "'"'"' 3 0 $ 44 $ 88 s o.oo Claims

0 First presentation of a multiple dependent claim $ 0 $ 0 $ 0.00

0 Terminal Disclaimer Fees $ 0.00

Extension Fee I 0 lstMontb I 02ndMonth I 0 3rdMonth '$ 0.00

Total additional for claims, time e11:tensions and diselailXlcr kcs $ o.oo

"'* If the "highest Number Previously Paid For" in this space is tess than 20, write "20" in this space. **"'If the "highest Number PreviOQsly Paid For" in this space is less than 3, write "3~ in this sp~. """*"'Multiple dq>cmdoncies, if any, included in the above calculation. *If the entry in col.umn 2 is less than the ~ntry in column 4, write "0" in columnS.

0 A check in the amount of 0.00 is attached.

0Charge$ 0.00 to deposit account 50-0534 • (A duplicate of this sheet is enclosed)

~ Please charge any additional fees or credit overpayment to Deposit Account 50-0534 . A duplicate of this sheet is enclosed.

~ Respectfully Submitted, Donald R. Boys R.,g, No. 35074

Donald R.. :Boys Central Coast Patent Agency, Inc. P.O. Box 187 Aromas, CA 95004 (831) 726-1457

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11/17/2084 15:29 8317263475 CCPA PAGE 03

Method ofTransmission: Facsimile CASB OOCKl!T NO. P1377

In refc:nmce to application of Ajay Janami Daga

SerialNo. 10/390,194

For An Automated Approach to Constraint Generation in IC Design

Sir; Transmitted herewith i$ and an amendment in the above-identified appHcation, undet 37 C.F.R. l.3ll.

0 No additional fee is required. G2l Applicant claims SmaU entity status under 37 CFR l.:l7. 0 The fee has been calculated as shown below.

**** CLAJMS AS AMENDED •••• ~

(1) (2) (3)" (4) (S) (6) (7) (8)

Claims Rem$ining Highest No. Paid Present Rate Rate Additional After Amendment Pot Previously Extra Small L&.rp Fee

Entitv Entity

Total 22 Minus ** 24 0 $ 9 s 18 $ 0.00 Claims

.lndep 2 Minm; ••• 3 0 Claims

$ 44 $ 88 $ 0.00

D First presentation of a multiple dependent claim $ 0 $ 0 $ o:oo

0 Terminal Disclaimer Pees $ 0.00

Extension Fee I 0 lst Month I 02ndMonth I 03rdMonth $ 0.00

Total additional for claims, time extensions and disclaimer fees $ 0.00

•• If the "highest Number Previously Paid For" ln. this space is less than 20, write "20q in this spBA;;e. ••• If the "highest Number Previously Paid for" in this space is less than 3, write "3" in this space. •••• Multiple dependencies, if any, included in the above calculation. • If the: entry in colu.mn .2 is less than the entty in column 4, write "0'' in column 5.

0 A check ln the amount of 0.00 is attached.

0Charge$ 0.00 to deposit account 50-0534 . (A duplicate of this sheet is enclosed)

Ill Please charge any additional f~ or credit overpayment to Deposit AccolUlt 50-0534 . A duplicate of this sheet is enclosed.

£d/~f/Lr-Respectfully Submitted, DonAld R. Boys Reg. No. 35074

Donald R. Boys Central Coast Patent Agency, Inc.

COIP>Y P.O. Box 187 Aromas, CA 95004 (831) 726-1457

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IN mE UNITED STATES PATENT AND TRADEMARK OFFICE

lnRe: Case: Serial No.: Filed:

Art Unit 2825 ExiUlliner: Lin, Sun J.

Ajay Janami Daga P1377 10/390,194 03/14/2003

RECE~ CENTRAL F. ~ 04 CENTER

NOV 1 7 2004

Subject: An Automated Approach to Constraint Generation in IC Design

To: The Commissioner of Patents and Trademarks Alexandria, VA 22313-1450

Dear Sir;

Response A

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:(

. .. · '·

11/17/2884 15:29 8317263475 CCPA

0 ••• •

-2-

Claims 1-24 are presented below for examination. Claims 1, 3, 5, 12, 13, 15, 17

and 24 are ~ended, and claims 2 and I 4 are canceled in this response.

1. (currently amended) A software-based system for generating timing constraints

for a proposed IC desi!W, comprising:

a first input as a synthesizable description of.the proposed IC dWgn;

a second input as a clock specification for the proposed IC design; and

a processing unit accepting the first and second inputs, apd determining

therefrom as an output a set of timing constraints to guide implementation ·of the

proposed IC design;,

wherein the processing unit. in detennining the timing constraints.

determines exceptions to single-cycle clocking for the proposed IC design.

2. (canceled)

3. (currently amended) The system of claim ~ .Lwherein the exceptions include

false paths and multi-cycle paths.

· 4. t original) The system of cla1m 1 wherein the output is provided in Synopsys

Design Constraint (SOC) format useable by one or more of virtual prototyping,

logic synthesis, place & route, and static timing tools in design implementation .

5. (currently amended) The system of claim 1 wherein the oroposed IC design is

one of an application-specific integrated circuit (A~IC) or a field-programmable

gate array (FPGA).

6. (original) The system of claim 1 wherein the first and second inputs and output

PAGE 85

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-3-

timing constraints are for an individual functional block on an IC instead of for

the entire IC.

7. (original) The system of claim 1 wherein the flrst and second inputs and output

timing constraints are for paths between functional blocks on an IC.

8. (original) The system of claim 7 wherein results are used to partition overall IC

timing requirements into block timing budgets.

9. (original) The system of claim 1 wherein the synthesizable description is

provided as one of Verilog or VHDL format. .

10. (original) The system of claim 1 wherein the first input is derived from a .lib

model, and converted into one ofVerilog or VHDL format.

11. (original) The system of claim 10 wherein a facility is provided for a user to

manually refine an automatically-generated model by adding functional detail.

12. (currently amended) The system of claim 1 wherein, as part of the clock

specification users define the clocks, their periods, their phase shifts relative to a

reference clock, and the nets on the proposed IC design to which a clock is

applied.

13. (currently amended) A method for guiding an implementation phase for a

proposed IC design, comprising the steps of:

(a) providing to a processing unit as a first input a synthesizable

description ofthe proposed IC design;

PAGE 06

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11/17/2004 15:29 8317263475 CCPA

(b) providing as a second input to the processing unit clock specification

for the proposed IC design; and

(c) using the first and the second inputs by the processing unit to

determine therefrom, as an output, a set of timing constraints to guide

implementation of the proposed IC design. wherein, the processing unit in

determining the timing constraints. determines exceptions to single-cycle

clocking for the proposed IC design.

14. (canceled)

15. (currently amended) The method of claim M .11. wherein the exceptions

include false paths and multi-cycle paths.

16. (original) The method ofclaim 13 wherein th.e output is provided in Synopsys

Design Constraint (SDC) fonnat useable by one or more of virtual prototyping,

logic synthesis, place & route, and static timing tools in design implementation.

17. (currently amended) The method of claim 13 wherein the proposed IC design

is one of an application-specific integrated circuit (ASIC) or a field

programmable gate array (FPGA).

18. (original) The method of claim 13 wherein the first and second inputs and

output timing constraints are for an individual functional block on an IC instead

of for the entire IC.

19. (original) The method of claim 13 wherein the first and second inputs and

output timing constraints are for interaction paths between functional blocks on

PAGE 07

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aniC.

20. (original) The system of claim 19 wherein results are used to partition overall

IC timing requirements into block timing budgets.

21. (original) The method of claim 13 wherein the synthesizable description is

provided as one ofVerilog or VHDL format.

22. (original) The method of claim 13 wherein the first input is derived from a

.lib model, and converted into one ofVerilog or VHDL format

23. (original) The method of claim 22 wherein a facility is provided for a user to


24. (currently amended) The method of claim 13 wherein, as part of the clock

specification users define the clocks, their periods, their phase shifts relative to a

reference clock, and the nets on the proposed IC design to which a clock is

applied.

PAGE 08

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11/17/2004 15:29 8317263475 CCPA

• 6-

REMARKS

The present response is to the Office Action mailed in the above

referenced case on August 24, 2004. Claims 1-24 are presented for examination.

Claims 1, 5-9, 12, 13, 17-21 and 24 are rejected under 35 U.S.C. 102(b) as being

anticipated by Ginetti et al. (5,896,299), hereinafter Ginetti. Claims 4 and 16 are

rejected under 35 U.S.C. 103(a) as being unpatentable over Ginetti in view of

Landy et al. {6,658,628 Bl), hereinafter Landy. Claims 2, 3, 10, 11, 14, 15,22

and 23 are objected to as being dependent upon a rejected base claim, but are.

indicated by the Examiner as reciting allowable subject matter.

Applicant has carefully studied tbe prior art presented by the Examiner,

and the Examiner's rejections and statements in the instant Office Action.

In response to the merit rejections applicant amends independent claims 1

and 13 to recite the patentable limitations of claims 2 and 14 respectively. Claims

2 and 14 are accordingly canceled, and depending claims 3 and 15 are amended to

correct the dependencies. Responding to the Examiner's claim rejections due to

infonnalities, applicant amends the affected claims appropriately as suggested by

the Examiner.

Applicant's independent claims 1 and 13, as amended to include subject

matter indicated by the Examiner as allowable, are now patentable over the prior

art presented by the Examiner. Claims 3 and 15 have been amended to reflect

new dependencies. Depending claims 3~12 and 15-24 are now patentable on their

own merits in their original form, or as amended herein, or at least as depended

from a patentable claim.

It is therefore respectfully requested that this application be reconsidered,

the claims the allowed, and that this case be passed quickly to issue. Ifthere are

PAGE 09

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-7-

any time extensions needed beyond any extension specifically requested witJl this

amendment, such extension of time is hereby requested. If there are any fees due

beyond any fees paid with this amendment, authorization is given to deduct such fees

from deposit account 50-0534.

Donald R. Boys Central Coast Patent Agency P.O. Box 187 Aromas, CA 95004 (831) 72()..1457

by

Respectfully Submitted, Ajay Janami Daga

d.-.«6:!,~ • Donald R Boys

Reg. No. 35,074

PAGE 18

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UNITED STATES PATENT AND TRADEMARK OFFICE

APPLICATION NO. FILING DATE

10/390,194 03/14/2003

24739 7590 08/2412004


FIRST NAMED INVENTOR

Ajay Janami Daga

UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS

P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov

I ATTORNEY DOCKET NO. I CONFIRMATION NO.

P1377 3209

EXAMINER

LIN, SUN J


2825

DATE MAILED: 08/24/2004

Please find below and/or attached an Office communication concerning this application or proceeding.

PT0-90C (Rev. 10/03)

Application No.

10/390,194

Office Action Summary Examiner

Sun J Lin

Applicant(s)

DAGA, AJAY JANAMI

Art Unit

2825

-- The MAILING DATE of this communication appears on the cover sheet with the correspondence address --Period for Reply

A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE ;a MONTH(S) FROM THE MAILING DATE OF THIS COMMUNICATION. - Extensions oftime may be available under the provisions of 37 CFR 1.136(a). In no event, however, may a reply be timely filed

after SIX (6) MONTHS from the mailing date of this communication. - If the period for reply specified above is less than thirty (30) days, a reply within the statutory minimum of thirty (30) days will be considered timely. - If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication. - Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).

Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any earned patent term adjustment. See 37 CFR 1.704(b).

Status

1)1:8l Responsive to communication(s) filed on 14 March 2003.

2a)0 This action is FINAL. 2b)C8] This action is non-final.

3)0 Since this application is in condition for allowance except for fonnal matters, prosecution as to the merits is

closed in accordance with the practice under Ex parte Quayle, 1935 C.D. 11, 453 O.G. 213.

Disposition of Claims

4)1:8l Claim(s) 1-24 is/are pending in the application.

4a) Of the above claim(s) __ is/are withdrawn from consideration.

5)0 Claim(s) __ is/are allowed.

6)C8] Claim(s) 1,4-9.12.13.16-21 and 24 is/are rejected.

7)1:8l Claim(s) 2.3.10. 11.14.15.22 and 23 is/are objected to.

8)0 Claim(s) __ are subject to restriction and/or election requirement.

Application Papers

9)0 The specification is objected to by the Examiner.

1 O)C8] The drawing(s) filed on 14 March 2003 is/are: a)C8] accepted or b)O objected to by the Examiner.

Applicant m~y not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).

Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121 (d).

11 )0 The oath or declaration is objected to by the Examiner. Note the attached Office Action or fonn PT0-152.

Priority under 35 U.S.C. § 119

12)0 Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).

a)O All b)O Some* c)O None of:

1.0 Certified copies of the priority documents have been received.

2.0 Certified copies of the priority documents have been received in Application No. __ .

3.0 Copies of the certified copies of the priority documents have been received in this National Stage

application from the International Bureau (PCT Rule 17.2(a)).

* See the attached detailed Office action for a list of the certified copies not received.

Attachment(s)

1) C8J Notice of References Cited (PT0-892)

2) 0 Notice of Draftsperson's Patent Drawing Review (PT0-948)

3) 1:8Jinformation Disclosure Statement(s) (PT0-1449 or PTO/SB/08) Paper No(s)/Mail Date 03/14/03.

U.S. Patent and Trademarl< Off1ce

4) 0 Interview Summary (PT0-413) Paper No(s)/Mail Date. __ .

5) 0 Notice of Informal Patent Application (PT0-152) 6) 0 Other: __ .

PTOL-326 (Rev. 1-04) Office Action Summary Part of Paper No./Mall Date 08182004

Application/Control Number: 1 0/390,194

Art Unit: 2825

DETAILED ACTION

Page 2

1. This office action is in response to application 10/390,194 filed on 03/14/2003.

Claims 1 - 24 remain pending in the application.

Claim Objections

2. Claims listed below are objected to because of the following informalities:

Claim 1, line 3, after "IC" insert -design-.


Claim 5, line 1, change "IC" to -proposed IC design-.

Claim 12, line 3, in front of "design" insert -proposed I C-.



Claim 17, line 1, change "IC" to -proposed IC design-.

Claim 24, line 3, in front of "design" insert -proposed I C-.

Appropriate correction is required.

Claim Rejections - 35 USC§ 102(b)

3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. §102(b) that form the basis for the rejections under this section made in this Office action:

A person shall be entitled to a patent unless-

(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.

4. Claims 1, 5-9, 12, 13, 17-21 and 24 are rejected under 35 U.S.C. §1 02(b) as

being unpatentable over U.S. Patent No. 5,896,299 to Ginetti eta/.

5. As to Claim 1, Ginetti eta/. teach the following subject matter:

• Method and svstem containing a computer implemented process (i.e.,

software-based svstem) for fixing timing constraints for a hierarchical design

of electronic circuit- [title; abstract; col. 1, line 66- col. 2, line 5]; Notice that

appropriate timing constraints are generated through fixing existing timing

Application/Control Number: 10/390,194

Art Unit: 2825

Page 3

constraints- [abstract]; A hierarchv design of circuit- [Fig. 14]; Notice that in

a hierarchv design, an electronic circuit under study may be a function block

in one hierarchical/eve/ (e.g., Fig. 3A) or a group of functional blocks

arranged in manvhierarchica//eve/s (e.g., Fig. 14); A proposed IC design is

any hierarchv design (one hierarchical/eve/ or many hierarchical levels) of

electronic circuit under study.

• synthesizing a RTL-HDL tvpe description of the circuit (i.e., proposed /C) -

[abstract]; Notice that RTL-HDL is a synthesizable description (called first

input);

• real clock timing (latency and skew). worst case conditions. best case

conditions- [abstract]; Notice that the real clock timing (latency and skew).

worst case conditions. best case conditions are constituents of a clock

specification (called second input) of the proposed IC design under study;

• Computer implemented process accepting the synthesizable description (first

input) and the clock specification (second input), and determining therefrom

as an output a set of timing constraints (upper-bond timing constraints, lower

bound timing constraints)- [abstract]; Notice that the set of timing constraints

could be utilized in guiding timing implementation of the hierarchical circuit

design {proposed IC design)- [col. 2, line 31 - 47; col. 5, line 1 - 60].

For reference purposes, the explanations given above in response to Claim 1 are

called [Response A] hereinafter.

6. As to claim 13, reasons are included in [Response A] given above.

7. As to Claims 5 and 17, Ginetti eta/. disclose one of his related publication on

"Using the ASIC synthesizer in DSP Designs"- [Other Publications]. Notice that the

ASIC is a synthesizable IC.

8. As to Claims 6 and 18, the explanations included in [Response A] could be applied

to any hierarchy circuit design, including a functional block (e.g., flip-flops) in an IC

design. Ginetti eta/. show and teach timing constraints (CK1, CK2) of a circuit

containing flip-flops 11. 13, which is a functional block- [Fig. 3A].


Art Unit: 2825

Page4

9. As to Claims 7 and 19, in addition to reasons included in [Response A] given

above, Ginetti et a/. show and teach a circuit design 1 08 with two hierarchical parts

(subcells 110. 112), there are timing constraints for paths (data path, clock path)

between subce/1 110 and subce/1 112- [Fig. 14; col. 6, line 66- col. 7, line 27]. Notice

that subce/1 110 and subce/1 112 are functional blocks.

For reference purposes, the explanations given above in response to Claims 7

and 19 are called [Response B] hereinafter.

10. As to Claims 8 and 20, in addition to reasons included in [Response A] and

[Response B] given above, Ginetti eta/. teach subject matter on timing constrains in

hierarchical designs of electronic circuits- [abstract; col. 1, line 5-9]. Notice that

timing requirements is clock timing Oatencv and skew) specifications of hierarchical

parts- [abstract]. Block timing budgets are timing constraints of hierarchical parts. In a

hierarchical design, overall IC is partitioned in hierarchical manners.

11. As to Claims 9 and 21, as explained in [Response A] given above, Ginetti eta/.

teach that the svnthesizable description is provided as a HDL tvpe. Notice that a VHDL

format description is a HDL type description.

12. As to Claims 12 and 24, Ginetti eta/. teach that the clock description includes

clock period, (clock) waveform, skew and latency associated with each clock- [col. 5,

line 4- 6]. Notice that clock description is an input, therefore clock period, (clock)

waveform, skew and latencv are defined and inputted by users. Waveform, skew and

latencv of a clock define its phase shift relative to a reference clock. A clock is assigned

to each clock net. In designing a hierarchical electronic circuit, a user may need to

assign many clocks to different clock nets. Notice also that many users may have

different ideas in defining clocks, their periods, their phase shifts relative to a reference

clock to the clock nets in the proposed IC design.


Art Unit: 2825

Claim Rejections - 35 USC § 103

Page 5

13. The following is a quotation of 35 U.S.C. 1 03(a) which forms the basis for all obviousness rejections set forth in this Office action:

(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.

The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 1 03(a) are summarized as follows:

(1 ). Determining the scope and contents of the prior art. (2). Ascertaining the differences between the prior art and the claims at issue. (3). Resolving the level of ordinary skill in the pertinent art. (4 ). Considering objective evidence present in the application indicating obviousness

or nonobviousness.

14. Claims 4 and 16 are rejected under 35 U.S.C. 1 03(a) as being unpatentable over

U.S. Patent No. 5,896,299 to Ginetti eta/. in view of U.S. Patent No. 6,658,628 81 to

Landv eta/.

15 As to Claim 4, Ginetti eta/. teach all subject matter recited in Claim 1, they do not

teach a method of providing the output in Svnopsvs Design Constraint (SOC) format

usable by one or more of virtual prototyping, logic synthesis, place & route and static

timing tools in design implementation. But Landv eta/. teach generating appropriate

time budget (or timing constraints) in Synopsvs Design Constraint (SOC) format file,

which is generated in a format or syntax corresponding to a .sdc suffix, for a particular

design- [col. 4, line 34- 38]. Landy eta/. also show and teach the following subject

matter:

• Timing file generator for hardmacro (e.g., AS/C)- [Fig. 1];

• Providing hardmac technology file and/or timing generation tool that may provide

transportable language or syntax that can be read and/or processed by other

synthesis/layout/analysis tools- [col. 1, line 38- 54]; Notice that synthesis tool

includes logic synthesis tool, layout tool includes place & rout tool, analysis tool

includes static timing tool.


Art Unit: 2825

Page 6

Notice that the Synopsys Design Constraint (SOC) format file is a transportable

language or syntax. The timing constraints are generated in Synopsys Design

Constraint (SOC) format file in order to provide a capability of being read and/or

processed by logic synthesis, place & rout tool and static timing tools provided by other

vendors. Data generated in a transportable language or syntax is very helpful for a

design company utilizing a variety of logic synthesis, place & rout tool and/or static

timing tools, which are provided by different manufacturers.

Therefore, it would have been obvious at the time the invention was made to a

person having ordinary skill in the art to have applied the teachings of Landy eta/. in

generating timing constraints in Synopsys Design Constraint (SOC) format file in order

to provide a transportable capability of being read and/or processed by a variety of logic

synthesis, place & rout tool and static timing tools, which are provided by different

vendors.

For reference purposes, the explanations given above in response to Claim 4 are

called [Response C) hereinafter.

16. As to Claim 16, reasons are included in [Response C) given above.

Allowable Subject Matter

17. Claims 2, 3, 10, 11, 14, 15, 22 and 23 are objected to as being dependent upon a

rejected base claim, but they would be allowable if rewritten in independent form

including all of the limitations of the base claim and any intervening claims.

Those claims are allowed is because that the prior art does not teach or fairly

suggest the following subject matter:

• The processing unit, in determining the timing constraints, determines

exceptions to single-cycle clocking for the proposed IC design in combination

with other limitations as recited in Claim 2 and Claim 14, respectively;

• The first input is derived from a .lib model and converted into one of Veri log of

VHDL format in combination with other limitations as recited in Claim 10 and

Claim 22, respectively;

Application/Control Number: 1 0/390,194

Art Unit: 2825

Conclusion

Page 7

18. Any inquiry concerning this communication or earlier communications from the

examiner should be directed to Sun J. Lin whose telephone number is (571) 272-1899.

The examiner can normally be reached on Monday-Friday (9:00AM-6:00PM).

If attempts to reach the examiner by telephone are unsuccessful, the examiner's

supervisor, Matthew Smith can be reached on (571) 272-1907. The fax phone numbers

for the organization where this application or proceeding is assigned are (703) 872-9318

for regular communications and (703) 872-9319 for After Final communications.

Any inquiry of a general nature or relating to the status of this application or

proceeding should be directed to the receptionist whose telephone number is (703) 308-

1782.

Sun James Lin Art Unit 2825 August23,2004

'

..

+

• • PTO/SB/08A (10.01) +~

Approved for use through 10/3112002. OMB 0651.0031 g. = U.S. Patent and Trademark Offl~e: U.S. DEPARTMENT OF COMMERCE ood4 ~

Under the Paperwork Reduction Act of 1995, no persons are required to reapond to a collection of information unless It contslns a valid OMB • ~ ;:;;;;;;g . ""nlrnl numbAr

Substitute for form 1449A/PTO Complet if Known

INFORMATION DISCLOSURE Application Number NA Flllna Data 03/1412003

STATEMENT BY APPLICANT First Named Inventor Ajay Janami Daga Art Unit "i'+lr- "Z 11 'Z-5"'

(us& as many sh&ets as necessary) Examiner Name N*' I ~"' Sheet I 1 lot I 1 Attorney Docket Number P1377

U.S. PATENT DOCUMENTS

Examiner Cite tnltiats' No. 1 Number·IOndCodo'(lf-

Publication Date MM.OO..YYYY

_ ~ •. Ts;a •• -''"-~...«-- _U$:_60/365_,~_9 ___ ._--.N~A __

Nama of Patentee or Pages, Columns, Lines, Where Applicant of Cited Document Relevant Passages or Relevant

Flaures Aooear

Aiav Janam __ i_D_a..;.ltli" .. ·-.. -I---...;Prio=· o=ri!Y. Clai!Jl:;._ ____ 1 ------l·--·~~u=s-____________ 1 __________ 1 ____________________ r------------------·----·· ............. !:'~:... ...... --.. ·--···-···- ·--.. ·--------------·------··t------------"·------- __ us~-----.. ----·----- -·---·--·-- ·------·--·-·--.. ·-- _____ , ___ , ________ ... _____ _

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---- ---- ~-=---·-------- --------------------------·-------·--US-

FOREIGN PATENT DOC

Examiner Cite Publication Dale

Initials' No.1 -~Podol ~u!!'be~:IOnd~a'Jf.-) ..... ~M-[;)~YYYY

Name of Patentee or Pages, Columna. Unoo, Where Relevant PaNgea

Applicant of Cited Document or Relevant Flgurea Appear Te

------- -------------------------- --------- --·----------- -----------· ---·----------------c..... .. _, __ ............... -....................... ___________ !-----------·-·-

---- ·-- ----·------ ----·--- -------· ---.. ------··!---------------- -- ---· ·-----------........ ____ .. --·------------·---r--.. -------·--- --------------------- ·---------.. ---------.. ·-·--1---------1--

'EXAMINER: Initial If reference consider , whether or nol cltstion is In conformance with MPEP 609. Draw line through citation If not In conformance and not considered. Include copy of this form wllh next communication to applicant. 1 Applicant's unique citation designation number (optional). 2 See Kinds Codes of USPTO Patent Documents at www.uspto.gov or MPEP 901.04. 3 Enter Office thai Issued the documen~ by the two-letter code (WIPO Standard ST.3). 4 For Japanese patent documents, the indication of the year of the reign of the Emperor must precede the aerial number of the patent document. 5 Kind of document by the appropriate symbols as indicatad on the document under WIPO Standard ST. 16 If possible. 8 Applicant Is to place e chock marie here if English language Translation Is attached. Burden Hour Ststoment: This form Ia estimated to take 2.0 h011n1to complete. Time will vary depending upon the needs of the Individual case. Any commanb on the amount of time you are required to complete this form should ba sent to the Chief Information Officer, U.S. Patant and Trademark Ofllce, Washington, DC 20231. DO NOT SEND FEES OR COMPLETED FORMS TO THIS ADDRESS. SEND TO: Asalstsnt Commissioner fer Patents, Washington, DC 20231.

Ulc:::::a-...... ..:en=..,. -~= .... \D..__, C"'c:::::a~C"' o..-t =o .... I') --

Application/Control No. Applicant(sYPatent Under Reexamination

10/390,194 DAGA, AJAY JANAMI Notice of References Cited

Examiner Art Unit

Sun J Lin 2825 Page 1 of 1


* Document Number Date

Name Classification Country Code-N umber-Kind Code MM-YYYY

A US-5,896,299 04-1999 Ginetti et al. 716/4

B US-6,658,628 81 12-2003 Landy et al. 716/1

c US-

D US-

E US-

F US-

G US-

H US-

I US-

J US-

K US-

L US-

M US-

FOREIGN PATENT DOCUMENTS

* Document Number Date

Country Name Classification Country Code-Number-Kind Code MM-YYYY

N

0

p

Q

R

s

T

NON-PATENT DOCUMENTS

* Include as applicable: Author, Title Date, Publisher, Edition or Volume, Pertinent Pages)

u

v

w

X

. A copy of thts reference IS not being furntshed wtth thts Office action. (See MPEP § 707.05(a).) Dates in MM-YYYY format are publication dates. Classifications may be US or foreign.

U.S. Patent ard Trademarl< Office

PT0-892 (Rev. 01-2001) Notice of References Cited Part of Paper No. 08182004

UNITED STATES PATENT AND 1'RADEMARK OFFICE

*BIBDATASHEET* Bib Oat! Sheet

FILING DATE

SERIAL NUMBER 03/14/2003 CLASS 10/390,194 716

RULE

~PPLICANTS

Ajay Janami Daga, Lake Oswego, OR;

*CONTINUING DATA ••••••••••••••••••••••••• Y'o:s. ~-This appln claims benefit of 60/365,7 49 03/18/2002

* FOREIGN APPLICA 110NS •••••••••••••••••••• ~ !JlJ7V(r

IF REQUIRED, FOREIGN FILING LICENSE GRANTED •• SMALL ENTITY •• • 05/13/2003

Foreign Priority claimed 0 !!( yes no STATE OR

5 usc 119 (a·d) condttlons met ~ ~ IE)' D M 1 11 All yes ')." e a er ~

COUNTRY !verified and Acknowledged Ex!lnineilfl Signature lni Is OR

!ADDRESS ~4739 CENTRAL COAST PATENT AGENCY PO BOX 187 IAROMAS,CA 195004

!TITLE

~utomated approach to constraint generation in IC design

FILING FEE FEES: Authority has been given in Paper No. to charge/credit DEPOSIT ACCOUNT

RECEIVED No. for following: 411

h e e e e e c

Page 1 o

UNITED STATFS DEPARTMENT OF COMMERCE United States Patent and Trademark Office Addre": COMMISSIONER FOR PATENTS

P.O.llox 14'0 Al""""dria, Vu:gi.nia 22313·1450 www.uspto.gov

CONFIRMATION NO.3

GROUP ART UNIT ATIORNEY DOCKET NO

2825 P1377

SHEETS TOTAL INDEPENDEN

DRAWING CLAIMS CLAIMS 5 24 2

ID All Fees

I CJ 1.16 Fees ( Filing )

I CJ 1.17 Fees ( Processing Ext. of time )

ID 1.18Fees{lssue)

ID Other

ID credit

Index of Claims Application No. Applicant(s)

I I I I II 111111 II 10/390,194 DAGA, AJA Y JANAMI Examiner Art Unit

Sun J Lin 2825

..; Rejected - (Through numeral) Cancelled N Non-Elected A Appeal

= Allowed + Restricted I Interference 0 Objected

Claim Date Claim Date Claim Date

1\l (ij

~ iii (ij iii

c:: c:: iii c:: c:: ·a "' c:: ·a c:: ·a ii ·c:: ii) ii ·c ii ·c::

0 0 0

1 .,J 51 101 2 0 52 102 3 0 53 103 4 .,J 54 104 5 .,J 55 105 6 .,J 56 106 7 .,J 57 107 8 .,J 58 108 9 .,J 59 109 10 0 60 110 11 0 61 111 12 .,J 62 112 13 .,J 63 113 14 0 64 114 15 0 65 115 16 .,J 66 116 17 .,J 67 117 18 .,J 68 118 19 .,J 69 119 20 .,J 70 120 21 .,J 71 121 22 0 72 122 23 0 73 123 24 .,J 74 124 25 75 125 26 76 126 27 77 127 28 78 128 29 79 129 30 80 130 31 81 131 32 82 132 33 83 133 34 84 134 35 85 135 36 86 136 37 87 137 38 88 138 39 89 139 40 90 140 41 91 141 42 92 142 43 93 143 44 94 144 45 95 145 46 96 146 47 97 1'""1 147 48 98 HI 148 49 99 I:'' I 149 50 100 I I 150


Search Notes Application No. Applicant(s)

1111~1111111111111111111 10/390,194 DAGA, AJAY JANAMI Examiner Art Unit

Sun J Lin 2825

SEARCHED SEARCH NOTES

(INCLUDING SEARCH STRATEGY)

Class Subclass Date Examiner DATE EXMR

716 1 8/10/2004 JSL EAST (USPAT;US- 8/10/2004 JSL PGPUB;UPO;JPO;DERWENT;IBM_ T DB]

716 6 8/10/2004 JSL

IEEE 8/10/2004 JSL

INTERFERENCE SEARCHED

Class Subclass Date Examiner


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LNumber Hits Search Text DB Time stamp 1 0 (clock adj specification) and ((phase adj shift) near (reference adj USPAT; 2004/08110 15:57

clock)) and (period) US-PGPUB; EPO; JPO; DERWENT; IBM_IDB

2 10 ((phase adj shift) near (reference adj clock)) and (period) USPAT; 2004/08/10 15:58 US-PGPUB; EPO; JPO; DERWENT; IBM_IDB

3 0 (specification) same ((phase adj shift) near (reference adj clock)) same USPAT; 2004/08/10 15:58 (period) US-PGPUB;

EPO; JPO; DERWENT; IBM_IDB

- 1580 716/1 USPAT; 2004/08/10 12:51 US-PGPUB; EPO;JPO; DERWENT; IBM_IDB

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- 0 (716/l).ccls. and (timing adj constraint) and (synthesiz$ adj description) USPAT; 2004/08/10 12:53 and ( clock adj specification) US-PGPUB;

EPO;JPO; DERWENT; IBM_IDB

- I (716/6).ccls. and (timing adj constraint) and (synthesiz$ adj description) USPAT; 2004/08/10 12:53 and ( clock adj specification) US-PGPUB;


- 1 (716/$).ccls. and (timing adj constraint) and (synthesiz$ adj description) USPAT; 2004/08110 13:35 and (clock adj specification) US-PGPUB;


- 1 (timing adj constraint) and (synthesiz$ adj description) and (clock adj USPAT; 2004/08/10 15:23 specification) US-PGPUB;


- 0 (relaxation same (clock adj requirements)) and (timing adj constraint) USPAT; 2004/08/10 13:43 and (synthesiz$ adj description) and (clock adj specification) US-PGPUB;


- 0 (relaxation same (clock adj requirements)) and (timing adj constraint) USPAT; 2004/08/1 0 13:44 and (clock adj specification) US-PGPUB;


- 0 (relaxation same (clock adj requirements)) and (timing adj constraint) USPAT; 2004/08/10 13:44 US-PGPUB; EPO;JPO; DERWENT; IBM IDB

Search History 8/10/04 3:59:40 PM Page 1

C:\APPS\east\workspaces\CASE 191. wsp

- 1 (relaxation same (clock adj requirements)) and (clock adj specification) USPAT; 2004/08/10 13:45 US-PGPUB; EPO;JPO; DERWENT; IBM_TDB

- 1 (relax$ same (clock adj requirements)) and (clock adj specification) USPAT; 2004/08/10 14:57 US-PGPUB; EPO; JPO; DERWENT; IBM_TDB

- 2 (relax$ same (clock adj requirements)) USPAT; 2004/08/10 13:51 US-PGPUB; EPO; JPO; DERWENT; IBM_TDB

- 0 (relax$ same (clock adj requirement)) USPAT; 2004/08/10 13:52 US-PGPUB; EPO;JPO; DERWENT; IBM_TDB

- I (exceptions near ((single adj cycle) adj clock$)) USPAT; 2004/08/10 13:54 US-PGPUB; EPO; JPO; DERWENT; IBM_TDB

- 2 (synopsys adj (design adj constraint)) USPAT; 2004/08/10 13:55 US-PGPUB; EPO;JPO; DERWENT; IBM_TDB

- 0 (timing adj constraint) and ((VHDL or HDL or Verilog) same (lib adj USPAT; 2004/08/10 15:25 model)) US-PGPUB;

EPO;JPO; DERWENT; IBM_TDB

- 1 ((VHDL or IIDL or Verilog) same (lib adj model)) USPAT; 2004/08/10 15:26 US-PGPUB; EPO; JPO; DERWENT; IBM_TDB

- 92 ((VHDL or IIDL or Verilog) same (deriv$) same (model)) USPAT; 2004/08/10 15:30 US-PGPUB; EPO;JPO; DERWENT; IBM_TDB

- 2 ((VHDL or HDL or Verilog) near (deriv$) near (model)) USPAT; 2004/08/10 15:32 US-PGPUB; EPO;JPO; DERWENT; IBM_TDB

- 1 (model) near (conver$) near (VHDL or IIDL or Verilog) USPAT; 2004/08/10 15:38 US-PGPUB; EPO;JPO; DERWENT; IBM_TDB

- 0 (lib adj model) near (VHDL or HDL or Verilog) USPAT; 2004/08110 15:38 US-PGPUB; EPO; JPO; DERWENT; IBM TDB

Search History 8/10/04 3:59:40 PM Page 2

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UTILITY PATENT APPLICATION

TRANSMITTAL

for new

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SeeMPEP 600

1. 00 Fee Transmittal Form (e.g., PTO/SB/17) (Submit an original and a duplicate for fee processing)

2. 00

contents.

3. [i]

Applicant claims small entity status. See 37 CFR 1.27. Specification [Total Pages ~] (preferred arrangement set forth below}

4. 00

- Descriptive title of the invention - Cross Reference to Related Applications - Statement Regarding Fed sponsored R & D - Reference to sequence listing, a table,

or a computer program listing appendix - Background of the Invention - Brief Summary of the Invention - Brief Description of the Drawings (jf filed) - Detailed Description - Claim(s) - Abstract of the Disclosure

Drawing(s) (35 U.S. C. 113) [Total Sheets

5. Oath or Declaration [Total Pages

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D Copy from a prior application (37 CFR 1.63 (d)) b. (for continuation/divisional with Box 18 completed)

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(Si

An Automated Approach to Constraint Generation in IC Design

by inventor Ajay .Janami Daga

Field of the Invention

The present invention is in the technical area of integrated circuit (IC)

design, and pertains more specifically to Electronic Design Automation (EDA)

tools providing methods and apparatus for generating timing constraints in a

design project.

Cross Reference To Related Documents

The present non-provisional patent application claims priority to

provisional application serial number 60/365,749, filed on 03/18/2002. The

entire disclosure of provisional application 60/365,749 is incorporated herein

by reference.

Background of the Invention

The term integrated circuit (IC) is a very general term covering a very

broad range of electronic devices based on solid-state electronics, such as

microprocessors. It is now notoriously well-known that a vast array of

consumer products, especially those products in the area of

telecommunications and computerized devices (including personal computers),

-2-

are based on ICs, such as central processing units (CPUs), microprocessors,

and, of course, digital memory devices of many sorts.

In the art of IC design and manufacturing, ongoing research and

development in a highly competitive environment is conducted to produce new

and better devices, which are manufactured by usually well-know techniques

involving many ways of treating semiconductor materials (wafers), applying

thin-film materials, patterning, and selectively removing materials to create

highly concentrated matrices of interconnected semiconductor elements, such

as transistors, providing, in the end, minute, complex circuitry to perform

specific tasks of computation and logic with almost unbelievable rapidity and

reliability.

Also typically, in the manufacturing process, many ICs are formed on a

single wafer. After what is termed in the art the "front-end" processing, during

which the ICs are formed, the individual ICs are separated into discrete units

termed chips in the art, which may then be packaged and used in a wide variety

ofways for different products and purposes.

When developmental engineers conceive a new chip, it is of course

necessary to lay out all of the circuits that will accomplish the purposes, which

amounts to placing all transistors, resistors, and other devices, and plotting the

interconnections that complete the circuitry. In the very early days of chip

design this was a relatively straightforward process, at least a lot more

straightforward than it is today. The trend in design, however, has always

quite naturally been to faster and faster operation (clock speed), higher and

higher density (area needed for circuitry), and lower power consumption to

attain maximum computing or storage power in the least possible space. The

speed motivation is obvious. Part ofthe density motivation is dictated by

space and volume requirements in product design, and part by cost

considerations. More good chips per wafer drives the cost per part down.

-3-

As need for density and speed steadily increase, new challenges arise in

IC design. For example, specific manufacturing techniques, lithography for

example, are always limited to such as minimum spacing of elements on a

chip, line width in interconnects, and the like, and to achieve higher density it

is often necessary to invent new processing techniques or improvements in

older techniques. Likewise, even though higher density has a usually

beneficial effect on speed capability (devices are connected closer together),

allowing higher operating rate (clock speed), there are always limitations

associated with device structure, materials, and the like, to speed as welt, and

achieving higher and higher speed involves new inventions and discoveries in

materials, combinations of materials, structures of devices, and so on.

It therefore becomes apparent that a circuit diagram is only a starting

point in a new IC design, even though massive computing engines are needed

even for this seminal part of a design. Given stringent requirements for a new

design for speed, density, and power consumption, development engineers

have to pick very carefully among many alternatives for materials, processes,

film characteristics and thicknesses, interconnection alternatives, and much

more; and the selections one makes almost always influence other possible

selections and decisions, as all are intimately related.

Still, even in the face of the complexity ofthe task, small market

windows and short product lifecycles provide no room for error in the

execution of chip design projects - schedule slippage is measured not just in

terms of additional R&D costs, but in lost market opportunities that can be

fatal for a company. Integrated circuit designers are therefore under

tremendous pressure to design complex chips to meet design and marketing

requirements.

The design of complex multi-million-transistor chips requires the

pervasive use of electronic design automation (EDA) software tools. These

tools are used to take high-level descriptions of designs in languages that are

"!L !L!!

- 4-

very similar to programming languages and yield, through a series of

complicated steps, the final mask for a chip. This flow is referred to as RTL to

GDS-II (RTL is the initial design description in Verilog, VHDL and GDS-II is

the mask for chip manufacturing).

To counter the risk of designs not converging on requirements,

engineers use virtual prototyping tools, a type ofEDA tool, to estimate

downstream chip implementation characteristics (speed, area, power) from

early design descriptions. The intent is to get an early gauge of design

feasibility. Virtual prototyping tools have garnered significant interest in the

design community, and virtual prototyping is among the fastest growing of

EDA market segments.

Virtual prototyping tools arguably provide reasonable estimates of

delays along timing paths on a chip. The feasibility of a design, however,

hinges on whether these delays are actually within acceptable bounds. Without

good constraints on the permissible delays for the millions of timing paths on a

chip, virtual prototyping tools are insufficient to gauge actual design

feasibility. Absence of good timing constraints early in the design flow also

results in chip implementation tools (logic synthesis, place & route) being

asked to meet requirements that are both unnecessarily stringent and uncertain.

This severely impacts ability of such tools to generate low-cost, low-power

implementations that meet performance requirements without requiring design

iterations.

What is clearly needed is a tool that starts with the fundamental speed

performance requirements for an IC to be designed, i.e. its clock speed, and by

examining the intended functionality ofthe new chip in regard to how it will

be clocked is capable of precisely identifying and constraining acceptable

delays of timing paths on the new chip. Such a tool could generate golden

timing constraints that must be obeyed for the finished chip to operate at its

intended clock speed. Fundamental to the golden timing constraints for a chip

!!"'!!

- 5-

is that they describe not only the bounds on path delays that are established by

the clock requirements of a chip, but that they also identify paths on a chip

where clock requirements are relaxed. The relaxation of clock requirements is

referred to in the industry as "exceptions to single-cycle clocking". The

automatic identification ofthe exceptions to single-cycle clocking is

fundamental to the generation of the golden timing constraints for a chip.

The golden constraints, once determined, could then be used to drive

existing virtual prototyping tools, logic synthesis tools, and place & route

tools. The use of the golden constraints could, because of the automatically

generated exceptions to clock requirements, then empower chip design without

expensive and time consuming iterations, while also yielding chips that

consume less area, less power, or, if required, run faster than was thought

possible.

A unique and innovative software system, called Focus by the

inventors, for developing such golden timing constraints in IC design is taught

in enabling detail in the descriptions of preferred embodiments below.

Summary of the Invention

In a preferred embodiment ofthe present invention a software-based

system for generating timing constraints for a proposed IC design is provided,

comprising a first input as a synthesizable description of the proposed IC, a

second input as a clock specification for the proposed IC, and a processing unit

accepting the first and second inputs, and determining therefrom as an output a

set oftiming constraints to guide implementation ofthe proposed IC design.

In preferred embodiments, the processing unit, in determining the

timing constraints, determines exceptions to single-cycle clocking for the

proposed IC design. Further, in a preferred embodiment the exceptions include

-6-

false paths and multi-cycle paths. Output in a preferred embodiment is

provided in Synopsys Design Constraint (SDC) format useable by one or more

of virtual prototyping, logic synthesis, place & route, and static timing tools in

design implementation. The IC may be of any of many sorts, including

application-specific integrated circuits (ASIC) or field-programmable gate

arrays (FPGA).

In one aspect of the invention the first and second inputs and output

timing constraints may be for an individual functional block on an IC instead

of for the entire I C. In another aspect the first and second inputs and output

timing constraints may be for paths between functional blocks on an IC. In the

latter case the results may be used to partition overall IC timing requirements

into b Jock timing budgets.

In preferred embodiments the synthesizable description is provided as

one ofVerilog or VHDL format. In other embodiments the first input may be

derived from a Jib model, and converted into one ofVerilog or VHDL format.

In one embodiment a facility is provided for a user to manually refine an

automatically-generated model by adding functional detaiL In various

embodiments, as a part of clock specification, users may define the clocks,

their periods, their phase shifts relative to a reference clock, and the nets on the

design to which a clock is applied.

In another aspect of the invention a method for guiding an

implementation phase for a proposed IC design is provided, comprising the

steps of (a) providing to a processing unit as a first input a synthesizable

description ofthe proposed IC; (b) providing as a second input to the

processing unit clock specification for the proposed IC; and (c) using the first

and the second inputs by the processing unit to determine therefrom, as an

output, a set of timing constraints to guide implementation of the proposed IC

design.

- 7-

In preferred embodiments ofthe method, in step (c), the processing

unit, in determining the timing constraints, determines exceptions to single

cycle clocking for the proposed IC design. The exceptions may include false

paths and multi-cycle paths.

Also in preferred embodiments ofthe invention the output is provided

in Synopsys Design Constraint (SDC) format useable by one or more ofvirtual

prototyping, logic synthesis, place & route, and static timing tools in design

implementation. The method in preferred embodiments is applicable

application-specific integrated circuits (ASICs) or field-programmable gate

arrays (FPGAs), as well as to many other sorts ofiCs.

In some cases the first and second inputs and output timing constraints

may be for an individual functional block on an IC instead of for the entire IC.

Also in some cases the first and second inputs and output timing constraints are

for interaction paths between functional blocks on an IC, and may be used to

partition overall IC timing requirements into block timing budgets.

In preferred embodiments the synthesizable description is provided as

one ofVerilog or VHDL format. In other embodiments the first input may be

derived from a .lib model, and converted into one ofVerilog or VHDL format.

Further, there may be a facility provided for a user to manually refine an

automatically-generated model by adding functional detail.

In other embodiments of the present invention, as part of the clock

specification, users define the clocks, their periods, their phase shifts relative to

a reference clock, and the nets on the design to which a clock is applied.

The Focus system, as summarized above, provides significant

advantages in IC design, by providing:

• A reduction in the risk of design failures by providing engineers an

early understanding of the precise challenges they face in realizing a

design. By providing virtual-prototyping tools with golden timing

-8-

constraints, the Focus system empowers the tools to create more

realistic block timing budgets. Correct block implementation

constraints, in tum, reduce the risk of design iterations.

• A reduction in the cost and power consumption of a design. By

generating timing constraints that do not over-constrain a design, the

Focus system allows block implementation tools to generate circuits

that consume as little area and power as possible, while meeting

performance objectives. Reduction in IC area typically translates to a

reduction in unit costs. Reduction in power consumption is crucial for

several consumer products.

• A reduction in IC design time by automating a task that is central to IC

design. Engineers conventionally specify timing constraints in an ad

hoc and continually evolving manner. As timing problems are

uncovered, and most of them tend be uncovered late in the

implementation flow, exceptions to single-cycle clocking are inserted.

All ofthis takes time, is error-prone and is the source of much anxiety

during IC sign-off

• The Focus system empowers an RTL-handoff-based design flow. With

the Focus system, system design houses are able to describe the design

they want to implement and hand this design, along with its constraints,

to a semiconductor vendor that will take responsibility for

implementing the design to meet requirements. Semiconductor vendors

typically prefer RTL handoffbecause it allows them to take

responsibility for a greater portion of the design flow. System design

houses prefer RTL handoffbecause it allows them to focus on their

core competency, which is the design of compelling products.

-9-

In embodiments ofthe invention described in enabling detail below, for

the first time a system is provided that allows users to identify false and multi

cycle paths ahead of implementation of a proposed design, and to use timing

constraints determined therefrom in implementing the proposed design.

Brief Description of the Drawing Figures

Fig. l is a block diagram illustrating overall operation ofFocus system

I 03 in a preferred embodiment of the present invention_

Fig. 2a is a first part of an example of a synthesizable description

furnished as input to the system in an embodiment of the present invention.

Fig. 2b is a final part of the example for which the first part is Fig. 2a_

Fig. 3 illustrates a clock specification input to the Focus system in an

embodiment of the present invention.

Fig. 4 is an SDC file generated for the example design described below

with reference to Figs. 2a, 2b, and 3 in an embodiment ofthe present

invention.

Description of the Preferred Embodiments

The system of the present invention, in a preferred embodiment, is a

software-enabled system that automatically (i.e. without user-specified

stimulus), analyzes a cycle-accurate description of interaction among

functional blocks on a proposed IC, to generate timing constraints that must be

satisfied by the IC to meet design requirements.

It is well-known that there are, broadly speaking, two historically

distinct stages in the creation of a new IC: (1) the design stage, and (2) the

- 10-

implementation stage. The system of the invention, termed Focus by the

inventors, links the two stages for the first time by establishing constraints

imposed on the implementation stage by facts and characteristics of the design

stage.

It is well-known that development engineers constrain the delays on the

timing paths of a proposed IC based on the speed at which they intend to clock

the IC. The engineers specify the clocks on their design and every timing path

on the IC is required to have a delay less than the clock cycle. Known IC

implementation tools strive to reduce path delays so that they are less than a

clock cycle. There are, however, large numbers of timing paths in almost any

design that are not relevant, that is, the functionality of the IC is such that the

delay on these paths does not matter. These paths are typically termed false

paths, although they are false only in terms of the fact that the delay does not

matter. There are also typically a significant number of timing paths on a

proposed IC wherein, by design, engineers provide extra time to perform

complex operations. These paths are termed multi-cycle paths. False and

multi-cycle paths are collectively referred to as exceptions to single-cycle

clocking.

The present inventors have determined that the critical timing

constraints for an IC are defined by the clocks and exceptions to single-cycle

clocking. At the time of filing the present patent application, it is known that

engineers do not typically specify exceptions to clocking at the start of design

flow. Instead, the engineers respond to timing problems reported by

conventional IC implementation tools and, based on communication between

design and verification engineers, establish whether a timing problem is real or

needs to be handled by adding a timing exception to the constraint file for a

design. This conventional process is an error-prone, time-consuming, process

that continues throughout IC implementation flow, and compounds errors in

the overall process.

- 11-

Overview

Fig. 1 is a block diagram illustrating overall operation ofFocus system

1 03 in a preferred embodiment of the present invention. The Focus system, as

shown by the flow ofFig. 1, takes as inputs the synthesizable description for a

design for an IC (102) and a specification for how the design is clocked (101).

Without requiring any other information, the Focus system generates

exceptions (false paths, multi-cycle paths) to single-cycle clocking. By

automatically identifying exceptions to clock requirements, the Focus system

relaxes the timing goals that an IC implementation must to obey. These

exceptions and the user-provided clock definitions constitute golden timing

constraints 104 for an IC under consideration. These constraints are written

out in the industry standard Synopsys Design Constraint (SDC) format and are

read and used by virtual prototyping, logic synthesis, place & route, and static

timing tools, as shown in block 105.

Applications in Design Flow

The Focus system is applicable to at least any digital application

specific integrated circuit (ASIC) or field-programmable gate array (FPGA)

design and implementation. The Focus system is applicable as well for both

synchronous and asynchronous designs. Focus is also applicable for the design

of large and complex SaCs that contain l 0 million or more gates and run at

clock speeds in excess of 300 megahertz (MHz), as well as for the design of

FPGAs containing less than a million gates that run at speeds up to 1 OOMHz or

more. Further, the Focus system may be used to constrain and drive the

implementation of individual blocks within an IC, as well as the entire I C.

Considering the full IC, the Focus system is used to generate the golden

timing constraints that constrain the interaction among blocks on the IC. These

- 12-

constraints are then imported by such as virtual prototyping tools, and used to

partition overall IC timing requirements into block timing budgets that

establish when information is available at the inputs of a block and when

information must be available at the outputs of a block

Considering IC block implementation flow, the Focus system generates

the golden timing constraints for the internal implementation of a block. These

block constraints, along with the block timing budgets generated using the

Focus system and virtual prototyping tools, may be used to drive block

implementation tools such as logic synthesis tools, place & route tools, and

static timing tools.

The Focus system in preferred embodiments is plug-and-play in

existing design flow. Therefore engineers do not need to alter the way they do

design, and they need to provide only minimal new information to the Focus

system. The information the Focus system requires, which is substantially

synthesizable design descriptions and clock specifications, is already at hand at

the start of IC implementation flow. The information the Focus system

generates is generated in a standard form (SDC) that is accepted across the

industry by major EDA players and start-ups alike. The Focus system does not

replace existing design tools, it simply makes them more effective.

Synthesizable Description Input (102 of Fig. 1)

The Focus system takes as input the synthesizable description for an IC

design and a specification of the clocks on the design. The synthesizable

description for a design is provided as input to Focus in Verilog or VHDL

format, both of which are well-known to the skilled artisan. All conventional

synthesizable constructs in these languages are supported by the Focus system.

Information for blocks on an lC design that do not have synthesizable

descriptions, such as for external hard IP blocks, embedded memory, or user-

- 13-

instantiated library cells, for example, is provided as input to the Focus system

using one oftwo approaches:

1) Users can provide a .lib model for the block as input. This model

describes black-box timing relationships between pins on the block.

This model is converted into a behavioral HDL model (Verilog or

VHDL format) that captures the timing relationships between pins on

an IP block. Users can refine this auto-generated model manually by

adding functional detail.

2) Alternatively, IP providers can use a known product known as Reduce

from FishTail Design corporation to generate an interface-logic model

(ILM) from a synthesizable description for an IP block. This interface

logic model, generated in Verilog or VHDL format, may be used as

input to Focus in lieu of the full synthesizable description for a block.

The constraints for a design can be generated using either a flat or

hierarchical methodology. In a flat methodology, the Verilog and VHDL files

for the full design are read into the Focus system. An example input as

synthesizable description is illustrated in Figs. 2a and 2b, as the example is too

large for a single drawing sheet. In a hierarchical methodology, individual

blocks on the design are analyzed separately and ILM descriptions for these

blocks are used when analyzing the full-chip.

Clock Specification Input (101 of Fig. 1)

In addition to the synthesizable description for a design, as described in

examples above, to apply the Focus system users need to specify the clocks on

the proposed IC design. As part of their clock specification users define the

clocks, their periods, their phase shifts relative to a reference clock, and the

nets on the design to which a clock is applied. Fig. 3 illustrates a clock

- 14-

specification input to the Focus system in an embodiment of the present

invention.

Focus Analysis (103 of Fig. 1)

Given both the synthesizable description for an lC design and a

specification for the clocks on the design, the Focus system proceeds to

automatically identify false and multi-cycle paths. This analysis is performed

without synthesizing the design description into a gate-level netlist. Instead,

functional abstraction is performed on the design to only preserve the

functional detail necessary for the purposes of computing false and multi-cycle

paths, while discarding superfluous functional detail. Symbolic simulation is

performed on the functionally abstracted design to ensure that the analysis is

exhaustive and is performed without requiring user-specified stimulus.

Functional abstraction helps ensure that the entire space of possible behaviors

on a design can be symbolically simulated in a computationally feasible

manner that scales to handle large designs.

Generated by Focus- Golden Timing Restraints (104 of Fig. 1)

The user-specified clocks and the false and multi-cycle paths identified

and determined by the Focus system are written out (output) in Synopsys

Design Constraint (SDC) format to a text file. The information in this text file

constitutes the golden timing constraints for an IC design. IC implementation

tools such as virtual prototyping, logic synthesis, place & route and static

timing ( l 05 of Fig. 1) import these constraints. The SDC file generated for the

example design is shown in Fig 4.

It will be apparent to the skilled artisan that there will be a variety of

alterations that may be made in embodiments ofthe invention described herein

- 15-

without departing from the spirit and scope of the invention. For example,

there are generally a number of different ways that a software application may

be written to accomplish similar or the same purposes, and there are typically

also a variety of programming languages that may be used to create software

for a system such as that described in preferred embodiments in the present

specification. For these and other reasons the invention should be limited only

by the scope of the claims that follow:

- 16-

What is claimed is:

l. A software-based system for generating timing constraints for a proposed

IC design, comprising:

a first input as a synthesizable description of the proposed IC;

a second input as a clock specification for the proposed IC; and

a processing unit accepting the first and second inputs, and determining

therefrom as an output a set of timing constraints to guide implementation of

the proposed IC design.

2. The system of claim 1 wherein the processing unit, in determining the

timing constraints, determines exceptions to single-cycle clocking for the

proposed IC design.

3. The system of claim 2 wherein the exceptions include false paths and multi

cycle paths.

4. The system of claim 1 wherein the output is provided in Synopsys Design

Constraint (SDC) format useable by one or more of virtual prototyping, logic

synthesis, place & route, and static timing tools in design implementation.

5. The system of claim 1 wherein the IC is one of an application-specific

integrated circuit (ASIC) or a field-programmable gate array (FPGA).

ll..]L ,., f"'!l

- 17-

6. The system of claim l wherein the first and second inputs and output timing

constraints are for an individual functional block on an IC instead of for the

entire IC.

7. The system of claim 1 wherein the first and second inputs and output timing

constraints are for paths between functional blocks on an IC.

8. The system of claim 7 wherein results are used to partition overalllC


9. The system of claim 1 wherein the synthesizable description is provided as

one of Veri log or VHDL format.

10. The system of claim l wherein the first input is derived from a .lib model,

and converted into one of Veri log or VHDL format.

11. The system of claim 10 wherein a facility is provided for a user to


12. The system of claim 1 wherein, as part of the clock specification users

define the clocks, their periods, their phase shifts relative to a reference clock,

and the nets on the design to which a clock is applied.

13. A method for guiding an implementation phase for a proposed IC design,

comprising the steps of:

- 18-

(a) providing to a processing unit as a first input a synthesizable

description ofthe proposed IC;

(b) providing as a second input to the processing unit clock

specification for the proposed IC; and

(c) using the first and the second inputs by the processing unit to

determine therefrom, as an output, a set of timing constraints to guide

implementation of the proposed lC design.

14. The method of claim 13 wherein, in step (c), the processing unit, in

determining the timing constraints~ determines exceptions to single-cycle

clocking for the proposed lC design.

15. The method of claim 14 wherein the exceptions include false paths and

multi-cycle paths.

16. The method of claim 13 wherein the output is provided in Synopsys

Design Constraint (SDC) format useable-by one or more of virtual prototyping,

logic synthesis, place & route, and static timing tools in design

implementation.

17. The method of claim 13 wherein the IC is one of an application-specific

integrated circuit (ASIC) or a field-programmable gate array (FPGA).

18. The method of claim 13 wherein the first and second inputs and output

timing constraints are for an individual functional block on an IC instead of for

the entire IC.

- 19-

19. The method of claim 13 wherein the first and second inputs and output

timing constraints are for interaction paths between functional blocks on an IC.

20. The system of claim 19 wherein results are used to partition overalllC


21. The method of claim l3 wherein the synthesizable description is provided

as one ofVerilog or VHDL format.

22. The method of claim 13 wherein the first input is derived from a .lib

model, and converted into one of Veri log or VHDL format.

23. The method of claim 22 wherein a facility is provided for a user to

manually refine an automatically-generated model by adding functional detaiL

24. The method of claim l3 wherein, as part of the clock specification users

define the clocks, their periods, their phase shifts relative to a reference clock,

and the nets on the design to which a clock is applied.

-20-

Abstract of the Disclosure

A software-based system for generating timing constraints for a

proposed lC design has a first input as a synthesizable description of the

proposed IC, a second input as a clock specification for the proposed IC, and a

processing unit accepting the first and second inputs, and determining

therefrom. as an output, a set of timing constraints to guide implementation of

the proposed IC design.

101

103 (104 Specification ~

Read and Used by:

Virtual Prototyping FOCUS Tool I ~I Golden Timing Logic Synthesis

Constraints Place & Route Synthesizable HDL I \ J

Static Timing Verilog, VHDL Generates exceptions Results

to single-cycle clocking Exceptions '-105

& Clock Definitions

., • ..;<...

102

Fig.l

(Start)

n1odule add_1nul (elk, reset, a, b, c, d, in_sel, op_sel, x, y); input elk, a, b, c, d, in _sel, op _sel, reset; output x, y; regx, y, count, latch_en, r_a, r_b, r_c, r_d, r_op_sel, r_in_sel; wire r_x, r_y, a_c, b_d, add, 1nul, add_Inul; always@ (posedge elk or posedge reset) begin if (reset) begin

count<= 0; latch en <= 0 ·

- ' r a<= o·

- ' r b <= o·

- ' r c <= o·

- ' r d <= o·

- ' r_op_sel <= 0; r in sel <= o·

- - ' end else begin

if (!count) begin r_a <=a; r b <= b·

- ' r_c <= c; r d <= d·

- ' r _ op _sel <= op _sel; r_in_sel <= in_sel; if(op_sel)

count <= count + 1 ; else

latch en<= 1 'b1· - '

end else begin

count<= 0; latch en<= 1'b 1·

- ' end

end end

(Continued on Fig. 2b)

Fig. 2a

(Continued from Fig. 2a)

ass_ign a_c = r_in_sel? r_a: r_c; assign b_d = r_in_sel? r_b: r_d; assign add = a_c + b_d; assign n1ul = a_c * b_d~ assign add _n1ul = r _ op _sel ? tnul : add; assign r _ x = r _in _sel ? add_ mul : x; assign r_y = r_in_sel? y: add_mul; alvvays@ (posedge elk or posedge reset) begiri

if (reset) begin X<= 0; y <= 0;

end else if (latch_ en) begin

x <= r_x; y <= r_y;

end end endtnodule

(END)

Fig. 2b

read_ design add_ mul. v link_ design create_clock clk200 -period 5 -net { elk} write sdc add mul. sdc

Fig. 3

#Clock Definitions

set clk200 _source _pins {} set clk200 _source_ nets [get_nets { elk } ] set clk200_source_pins [add_to_collection $clk200_source_pins \

[get _pins -of $clk200 _source_ nets]] create_clock -name clk200 -period 5 -waveform { 0 2.5 } $clk200 _source _pins

#Exceptions for endpoints clocked by clk200

set_tnulticycle _path -through [get_ nets mul] -setup 2 set_ multi cycle _path -through [get_ nets 111ul] -hold 1 set_false_path -through [get_ nets r_c] -through [get_ nets r_x] set_false_path -through [get_nets r_d] -through [get_nets r_x] set_ false _path -through [get_nets r_a] -through [get_nets r__y] set_false_path -through [get_nets r_b] -through [get_ nets r__y]

Fig. 4

Mar 13 2003 4:08PM

DECLARATION AND PO\VER OF ATTORNEY FOR PATENT APPLICATION

A TIORNEY DOCKET NO. P1377

As a below named inventoT, I hereby declare that: My residence, post office address and citizenship are as stated be low nex.t to my name. I believe I am the original, first and sole inventor (if only one name is listed below) or an original, first lllldjoint inventor (if plural names are listed below) of the subject matter which is claimed and for which a patent is sought on the invention entitled: Automated APProach to Constraint Generation in IC Design

the specification of which (check one) ~ is attached hereto. 0 was filed on: as patent aoolication serial number 0 and was amended on __

(If applicable) I hereby state that 1 have reviewed and understood the contents of the above-identified specification, including the

claims, as amended by any amendment referred to above. I acknowledge tbe duty to disclose information which is material to patentability in accordance with Title 37, Code of Federal Regulations sec. 1.56. In the case that the present application is a continuation-in-part application, J further acknowledge the duty to disclose material information as defined in Title 37, Code of Federal Re~ulations sec. 1.56. which became available between the filing date ofthe prior application and the filing date of the present application. I hereby claim foreign priority benefits under Title 35, United States Code sl19 of any foreign applications for patent or inventor's certificate listed below and have also identified below any foreign application for patent or inventor's certificate having a filing date before that ofthe application on which priority is claimed:

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