130523242-tai-liệu-tham-khảo-về-PIC-va-một-số-vấn-đề-lien-quan

7/30/2019 130523242-tai-liu-tham-kho-v-PIC-va-mt-s-vn--lien-quan

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ti liu tham kho v PIC v mt s vn lin quan

gi biviettran Th 2 12/11/12 10:352.1 Vi iu khin PIC 18F4431:2.1.1 Gii thiu chung v h vi iu khin PIC ca hngMicrochip:

Hnh 2.3: Cc h vi iu khin PICPIC (Programmable intelligent Controller) do hng GeneralInstrument t tn cho con vi iu khin u tin ca h: PIC1650. Hng Microchip tip tc pht trin sn phm ny. Cho n

nay, cc sn phm vi iu khin PIC ca Microchip c gn100 loi sn phm t 10Fxxx n 12Cxxx, 12Fxxx, 16Cxxx,17Cxx, 16Fxx, 16Fxxx, 16FxxA, 16FxxxA, 16LFxxxA, 18Fxxx,18LFxxx, 18Fxxxx, 18LFxxxx.Cch phn loi PIC: Theo ch ci:- Cc h c ch C nh PIC xxCxxx thuc nhm OTP (One TimeProgrammable) chc th lp trnh v np cho n moat ln duy

nht.- Cc h c ch F hoc LF (thuc nhm Flash) cho php ghi vxa nhiu ln bng cc mch in t thng thng. Theo hai ch su tin:- 8 bit: PIC10 PIC12 PIC16 PIC18- 16 bit: PIC24F PIC24H dsPIC30 dsPIC33Ty theo nhng ng dng c th m ngi dng c th chn raloi chip ph hp. Trong PIC18F4431 lIC chuyn dng

iu khin ng c theo ngh ca nh sn xut.
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2.1.2 Tng quan v vi iu khin PIC 18F4431:a. Nhng c im chung ca PIC 18F4431:- L CPU s dng tp lnh RISC v c tc x l cao, cngsut thp nh s dng cng ngh CMOS FLASH/EEPROM.

- Tp lnh gm 75 lnh.- Mt chu k lnh bng 4 chu k xung clock. Tn s dao ngcho php ti 40Mhz. Cho php chn la ch dao ng(ni/ngoi).- 8K x 14 word b nh FLASH lp trnh.- B nh SRAM 768 byte, bn cnh b nh EEPROM ln n256 byte.- Trang b 34 ngt vi 8 cp ngt.

- 5 Port I/O.- Trang b 3 bnh thi (Timer): 2 b 8 bit, 1 b 16 bit.- module Capture/Compare/PWM.- B chuyn i ADC 10 bit vi 9 knh, tc 5 10 us.- Cng serial ng b vi ch SPI (Master) v I2C(Master/Slave) thc hin bng phn cng.- Cng giao tip ni tip ng b/bt ng b vi 9 bit a chkim tra.

- Cng giao tip song song (PSP) 8 bit.- Cc chnh a chtrc tip, gin tip v tng i.- Cho php c/ghi b nh chuwong trnh.- C ch ba v m lp trnh v ch SLEEP tit kimin nng.- Tm in th hot ng rng t 2 n 5.5V. Dng cp khong25mA.b. Cc module ni bt ca PIC 18F4431:- Module Power Control PWM 14 bit:C n 4 knh Power Control PWM, mi knh gm 1 cp PWMoutput xung i. C thiu chnh thi gian dead-band mt cch linh hot. C th cp nht ng thi chu k v duty cycle linh hot- Module Motion Feedback c tn hiu hi tip:C 3 knh capture c lp bao gm cc ch hot ng linhhot cho vic o c rng xung, h tr Hall Sensor, c thto tn hiu trigger output cho cc module khc. C kh nng giao tip vi tn hiu xung hi tip t Encoder


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bao gm : 2 ng vo cho 2 pha A, B v 1 ng vo index (xung Z)t encoder. Bn cnh cn h tr vic o c vn tc motor.- Module A/D Converter 10-bit tc cao (200Ksps): C ti 9 knh ADC knh ly mu ng thi. Ly mu lin tc: 1, 2 hoc 4 knh c la chn.- Nhng tnh nng ni bt trong giao tip vi ngoi vi: Chu dng sink/source cao: 25mA. C 3 ngun ngt ngoi.module Capture/Compare/PWM (CCP) trong : Capture 16bit, phn gii ti a 6.25ns; Compare 16 bit, phn gii tia 100ns; PWM phn gii t 1 n 10 bit. Module giao tip ni tip bt ng b (USART): h tr giaotip RS-485, RS-232 v LIN1.2; tng kim tra tc Baud. Giao tip RS-232 s dng khi dao ng ni (khng cn dngthnh anh ngoi).

c. S chn PIC 18F4431:

Hnh 2.13: S chn dng DIP PIC18F4431 Tm tt chc nng cc chn:- PORT A: L port I/O. C tt c 8 chn, t RA0 n RA7. Ni dung cathanh ghi TRISA s qui nh chn no ca port A l input hayoutput. Cc chn RA cn l cc chn input cho Module MotionFeedback. Cc chn RA c thc s dng l ng vo A/D choModule ADC.Chn RA6, RA7 cn c kt hp l ng vo cho b dao ngngoi.- PORT B: L port I/O. C tt c 8 chn, t RB0 n RB7. C thclp trnh bi phn mm s dng chc nng pull-up cho ttc cc ng vo. Vic thay i gi tr thanh ghi TRISB s yt nh

chn no ca port B l Input, chn no l output.


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Bn chn RB c chc nng ngt khi trng thi thay i(chc nng ny khng hot ng khi chn port c quy nh loutput).Su chn RB cn c kt hp s dng l cc chnoutput ca module Power Control PWM.- PORT C: L port I/O. C tt c 8 chn, tRC0 n RC7. Vic thay igi tr thanh ghi TRISC s quyt nh chn no ca port C lInput, chn no l output.RC0 cn c dng lm ng ra b dao ng Timer1 hoc ngvo bm couter 1.RC1 ,RC2 u c thc s dng cho module

Capture/Compare/PWM RC3, RC4, RC5 c th lm chn ng vo cc ngt ngoi INT0,INT1 v INT2 RC6, RC7 c thc s dng lm chn TXD/RXD cho b giaotip bt ng b hoc ng b.- PORT D: L port I/O. C tt c 8 chn, t RD0 n RD7. Vic thay igi tr thanh ghi TRISD s quyt nh chn no ca port D l

Input, chn no l output.Ba chn RD cn c s dng l chn pht xung chomodule Power Control PWM.- PORT E: L port I/O. C tt c 4 chn, t RE0 n RE3. Vic thay igi tr thanh ghi TRISE s quyt nh chn no ca port E lInput, chn no l output., ring chn RE3 chc th l chnInput. Chn RE3 cn l chn ng vo reset (MCLR).- Cc chn ngun : chn 11 v 32 ni ngun dng Vdd; chn 12v 31 ni ngun m Vss.d. Cu trc b nh ca PIC 18F4431:C 3 phn ring bit trong b nh ca PIC18F4431 gm: B nhchng trnh(Program memory), b nh d liu(data RAM) vb nh EEPROM.i) T chc b nh chng trnh:

B nh chng trnh ca PIC18F4431 l b nh flash, dunglng 16Kbytes v c th cha c 8192 lnh n.


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Vect Reset t ti a ch000000h cn Vect ngt th ti ach000008h v 000018h.

Hnh 2.4: S b nh chng trnh v ngn xp ca

PIC18F4431ii) T chc b nh d liu:B nh d liu thuc loi b nh RAM tnh c th cha ti 4096byte d liu. Mi thanh ghi trong b nhc nh a ch12-bit.B nh d liu c chia lm 16 bank thanh ghi, mi bank gm256 byte d liu, 4 bit thp ca thanh ghi Bank Select Registerc dng la chn bank.

B nh d liu bao gm cc thanh ghi chc nng c bit SFR(Special Function Register) v cc thanh ghi a dng GPR(General Purpose Register). Cc thanh ghi SFR c s dngbi CPU v cc b nh ngoi vi iu khin cc hot ngc yu cu ca thit b. Trong khi cc thanh ghi GPR c sdng cha d liu v thc hin cc chc nng theo yu cuca ngi s dng.Ton b cc thanh ghi u c th truy cp trc tip hoc gin

tip thng qua thanh ghi FSG(File Select Register) v BSR(BankSelect Register)iii) T chc b nh EEPROM v FLASH:Vng nh d liu EEPROM v vng nh chng trnh FLASH lvng nh ROM c thc v ghi trong khi chng trnh hotng chvi in th Vcc=+5V. Vic reset h thng cng nhmt in khng lm mt d liu trong vng nh ny. truyxut vng nh ny, ta phi thng qua cc thanh ghi SFR sau:EEDATA, EEADR, EECON1, EECON2.e. Module Power Control PWM:Power Control PWM Module n gin l to ra nhiu xung ngb c rng thay i c (PWM: pulse with modulation). Ccng ra PWM c ng dng trong iu khin ng c v cc ngdng chuyn i cng sut. Module ny h triu khin ccng dng sau:

- ng c khng ng b 1 pha v 3 pha

- ng c kch t


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- ng c DC khng chi than- B cp in lin tc (UPS)- ng c DC c chi thanCc thng s c bn ca Module Power Control PWM:

- C 8 chn ng ra PWM chia lm 4 cp xung i, vi 4 dutycycle c lp nhau.- phn gii 14-bit ph thuc vo chu k xung PWM.- C th thay i chu k xung PWM mt cch linh hot.- Thi gian dead-time c th lp trnh c chng hintng trng dn trong ng dng- C 2 ch cho ng ra PWM l Edge-aligned v Center-aligned- C ch pht xung n

- H tr ngt cho update xung i trong ch Center-alignedS khi ca module Power Control PWM:

Hnh 2.5: S khi Module Power Control PWMTrong Module c 4 b to duty cyle ring bit, chng c nhs t 0 n 3. Module c 8 ng ra c nh s t 0 n 8.Trong ch xung i cc pin chn pin l to thnh 1 cp. Vd: PW0 s xung i vi PWM1; PWM2 s xung i vi PWM3

B Dead-time s chn mt khong thi gian off gia lc xungPWM ca pin ny ang cnh xung cn xung PWM xung itng ng ang cnh ln, iu ny s ngn chn hin tngtrng dn trong iu khin ng m cc kha cng sut.i) Cc thanh ghi iu khin:Hot ng ca Module PWM c iu khin thng qua 22 thanhghi khc nhau. 8 trong sc dng iu chnh cc thngs ca module:- PWM timer control register 0 ( PTCON0)- PWM timer control register 1 ( PTCON1)- PWM control register 0 ( PWCON0)- PWM control register 1 ( PWCON1)- Dead time control register (DTCON)- Output overide register(OVDCOND)- Output state register (OVDCONS)- Fault configrration register (FLTCONFIG)7 cp thanh ghi (14 thanh ghi) cn li dng hiu chnh cc

thng sc bit:


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- PWM time base registers (PTMRH and PTMRL)- PWM periode registers (PTPERH and PTPERL)- PWM special event compare register ( SEVTCMPH andSEVTCMPL)

- PWM duty cycle #0 register ( PDC0H and PDC0L)- PWM duty cycle #1 register ( PDC1H and PDC1L)- PWM duty cycle #2 register ( PDC2H and PDC2L)- PWM duty cycle #3 register ( PDC3H and PDC3L)ii) Cc module chc nng:PWM module h tr nhiu ch hot ng ph hp cho yucu iu khin ng c v cc ng dng cng sut. PWM modulec tng hp t cc khi chc nng sau:

- PWM Time Base- PWM Time Base Interrrupts- PWM Period- PWM Duty Cycle- Dead Time Generators- PWM Output Overrides- PWM Fault Inputs- PWM Special Event Trigger

iii) PWM Time Base:PWM time basec cung cp 12 bit timer vi chc nngprescaler and postcaler. S khi n gin ca PWM timebase c trnh by trong hnh 3.7. PWM time base c hiuchnh thng qua 2 thanh ghi PTCON0 v PTCON1. Time basec enabled hay disabled bng vic set hay clear bit PTENtrong thanh ghi PTCON1. Ch , cp thanh ghi PTMR (PTMRH:PTMRL) s khng b clear khi bit PTEN b clear bng phnmm.PWM Time Base c 4 ch hot ng sau:- Free running mode => edge aligned PWM- Single shot mode => center aligned PWM- Continous Up/Down count mode => support electronicallycommtated motors- Continous Up/Down count mode with interrupts for doubleupdates- ch trn c la chn thng qua bit PTMOD1:PTMOD0

trong thanh ghi PTCON0.


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PWM Time Base Presclaler :C 4 la chn Presclale(chia tn) cho ng vo xung Clock avo b Timebase l: 1:1, 1:4, 1:16 hoc 1:64. Vic la chn nyc quy nh bi cc bit PTCKPS0 v PTCKPS1 trong thanh ghi

PTCON0. Cc bit ny sc xa khi xy ra mt trong cc skin sau: - C s kin ghi vo thanh ghi PTMR.- C s kin ghi vo cc thanh ghi PTCON (PTCON0 hocPTCON1).- C s kin Reset thit b.iv) Chu k xung PWM:PWM periode c nh ngha bi cp thanh ghi PTPER (PTPERH vPTPERL). PWM period c phn gii 12 bit. PTPER l

cp thanh ghi double buffered s dng set chm caPWM time base.Ni dung ca PTPER buffer c np vo thanh ghi PTPER ccthi im sau:Free running mode vSingle shot modes: thanh ghi PTMR ca v zero sau khi trng gi tr vi thanh ghi PTPER.Up/down counting mode: khi PTMR bng zero. Gi trc lutrong PTPER buffer tng np vo thanh ghi PTPER khi PWM

time base c disabled ( PTEN=0).Chu k xung PWM c thc tnh theo cc cng thc sau:

Hnh 2.6: cc cng thc tinh chu k v tn s PWMv) PWM duty cycle:PWM duty cycle c xc nh bi cc thanh ghi PDCx ( PDCxHv PDCxL). C tng cng 4 cp thanh ghi PWM duty cycle cho 4cp xung PWM.- PDC0 (PDC0L v PDC0H)- PDC1 (PDC1L v PDC1H)- PDC2 (PDC2L v PDC2H)- PDC3 (PDC3L v PDC3H)Gitr trong mi thanh ghi xc nh khong thi gian m ng raPWM tch cc.Trong ch Edge-aligned, PWM period bt u ti Q1 v kt

thc khi thanh ghi duty cycle trng vi gi tr cha trong cp


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thanh ghi PTMR.Bm PWM duty cycle (PWM Duty Cycle Register Buffer):- thanh ghi PWM duty cycle u c double buffered. Mi dutycycle block, u c thanh ghi ng vai tr bm(buffer) m c

thc truy xut bi ngi dng. Thanh ghi duty cycle bufferth hai s gi gi tr so snh vi PWM periode hin ti.- Trong ch edge-aligned PWM output, gi tr duty cycle misc update mi khi gi tr hai thanh ghi PTMR v PTPERtrng nhau. Sau PTMR sc reset nh trong hnh 3.13. Nidung ca duty cycle buffer s tng cp nht vo thanh ghiduty cycle khi PWM time base b disable.vi) B to thi gian dead time:

Trong cc b bin tn , khi cc xung PWM chi nghchiu khin cc kha cng sut pha cao v pha thp trongcng 1 nhnh, phi chn 1 khon thi gian dead time. Khonthi gian dead time lm cho ng ra PWM xung i u trngthi khng tc ng trong 1 khong thi gian ngn => trnh hintng trng dn khi kha ny ang ON cn kha kia ang OFF.Mi cp xung PWM i nghch u cmt counter 6 bit mxung, chn khon dead time vo xung PWM. Mi b to

dead time cb pht hin cnh ln v cnh xung c kt nivi b so snh duty cycle. Dead time c np vo timer khipht hin PWM cnh ln hay cnh xung. Ty vo xung PWMang cnh ln hay cnh xung, m 1 khon thi gian chuyntip c lm tr cho n khi timer m v zero.

f. Motion Feedback Module:Motion Feedback Module l mt ng dng chuyn bit dnh chovic c tn hiu chuyn ng hi tip. Cng vi module PowerControl PWM, n cung cp rt nhiu gii php iu khin dnhcho cc loi ng cin. Module ny bao gm 2 ch chcnng:- Chc nng Input Capture(IC)- Chc nng Quadrature Encoder Interface(QEI): x l xung hitip t Encoder.Trong gii hn ng dng ca lun vn ny, nn y chgiithiu v chc nng th hai QEI.

i) Khi qut v chc nng QEI ca Module Motion Feedback:


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Chc nng QEI c kh nng gii m c nhng thng tin v tr,tc cng nh s di chuyn ca ng c t Encoder hi tipv. C th QEI gm c:- ng vo QEI trong 2 ng vo pha A, B (QEA v QEB) v 1 ng

vo Index.- C cc chc nng ngt bo i chiu quay ng c, ngt cabm v tr v ngt iu khin tc - Bm xc nh v tr 16 bit.- C 2 ch d v tr: ch chun v ch chnh xc cao.- ch update v tr (x2 v x4)- Bo tc vi Postscaler kh trnh dnh cho cc ng dngo tc cao.

Tm li b QEI gm 3 thnh phn chnh: khi logic iu khinQEI, bm v tr v b postscaler dnh cho vic o tc ngc.Khi logic iu khin QEI s kim tra c cnh ln cc chn ngvo pha QEA, QEB v pht ra tn hiu tng bm v tr ln.Khi cn c th pht hin tn hiu ng vo Index (INDX), pht ratn hiu bo chiu quay v cc tn hiu o tc .Bm v tr ng vai tr nh l mt b xc nh qung ng

chuyn ng. Cc tn hiu cnh xung t ng vo QEA v QEB sc tch ly to nn tn hiu xung clock v c a vothanh ghi m POSCNT (Position Counter Register). Thanh ghiPOSCNT se tng gi tr khi c xung cnh t ng vo QEA hoc tc 2 ng vo QEA, QEB ty thuc vo vic chn ch hotng. Gi tr thanh ghi sc reset khi t n gi tr cathanh ghi MAXCNT hoc khi c xut hin mt xung Index ngvo. Nu c cho php ngt th mt s kin ngt s xy ra khiPOSCNT c reset.B Postscaler tc c chc nng l gim tn s ly mu xungtc , c s dng tng kh nng ca bm tc . Bncht l n s chia gim s lng xung mu u vo cho mtxung u ra.

Hnh 2.7: S khi module chc nng QEI

ii) Cu hnh cho chc nng QEI:

Module QEI s dng chung cc chn ng vo vi module Input


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Capture(IC) v cc chn ny chphc v cho 1 chc nng cngthi im. Ch l khi c 2 chc nng IC v QEI u cenabled th chc nng QEI sc u tin hn cn chc nngIC s tng disabled. Hot ng ca QEI c iu khin bi

thanh ghi iu khin QEICON:

Hnh 2.8: Thanh ghi iu khin QEICONBit 7: /VELM: bit chn cho tc 1 = khng s dng cho tc 0 = cho php s dng cho tc Bit 6: ERROR: bit bo li QEI

1 = bo bm b trn0 = khng trnBit 5: UP/DOWN: bit xc nh chiu quay1 = quay ti0 = quay luiBit 4:2: QEIM2:QEIM0: nhm bit chn ch QEI111 = Khng s dng110 = Cho php chy QEI ch nhn 4; POSCNT c reset

khi POSCNT = MAXCNT101 = Cho php chy QEI ch nhn 4; POSCNT c resetkhi c xung INDX ng vo.100 = Khng s dng010 = Cho php chy QEI ch nhn 2; POSCNT c resetkhi POSCNT = MAXCNT001 = Cho php chy QEI ch nhn 2; POSCNT c resetkhi c xung INDX ng vo.000 = Tt QEIiii) Cc ch QEI:Vic xc nh v tr ng c ph thuc vo hot ng m cathanh ghi POSCNT. C 2 ch update QEI xc nh v tr cang c l : QEI x2 v QEI x4.- Ch Update QEIx2 : (QEIM = 001;010) ch ny, b kim tra logic QEI chxt mi cnh ca ngvo QEA thi. C mi cnh ln v cnh xung ca tn hiu xungchn QEA s lm tng gi tr bm v tr.

- Ch Update QEIx4: (QEIM = 101;110)


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ch ny phn gii xc nh v tr s tt hn v bm vtr s tng/gim gi tr khi c cnh ln v cnh xung ca tnhiu xung c 2 chn QEA v QEB.iv) Ngt QEI:

S kin ngt QEI xy ra v c ngt IC2QEIF c set ln 1 datrn nhng tnh hung sau:Gi tr POSCNT t gi trt trong thanh ghi MAXCNT(QEIM=101 hoc 110)Gi tr POSCNT c s chuyn t FFFFh thnh 0000h (QEIM=010hoc 110)Xut hin mt xung Index chn ng vo INDX.v) Thi gian ly mu QEI

Chu k ti thiu cho php ca cc xung ng vo QEI (QEA vQEB) l 16 ln chu k lnh.Tn sm ca bm v tr, Fpos, ph thuc vo tc quayca motor RPM (vng/pht), h sm D v ch update QEI:

g. Ngt:Pic 18f4431 c nhiu ngun ngt v mt c im u tin ngt

cho php mi ngun ngt c quy nh mc u tin cao hocthp. Vecto u tin ngt cao ti 000008h v vecto u tin ngtthp ti 0000018h. Bin cu tin ngt cao s ngt bt cutin ngt thp no ang trong qu trnh thc hin.C 13 thanh ghi c s dng iu khin ch ngt. Nhngthanh ghi l:- RCON- INTCON- INTCON2- INTCON3- PIR1, PIR2, PIR3- PIE1, PIE2, PIE3- IPR1,IPR2,IPR3

Nhn chung , mi ngt c 3 bit iu khin.3 bit l:- Bit c ngt xc nh bin c ngt xy ra.- Bit enable cho php chy chng trnh chia nhanh vectoa cha ngt khi m c nhc bt ln 1.


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- Bit u tin chn mc u tin cao hoc u tin thp ( huht ngt u c bit u tin).

Hnh 2.8: S khi b Interrupt Thanh ghi INTCON:Thanh ghi INTCON c thc hoc ghi vi nhng gi tr bit chophp, bit u tin v bit ngt

Hnh 2.10: Thanh ghi INTCON

Hnh 2.11: Thanh ghi INTCON2

Hnh 2.12: Thanh ghi INTCON3

Thanh ghi PIR:Thanh ghi PIR cha cc bit c ngt ring cho mi ngt ngoi vi.V s lng ngt ngoi vi, c 3 thanh ghi iu khin ngtngoi vi.

Hnh 2.13: Thanh ghi PIR1

Hnh 2.14: Thanh ghi PIR2

Hinhg 2.15: Thanh ghi PIR3 Thanh ghi PIE:Thanh ghi PIE cha bit cho php ring mi ngt ngoi vi. Do sngt ngoi vi, c 3 thanh ghi cho php vic ngt ngoi vi. Khi

IPEN = 0, bit PEIE phi c bt cho php bt c ngt ngoivi no.

Hnh 2.16: Thanh ghi PIE1



Thanh ghi IPR:


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Thanh ghi IPR cha bit u tin cho mi ngt ngoi vi. C 3thanh ghi u tin ngt ngoi vi. S dng bit u tin i hi biIPEN phi c bt.

Hnh 2.19: Thanh ghi IPR1



Thanh ghi RCON:Thanh ghi RCON ch bit quyt nh nhng yu t ca reset

hoc l khi ng t ch qun l ngun. Thanh ghi cngcha bit cho php ngt u tin IPEN.

Hnh 2.22: Thanh ghi RCON Cc chn ngtNgt ngoi trn cc chn INT0, INT1, INT2 cnh ln hoc cnhxung. nu cc bit INTEDGx trong thanh ghi INTCON2 bng 1,ngt s pht hin cnh ln. Nu bit mc 0 th ngt khi

c cnh xung.Khi c 1 xung xut hin chn INTx, c ngt sc ln mc1, Vic ngt ny c th cm bng cch cho bit enable tngng xung mc 0, INTxIE. Trc khi c cho php li, c bongt, INTxIF phi c xa bng phn mm trong chng trnhngtMt ngt ngoi c th khi ng vi x l t ch nghnu bitINTxIE c xc lp u tin trong cc ch. Nu bit cho

php ngt ton c

c, GIE,

c b

t ln, vi x

l s

chia ccvecto ngt khi ng.

u tin ngt cho ngt ngoi 1 v 2 xc nh bi gi tr chatrong bit INT1IP (INTCON3) v INT2IP (INTCON3). Khngc bit u tin no vi ngt ngoi 0, n lun c u tin mc cao. Ngt timer 0:Trong ch 8 bit( mc nh). vic trang timer 0 sa bitTMR0IF ln 1. Trong ch 16 bit, vic trang trong 2 thanh ghiTMR0H:TMR0L a bit TMR0IF ln 1. Vic ngt c thc cho


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php hoc cm bng vic bt hoc xa bitcho php TMR0IE(INTCON). Ngt u tin cho timer 0 c quyt nh bi gitr trong TMR0IP (INTCON2) Ngt thay i portB:

Mt ng vo thay i trn portB sa bitRBIF(INTCON) ln 1. Ngt c thc cho php hoc cmbng cc bt hoc xa bit cho php RBIE(INTCON). u tinngt cho port B c quyt nh bi gi tr cha trong bit utin ngt RBIP(INTCON2).h. Cc bnh thi : Timer 0:Module timer 0 c nhng c im sau:

- C th la chn phn bm 8 bit hoc 16 bit.- C thc hoc ghi- H s prescaler dng cho bm 8bit- Ngun clock c th chn bn trong hoc bn ngoi- Ngt trn 8 bit (FFh-00h) v 16 bit (FFFFh-0000h)- Chn cnh cho ngun clock ngoi

Hnh 2.23: Thanh ghi T0CON

Bit 7 TMR0ON: Timer0 bit iu khin on/off1 = Enables Timer00 = Stops Timer0Bit 6 T016BIT: Timer0 16-bit Control bit1 = Timer0 c cu hnh nh an 8-bit timer/counter0 = Timer0 c cu hnh nh a 16-bit timer/counterBit 5 T0CS: Timer0 bit chn ngun clock cho timer1 = Transition on T0CKI pin

0 = Internal instruction cycle clock (CLKO)Bit 4 T0SE: Timer0 Source Edge Select bit1 = Increment on high-to-low transition on T0CKI pin0 = Increment on low-to-high transition on T0CKI pinBit 3 PSA: Timer0 Prescaler Assignment bit1 = Timer0 prescaler is NOT assigned. Timer0 clock inputbypasses prescaler.0 = Timer0 prescaler is assigned. Timer0 clock input comes fromprescaler output.Bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits


16/20

111 =1:256 prescale value110 =1:128 prescale value101 =1:64 prescale value100 =1:32 prescale value

011 =1:16 prescale value010 =1:8 prescale value001 =1:4 prescale value000 =1:2 prescale valueCh 8 bit:Hot ng ch ny khi bit T0CON =1.v c ngt s btkhi timer trn t ff->00h.Ch 16 bit:

Hot ng ch ny khi bit T0CON=0 v c ngt s btkhi timer trn t ffffh->0000h. ch ny dng hai cp thanhghi l TMR0H v TMR0L ni dung ca timer sc cp nhtthng qua hai cp thanh ghi ny. Timer 1:C cc chc nng sau:- Timer/counter 16 bit- C thc hoc xo c

- La chn ngun xung clock bn ngoi hoc bn trong- Ngt trn t FFFFh->0000H- Thanh ghi iu khin l T1CON

Hnh 2.24: Thanh ghi T1CONBit 7 RD16: 16-bit bit cho chep write/read1 = Enables register read/write of TImer1 in one 16-bitoperation0 = Enables register read/write of Timer1 in two 8-bitoperationsBit 6 T1RUN: Timer1 System Clock Status bit1 = System clock is derived from Timer1 oscillator0 = System clock is derived from another sourceBit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Selectbits11 =1:8 Prescale value10 =1:4 Prescale value

01 =1:2 Prescale value


17/20

00 =1:1 Prescale valueBit 3 T1OSCEN: Timer1 bit cho phep Oscillator1 = Timer1 oscillator is enabled0 = Timer1 oscillator is shut-off

Bit 2 T1SYNC: Timer1 External Clock Input SynchronizationSelect bitWhen TMR1CS = 1 (External Clock):1 = Do not synchronize external clock input0 = Synchronize external clock inputBit 1 TMR1CS: Timer1 Clock Source Select bit1 = External clock from pin RC0/T1OSO/T1CKI (on the risingedge)

0 = Internal clock (FOSC/4)Bit 0 TMR1ON: Timer1 On bit1 = Enables Timer10 = Stops Timer1 Timer 2:- Hot ng ch 8 bit- Counter c thc hoc ghi- Phn mm c th lp trnh bng prescale

- Phn mm c th lp trnh bng postscale

Hnh 2.25: Thanh ghi T2CONBit 7 Unimplemented: Read as 0Bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits0000 = 1:1 Postscale0001 =1:2 Postscale1111 =1:16 PostscaleBit 2 TMR2ON: Timer2 On bit1 = Timer2 is on0 = Timer2 is offBit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits00 = Prescaler is 101 = Prescaler is 41x = Prescaler is 16Ngt timer2: gi tr ca TMP2 sc so snh vi PR2 khi gi trca hai thanh ghi bng nhau c ngt TMR2IF s bt ln cho n

khi c xo bng phn mm


18/20

i. Module I2C:L cng cy cho ch clave,v cung cp ngt trn haibit START v STOP trong phn cng d dng thc thi trn

ch master.Hai chn c s dng chuyn d liu:SDI v SDA pin.Vngi dng phi cu hnh hai chn ny l output hay inputthng qua hai thanh ghi TRISC v TRISD.Khi s dng i2c giao tip th hai chn ny phi c ni ln5v vi in tr ko ln,v gi tri in tr ny ph thuc vo tc boud ca pic.Ch clave:

Trong ch ny hai chn SCL SDA phi c cu hnh nh lng vo (TRISC hoc TRISDc set).khi a chkhphoc d liu chuyn sau khi address match c nhn,tngphn cng s pht xung ACK v load v gi tr trong thanh ghiSSPBUF .C hai iu kin l nguyn nhn module SSP khng pht ACKxung:- Buffer full bit BF c set sau khi s chuyn c nhn

- Bit bo trn SSPOV (SSPCON) c set sau khi s chuync nhnTrong trng hp ny ,thanh ghi SSPSR gi tr khng load voSSPBUF nhng bit SSPIF c setTrnh t hot ng ny cho 10 bit_address:1. Nhn byte cao ca a ch(bits SSPIF,BF,UA c set2. update thanh ghi SSPADD vi byte th hai caaddress(slow)_bit UA clear3. c thanh ghi SSPBUF v clear c SSPIF4. Nhn byte th hai ca a ch(slow) SSPIF,BF UA c set5. Update thanh ghi SSPADD vi byte cao ca ADDRESS6. c gi tr thanh ghi SSPBUF xoa bit BF v xo SSPIF7. Nhn lai iu kin start8. Nhn byte th 1 (high) ca address SSPIF,BF c set9. c thanh ghi SSPBUF clear bit SSPIF,BF.Ch master:Vn hnh ch ny s dng ngt khi pht hin iu kin trn

hai bit start v stop v trong ch ny hai chn SCL SDA c


19/20

cu hnh nh ng output

Hnh 2.26: Thanh ghi SSPSTATBit7: SMP bit ny phi c xo trong ch i2cBit6: CKE bit ny cng phi c xo trong ch i2cBit5: D/A data/address bit chvn hnh ch i2c1 = chnh xc rng byte cui cng c nhn l hoc chuyn ldata0 = chnh xc rng byte cui cng c nhn l hoc chuyn laddressBit4: P stop bit chvn hnh ch i2c, bit ny c xo khimodule ssp c disable hoc khi bit start c nhn thy.V

SSPEN c xo1 = bit stop c pht hin0 = bit stop khng c nhn thyBit3: S start bit chvn hnh trong ch i2c1 = bit start c nhn ra0 = bit start khng c nhn raBit 2: R/W bit thng tin v read v write(chvn hnh trong ch i2c)

1 = read0 = writeBit 1: UA bit update a ch1 = chnh sc rng ngi dng cn update address trong thanhghi SSPADD0 = address khng cn updateBit 0: BF trng thi bufferTrong ch nhn:1 = nhn hong thnh SSPBUF y0 = nhn khng hon thnh SSPBUF cha yTrong ch chuyn1 = ang chuyn SSPBUF y0 = chuyn hon thnh,SSPBUF trng

Hnh 2.27: Thanh ghi SSPCONBit 7:WCOL1 = thanh ghi SSPBUF c vit

0 = khng c va chm


20/20

Bit 6: SSPOV bit nhn bo trn1 = 1 byte c nhn trong khi vn gi data trc,trong trnghp trn data in sspsr s b mt0 = khng b trn

Bit 5: SSPEN bit cho php truyn ng b1 = cho php port ni tip,cu hnh chn SDA SCL nh port nitip0 = diable port ni tipBit 3-0:bit chn ch truyn port ni tip ng b0000= SPI master mode,Fosc/40001= SPI master mode,Fosc/160010= SPI master mode,Fosc/64

0011= SPI master mode,clock=TMR2 output/20100= SPI sclave mode,clock=SCK pin,SS pin control enable0101= SPI sclave mode,clock=SCK pic,SS pin control disable0110= I2C sclave mode 7-bit address0111=I2C sclave mode 10-bit address1011=i2c firmware controlled master mode1110=i2c sclave mode 7 bit address vi start stop enabled bit1111=i2c sclave mode 10 bit address vi start stop enabled bit

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