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126 / MAPLD2004Lake3 Techniques for Long Term Reliability Analysis Accelerated burn-in: unprogrammed devices –Chamber temperature: 125ºC –Stress pattern: dynamic, 1MHz, production unprogrammed device test –Duration: 16 hours –Stress voltages: 4.1V I/O; 3.2V core –Test: room temp unprogrammed electrical test, read and record Low temperature operating life (LTOL): programmed devices –Chamber temperature: -65ºC –Stress pattern: dynamic, 1MHz, 10K vectors, high toggle rate –Duration: 500 hours (read point at 24hrs, 168hrs) –Stress voltages: 3.3V I/O, 2.75V core –Test: 3 temp electrical test, read and record data
Citation preview
126 / MAPLD2004Lake 1
Life Test Effects on the Aeroflex ViaLink™ FPGA
Ronald LakeAeroflex Colorado Springs
126 / MAPLD2004Lake 2
Purpose of Investigation
• Industry is currently evaluating long term reliability of antifuse products
• Aeroflex is proactively reviewing long term reliability of RadHard Eclipse ViaLink™ products– Burn-in – Low Temperature Operating Life (LTOL)– High Temperature Operating Life (HTOL)
• Accelerated Voltage• Monitor
126 / MAPLD2004Lake 3
Techniques for Long Term Reliability Analysis
• Accelerated burn-in: unprogrammed devices– Chamber temperature: 125ºC– Stress pattern: dynamic, 1MHz, production unprogrammed device test– Duration: 16 hours– Stress voltages: 4.1V I/O; 3.2V core – Test: room temp unprogrammed electrical test, read and record
• Low temperature operating life (LTOL): programmed devices– Chamber temperature: -65ºC– Stress pattern: dynamic, 1MHz, 10K vectors, high toggle rate– Duration: 500 hours (read point at 24hrs, 168hrs)– Stress voltages: 3.3V I/O, 2.75V core– Test: 3 temp electrical test, read and record data
126 / MAPLD2004Lake 4
Techniques for Long Term Reliability Analysis
• High temperature operating life (HTOL): programmed devices– Accelerated HTOL
• Chamber temperature: 125ºC• Stress pattern: dynamic, 10K vectors, high toggle rate• Duration: 500 hours (read point at 96hrs)• Stress voltages: 4.1V I/O, 3.2V core• Test: 3 temp electrical test, read and record data
– HTOL monitor - replicates customer use conditions• Chamber temperature: 125ºC• Stress pattern: dynamic, 10K vectors, high toggle rate• Duration: 1000 hours (read point at 500hrs)• Stress voltages: 3.3V I/O, 2.5V core• Test: 3 temp electrical test, read and record data
126 / MAPLD2004Lake 5
Stress Voltage Margin
• Operating voltage (functional operation)– 2.7 V core– 3.6 V I/O
• Absolute Maximum– 3.6 V Core– 4.6 V I/O
• Aeroflex Accelerated Voltage Stress Results– QL6325 used for evaluation (in plastic pkg)
• 4.7 V Core (pass ET)– 4.9 V Core (Fails ET)
• 5.5 V I/O (pass ET)– 6.0 V I/O (Fails ET)
– No Auto Programming of ViaLinks Detected• Un-programmed Devices used for this evaluation
126 / MAPLD2004Lake 6
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
A
B
C
D
A
B
C
D
I843
INPAD_25UM*
I798
NAND_16
nand_16_i
q11_0q11_1
q11_10q11_11q11_12q11_13q11_14
q11_2q11_3q11_4q11_5q11_6q11_7q11_8q11_9
I800
SHIFT_REGclk
resetset
si
so
I832
SHIFT_REG_16_2
sr_clk
sr_d1_isr_d2_i
sr_resetsr_set a225
f225
qa225qb225
I788
REG64X8
addr[5:0]
clk
d_in[7:0]
resetset
wr_e q_out[7:0]
. 25um
Q
CLR
D
I775
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I776
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I777
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I778
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I779
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I780
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I781
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I782
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I727
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I728
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I729
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I730
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I731
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I732
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I733
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I734
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I735
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I736
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I737
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I738
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I739
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I740
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I741
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I742
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I743
OUTPADFF_25UM
*
. 25um
Q
CLR
D
I744
OUTPADFF_25UM
*
I726
RAMTEST3072X18
w_clk
w_ra[11:0]
wd[17:0]
we
rd[17:0]
I783
SHIFT_REG_16
sr_clk
sr_d1_isr_d2_i
sr_resetsr_set a360
f360
n360
o360qa360
qb360
I720
SHIFT_REG_DRAW
clear
clk
preset
sr_in sr_out
. 25um
Q
CLREN
D
I745
INPADFF_25UM
*
. 25um
Q
CLREN
D
I746
INPADFF_25UM
*
. 25um
Q
CLREN
D
I747
INPADFF_25UM
*
. 25um
Q
CLREN
D
I748
INPADFF_25UM
*
. 25um
Q
CLREN
D
I749
INPADFF_25UM
*
. 25um
Q
CLREN
D
I750
INPADFF_25UM
*
. 25um
Q
CLREN
D
I751
INPADFF_25UM
*
. 25um
Q
CLREN
D
I752
INPADFF_25UM
*
. 25um
Q
CLREN
D
I753
INPADFF_25UM
*
. 25um
Q
CLREN
D
I754
INPADFF_25UM
*
. 25um
Q
CLREN
D
I755
INPADFF_25UM
*
. 25um
Q
CLREN
D
I756
INPADFF_25UM
*
. 25um
Q
CLREN
D
I757
INPADFF_25UM
*
. 25um
Q
CLREN
D
I758
INPADFF_25UM
*
. 25um
Q
CLREN
D
I759
INPADFF_25UM
*
. 25um
Q
CLREN
D
I760
INPADFF_25UM
*
. 25um
Q
CLREN
D
I761
INPADFF_25UM
*
. 25um
Q
CLREN
D
I762
INPADFF_25UM
*
. 25um
Q
CLREN
D
I763
INPADFF_25UM
*
. 25um
Q
CLREN
D
I764
INPADFF_25UM
*
. 25um
Q
CLREN
D
I765
INPADFF_25UM
*
. 25um
Q
CLREN
D
I766
INPADFF_25UM
*
. 25um
Q
CLREN
D
I767
INPADFF_25UM
*
. 25um
Q
CLREN
D
I768
INPADFF_25UM
*
. 25um
Q
CLREN
D
I769
INPADFF_25UM
*
. 25um
Q
CLREN
D
I770
INPADFF_25UM
*
. 25um
Q
CLREN
D
I771
INPADFF_25UM
*
. 25um
Q
CLREN
D
I772
INPADFF_25UM
*
. 25um
Q
CLREN
D
I773
INPADFF_25UM
*
. 25um
Q
CLREN
D
I774
INPADFF_25UM
*
. 25um
Q
CLREN
D
I539
INPADFF_25UM
*
. 25um
Q
CLREN
D
I669
INPADFF_25UM
*
. 25um
Q
CLREN
D
I670
INPADFF_25UM
*
. 25um
Q
CLREN
D
I671
INPADFF_25UM
*
. 25um
Q
CLREN
D
I672
INPADFF_25UM
*
. 25um
Q
CLREN
D
I673
INPADFF_25UM
*
. 25um
Q
CLREN
D
I674
INPADFF_25UM
*
. 25um
Q
CLREN
D
I675
INPADFF_25UM
*
. 25um
Q
CLREN
D
I533
INPADFF_25UM
*
. 25um
Q
CLREN
D
I534
INPADFF_25UM
*
. 25um
Q
CLREN
D
I676
INPADFF_25UM
*
. 25um
Q
CLREN
D
I677
INPADFF_25UM
*
. 25um
Q
CLREN
D
I678
INPADFF_25UM
*
. 25um
Q
CLREN
D
I679
INPADFF_25UM
*
I529
INV_CHAINinv_chn_in1inv_chn_in2inv_chn_in3
inv_chn_o
CKPAD_25um
I695*
CKPAD_25um
I833*
CKPAD_25um
I801*
CKPAD_25um
I543*
CKPAD_25um
I666*
CKPAD_25um
I558*
CKPAD_25um
I784*
CKPAD_25um
I785*
CKPAD_25um
I320*
HDPAD_25um
I805*
HDPAD_25um
I786*
HDPAD_25um
I787*
HDPAD_25um
I834*
HDPAD_25um
I835*
HDPAD_25um
I836*
HDPAD_25um
I837*
HDPAD_25um
I838*
HDPAD_25um
I802*
HDPAD_25um
I803*
HDPAD_25um
I804*
HDPAD_25um
I824*
HDPAD_25um
I537*
HDPAD_25um
I689*
HDPAD_25um
I667*
HDPAD_25um
I717*
I811
OUTPAD_25UM
*
I812
OUTPAD_25UM
*
I813
OUTPAD_25UM
*
I814
OUTPAD_25UM
*
I815
OUTPAD_25UM
*
I816
OUTPAD_25UM
*
I817
OUTPAD_25UM
*
I818
OUTPAD_25UM
*
I819
OUTPAD_25UM
*
I820
OUTPAD_25UM
*
I821
OUTPAD_25UM
*
I822
OUTPAD_25UM
*
I823
OUTPAD_25UM
*
I809
OUTPAD_25UM
*
I810
OUTPAD_25UM
*
I839
OUTPAD_25UM
*
I840
OUTPAD_25UM
*
I841
OUTPAD_25UM
*
I842
OUTPAD_25UM
*
I830
OUTPAD_25UM
*
I831
OUTPAD_25UM
*
I696
OUTPAD_25UM
*
I808
OUTPAD_25UM
*
I532
OUTPAD_25UM
*
I697
OUTPAD_25UM
*
I474
OUTPAD_25UM
*
I475
OUTPAD_25UM
*
I703
OUTPAD_25UM
*
QuickLogicCorporation
1277 Orleans DriveSunnyvale, CA 94089
QL6325RELCKT5
4/1/2004 11:29:28 AM
QL6325RELCKT5
.
iclkextclk iclk w_gset
w_gclrw_ram_weinv_ch_i1 w_wr_eiclkgclr w_gclr
inv_ch_i2 inv_ch_o1
gset w_gset
w_r
eg_q
[7:0
]
inv_ch_i3
w_r
eg_a
ddr[5
:0]
w_r
am_a
ddr[1
1:0]
w_r
am_d
[17:
0]
w_r
am_q
[17:
0]
w_reg_q[7]outreg_clk w_outreg_clk w_reg_q[6]w_reg_q[5]w_ram_d[17] w_ram_q[17]
w_r
eg_d
[7:0
]
w_ram_addr[11] w_reg_q[4]w_ram_d[16] w_ram_q[16] w_reg_addr[5]w_ram_addr[10] w_reg_q[3]w_ram_d[15] w_ram_q[15] w_reg_addr[4]r_wr_e w_wr_e w_ram_addr[9] w_reg_q[2]w_ram_d[14] w_ram_q[14] w_reg_addr[3]w_ram_addr[8] w_reg_q[1]w_ram_d[13] w_ram_q[13] w_reg_addr[2]w_ram_addr[7] w_reg_q[0]w_ram_d[12] w_ram_q[12] w_reg_addr[1]w_ram_addr[6] w_ram_d[11] w_ram_q[11] w_reg_addr[0]w_ram_addr[5]inreg_clk w_inreg_clk w_ram_d[10] w_ram_q[10]w_ram_addr[4] w_ram_d[9] w_ram_q[9] w_reg_d[7]w_ram_addr[3] w_ram_d[8] w_ram_q[8] w_reg_d[6]w_ram_addr[2] w_ram_d[7] w_ram_q[7] w_reg_d[5]w_ram_addr[1] w_ram_d[6] w_ram_q[6] w_reg_d[4]w_ram_addr[0]ram_we w_ram_we w_ram_d[5] w_ram_q[5] w_reg_d[3]w_ram_d[4] w_ram_q[4] w_reg_d[2]w_ram_d[3] w_ram_q[3] w_reg_d[1]w_ram_d[2] w_ram_q[2] w_reg_d[0]
inreg_en w_inreg_en nand16_o0 w_ram_d[1] w_ram_q[1]w_ram_d[0] w_ram_q[0]
nand16_o1ram_d[17]
nand16_o2 w_ram_d[17]w_inreg_clknand16_o3 w_inreg_en
w_gclrnand16_o4
ram_d[16]nand16_o5w_ram_d[16]
nand16_o6 w_inreg_clkw_inreg_en reg_addr[5]
nand16_o7 w_gclrnand_16_i w_reg_addr[5]w_inreg_clknand16_o8 ram_d[15] w_inreg_en
w_ram_d[15] w_gclrnand16_o9 w_inreg_clkw_inreg_ennand16_o10 w_gclr reg_addr[4]
nand16_o11 w_reg_addr[4]ram_d[14] w_inreg_clknand16_o12 w_ram_d[14] w_inreg_en
w_inreg_clk w_gclrnand16_o13 w_inreg_en
w_gclrnand16_o14 reg_addr[3]
ram_d[13] w_reg_addr[3]w_ram_d[13] w_ram_q[17] ram_q[17] w_inreg_clk
w_inreg_clk w_outreg_clk w_inreg_enw_inreg_en w_gclr
w_gclr w_gclr
ram_d[12] w_ram_q[16] ram_q[16] reg_addr[2]w_outreg_clkw_ram_d[12] w_reg_addr[2]
w_inreg_clk w_inreg_clkw_gclrw_inreg_en w_inreg_enw_gclr w_gclrw_ram_q[15] ram_q[15]
ram_addr[11] w_outreg_clkram_d[11]w_ram_addr[11] reg_addr[1]w_ram_d[11] w_gclrw_inreg_clk w_inreg_clk w_reg_addr[1]w_inreg_en w_inreg_en w_ram_q[14] ram_q[14] w_inreg_clkw_gclr w_gclr w_outreg_clk w_inreg_en
w_gclrram_addr[10] ram_d[10] w_gclr w_reg_q[7] reg_q[7]w_ram_addr[10] w_ram_d[10] w_outreg_clkw_inreg_clk w_ram_q[13] ram_q[13]w_gset w_inreg_clk reg_addr[0]w_inreg_en w_outreg_clkw_gclr w_inreg_en w_gclrsr_d_so w_gclr w_reg_addr[0]sr_d_si w_gclr w_gclr w_inreg_clkiclk ram_addr[9] w_inreg_enram_d[9] w_ram_q[12] ram_q[12] w_gclrw_ram_addr[9] w_ram_d[9] w_outreg_clkw_inreg_clk w_inreg_clk w_reg_q[6] reg_q[6]w_inreg_en w_inreg_en w_gclr reg_d[7] w_outreg_clkw_gclr w_gclr w_reg_d[7]w_ram_q[11] ram_q[11] w_gclrram_addr[8] w_inreg_clkram_d[8] w_outreg_clk w_inreg_enw_ram_addr[8] w_ram_d[8] w_gclrsr_16_a360 w_inreg_clk w_gclrw_inreg_clksr_16_set w_sr_16_set w_inreg_en w_inreg_enw_gclr w_ram_q[10] ram_q[10]w_gclr reg_d[6] w_reg_q[5] reg_q[5]sr_16_o360 w_outreg_clk w_outreg_clkram_addr[7] w_reg_d[6]sr_16_rst w_sr_16_rst ram_d[7] w_gclr w_inreg_clkw_ram_addr[7] w_gclrw_sr_16_set w_ram_d[7] w_inreg_ensr_16_qa360 w_inreg_clkw_sr_16_rst w_inreg_clk w_ram_q[9] ram_q[9] w_gclrw_inreg_enw_sr_16_d w_inreg_en w_outreg_clksr_16_d w_sr_16_d w_gclrw_sr_16_d w_gclrsr_16_n360w_sr_16_clk w_gclr reg_d[5]ram_addr[6] ram_d[6] w_reg_d[5] w_reg_q[4] reg_q[4]sr_16_clk w_sr_16_clk w_ram_addr[6] w_ram_q[8] ram_q[8]sr_16_qb360 w_ram_d[6] w_inreg_clk w_outreg_clkw_inreg_clk w_outreg_clkw_inreg_clk w_inreg_enw_inreg_en w_inreg_en w_gclr w_gclrw_gclr w_gclrsr_16_f360 w_gclr
ram_addr[5] w_ram_q[7] ram_q[7]ram_d[5] reg_d[4]w_outreg_clkw_ram_addr[5] w_ram_d[5] w_reg_d[4]w_inreg_clk w_inreg_clk w_gclr w_inreg_clk w_reg_q[3] reg_q[3]w_inreg_en w_inreg_en w_inreg_en w_outreg_clksr_16_2_set w_sr_16_2_set sr_16_2_a210 w_gclr w_gclr w_ram_q[6] ram_q[6] w_gclrw_outreg_clk w_gclrram_addr[4] ram_d[4]sr_16_2_rst w_sr_16_2_rst sr_16_2_qa210w_sr_16_2_set w_ram_addr[4] w_gclrw_ram_d[4] reg_d[3]w_sr_16_2_rst w_inreg_clk w_inreg_clkw_sr_16_2_d1 w_inreg_en w_ram_q[5] ram_q[5] w_reg_d[3]sr_16_2_d1 w_sr_16_2_d1 sr_16_2_qb210 w_inreg_enw_sr_16_2_d2 w_gclr w_outreg_clk w_inreg_clkw_gclrw_sr_16_2_clk w_inreg_en w_reg_q[2] reg_q[2]
ram_addr[3] w_gclr w_gclr w_outreg_clksr_16_2_d2 w_sr_16_2_d2 sr_16_2_f210 ram_d[3]w_ram_addr[3] w_ram_d[3] w_ram_q[4] ram_q[4] w_gclrw_inreg_clk w_inreg_clk w_outreg_clksr_16_2_clk w_sr_16_2_clk w_inreg_en reg_d[2]w_inreg_enw_gclr w_gclr w_gclr w_reg_d[2]
w_inreg_clkram_addr[2] ram_d[2] w_ram_q[3] ram_q[3] w_inreg_enw_ram_addr[2] w_outreg_clk w_gclr w_reg_q[1] reg_q[1]w_ram_d[2]w_inreg_clk w_outreg_clkw_inreg_clkw_inreg_en w_gclrw_inreg_ensr_v_clk w_sr_v_clk w_gclr reg_d[1] w_gclrw_gclr w_ram_q[2] ram_q[2] w_reg_d[1]ram_addr[1] w_outreg_clksr_v_set w_sr_v_set ram_d[1] w_inreg_clkw_sr_v_clk w_ram_addr[1] w_inreg_enw_sr_v_set w_ram_d[1] w_gclrsr_v_so1 w_inreg_clk w_gclrsr_v_rst w_sr_v_rst w_sr_v_rst w_inreg_clkw_inreg_en w_reg_q[0] reg_q[0]w_sr_v_si w_inreg_en w_ram_q[1] ram_q[1]w_gclr w_outreg_clkw_gclr w_outreg_clksr_v_si w_sr_v_si reg_d[0]
ram_addr[0] w_gclrram_d[0] w_gclr w_reg_d[0]w_ram_addr[0] w_inreg_clkw_ram_d[0]w_inreg_clk w_ram_q[0] ram_q[0] w_inreg_enw_inreg_clkw_inreg_en w_outreg_clk w_gclrw_inreg_enw_gclr w_gclr w_gclr
Combinatorial Blocks for Fanout Analysis
Registered I/O
High Drive Input ControlsCombinatorial Paths with Low Fanout
Synchronous Register FileSRAM Containing all 24 Blocks
Synchronous Fanout Paths
Total Dose Timing Analysis
Reliability Design for Life Test Effects
126 / MAPLD2004Lake 7
Reliability Design for ViaLink™ Lifetest
• Goal: Verify long term reliability of programmed and un-programmed vialinks with HTOL and LTOL tests
• Design– Create worst case design, beyond customer’s ability– Use all FPGA logic, memory and I/O resources– Use all wiring types, with associated ViaLinks™
• Worst case design constraints– Force fan-out = 16 (user restricted to fan-out=10)– Force fixed placement to drive long interconnects– Force use of worst case ViaLinks™ with fixed placement– Disable automatic buffering– Use design structures which may be toggled efficiently
during life test
126 / MAPLD2004Lake 8
Resource Utilization for Reliability DesignUtilized cells (preplacement) 1533 of 1536 (99.8)
Utilized cells (postplacement) 1514 of 1536 (98.6)
Utilized Logic cell Frags (preplacement) 7195 of 9216 (78.1)
Utilized Logic cell Frags (postplacement) 7195 of 9216 (78.1)
Utilized Fragment A 1164
Utilized Fragment F 1302
Utilized Fragment O 1393
Utilized Fragment N 1056
IO control cells 16 of 16 (100.0)
Clock only cells 9 of 9 (100.0)
Bi directional cells 99 of 99 (100.0)
RAM cells 24 of 24 (100.0)
PLL cells 0 of 4 (0.0)
Flip-Flop of IO cells 70 of 316 (22.2)
1st Flip-Flop of Logic cells 1097 of 1536 (71.4)
2nd Flip-Flop of Logic cells 1183 of 1536 (77.0)
Routing resources 64210 of 119431 (53.8)
ViaLink resources 57098 of 3213992 (1.8)
126 / MAPLD2004Lake 9
Reliability Design Utilization With Customer Design FlowUtilized cells (preplacement) 1533 of 1536 (99.8)
Utilized cells (postplacement) 1536 of 1536 (100.0)
Utilized Logic cell Frags (preplacement) 8033 of 9216 (87.2)
Utilized Logic cell Frags (postplacement) 8288 of 9216 (89.9)
Utilized Fragment A 1536
Utilized Fragment F 1534
Utilized Fragment O 1447
Utilized Fragment N 1491
IO control cells 16 of 16 (100.0)
Clock only cells 9 of 9 (100.0)
Bi directional cells 99 of 99 (100.0)
RAM cells 24 of 24 (100.0)
PLL cells 0 of 4 (0.0)
Flip-Flop of IO cells 70 of 316 (22.2)
1st Flip-Flop of Logic cells 1097 of 1536 (71.4)
2nd Flip-Flop of Logic cells 1183 of 1536 (77.0)
Routing resources 65777 of 119431 (55.1)
ViaLink resources 57520 of 3213992 (1.8)
126 / MAPLD2004Lake 10
Reliability Design: Shift Register Details
I48
SUPER_LOGIC
I32
SUPER_LOGIC
I33
SUPER_LOGIC
I34
SUPER_LOGIC
I35
SUPER_LOGIC
I36
SUPER_LOGIC
I37
SUPER_LOGIC
I38
SUPER_LOGIC
I39
SUPER_LOGIC
I40
SUPER_LOGIC
I41
SUPER_LOGIC
I42
SUPER_LOGIC
I43
SUPER_LOGIC
I44
SUPER_LOGIC
I45
SUPER_LOGIC
I46
SUPER_LOGIC
I47
SUPER_LOGIC
I49
SUPER_LOGIC
I50
SUPER_LOGIC
I51
SUPER_LOGIC
I52
SUPER_LOGIC
I53
SUPER_LOGIC
I54
SUPER_LOGIC
.25um
.25um
QR
S
F1
0
10
QR
S
0 1
A
10
1
1
0
NE
D
1 0
0
O
MC
B
I55
SUPER_LOGIC
.25um
.25um
QR
S
F1
0
10
QR
S
0 1
A
10
1
1
0
NE
D
1 0
0
O
MC
B
I56
SUPER_LOGIC
I57
SUPER_LOGIC
I58
SUPER_LOGIC
I59
SUPER_LOGIC
I60
SUPER_LOGIC
I61
SUPER_LOGIC
SHIFT_REG_16
4/1/2004 11:29:14 AM
SHIFT_REG_16
.
sr_set
sr_reset
a8
o8sr_d1_i
qa1 qa2 qa3 qa4 qa5 qa6 qa7 qa8
n8qb1 qb2 qb3 qb4 qb5 qb6 qb7 qb8
f8
sr_d2_i
sr_clk
126 / MAPLD2004Lake 11
Reliability Design: Combinatorial Blocks Detail
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0
NAND2i0NAND2i0
NAND_16
3/17/2004 10:03:24 AM
NAND_16
NAND_16
q11_0
q11_1
q11_2
q11_3
nand
_16_
i
q11_4
q11_5
q11_6
q11_7
q11_8
q11_9
q11_10
q11_11
q11_12
q11_13
q11_14
126 / MAPLD2004Lake 12
Reliability Design: Fixed Worst Case Placement Constraints
126 / MAPLD2004Lake 13
Reliability Design: Short Path Placement
126 / MAPLD2004Lake 14
Reliability Design: Combinatorial Fan-out
126 / MAPLD2004Lake 15
Reliability Design: Worst Case Fan-out
126 / MAPLD2004Lake 16
Reliability Design: LTOL / HTOL I/O Overshoot and Undershoot
126 / MAPLD2004Lake 17
Reliability Design: Expanded View LTOL / HTOL I/O Overshoot
126 / MAPLD2004Lake 18
LTOL Current Deltas
AVG STDEV MAX MIN Temp Test0.30% 0.0156 5.30% -1.50% 25 QIDD0.45% 0.012893 3.87% -1.12% 25 QIDD0.05% 0.000388 0.11% -0.03% 25 AIDD_1MHZ
-0.02% 0.001744 0.11% -0.85% 25 AIDD_5MHZ0.02% 0.00176 0.45% -0.44% 25 AIDD_10MHZ0.12% 0.000348 0.26% 0.08% 25 AIDD_20MHZ
Current Measurements for HTOL / LTOL Material
126 / MAPLD2004Lake 19
Summary
• Worst case design created to evaluate long term ViaLink™ reliability
• Programmed and un-programmed ViaLink’s™ evaluated through low temperature operating life (LTOL) and accelerated high temperature operating life (HTOL)
• Data to date shows no ViaLink™ damage during lifetest– No functional failures– No increase in quiescent or active current
