DesignCon 2013

Power/Ground bump Optimization Technique on Early Design Stage

Youngsoo Lee, Samsung Electronics Inc. [sontag.lee@samsung.com, 82-31-8000-2475] Dongyoun Yi, Samsung Electronics Inc. [dongyoun.yi@samsung.com]

Abstract This paper demonstrates on-chip power/ground bump optimization technique in the early chip design stage considering IR/DvD effect. By providing special functions; power map creation and design prototyping with the same level of accuracy in the post sign-off, the proposed early stage power/ground bump optimization technique enables designers to predict a power noise and determine an optimal power and ground bump topology on a proper point when RDL and package routing specification should be decided. This paper introduces the overall procedure of the proposed method. The comparison results on the simulation level between before and after of applying the proposed method are held as well. In particular, the paper shows how the proposed optimization method is validated from silicon to system level and the comparison results on co-analysis covering a chip, package and board.

Author(s) Biography Youngsoo Lee is in charge of on-chip power integrity & reliability as one of technical leader in the Design Technology team at Samsung Electronics. She received her Bachelor degree from Department of Computer Engineering in Pusan National University, South Korea, in 2000. In 2002, she earned her Master degree from the same university as BS and joined Samsung Electronics; she had worked as a hardware emulator verification engineer by 2005. She first started on-chip power integrity work in 2005, and since then, has been playing a leading role in development Samsung power integrity flow from 90nm to 28nm process. Currently, she is working to make a power integrity flow for advanced process nodes such as 20nm and 14nm and extending her research area to a package and off-chip power integrity solution.

Dongyoun Yi received his BS degree in Computer Science and Engineering from Seoul National University, South Korea in 2010 and joined Samsung Electronics as an assistant engineer, playing a significant role in chip power integrity related design methodology. In particular, he has been developing a key component of Samsung's early-stage analysis methodology.

Introduction A flip chip design brings designers many benefits like reduced inductance for signal, power and ground network, die and package shrink. Consequently, most of key industries are widely adopting a flip chip packaging for a chip needs high frequency and large amount of power. In spite of those advantages, a flip chip design’s the relatively higher cost compared to a wire bond design is still challenging. Therefore, cost-effective flip chip design becomes one of important factors in determining chip’s price competitiveness. As one of the remedy for cost reduction in a flip chip design, this paper introduces a power and ground bump optimization technique on chip insuring no drawback due to power noise as well as reducing PCB and probing test cost.

Background Obtaining an optimal P/G bump topology is not simple, since the RDL (Redistribution Layer) routing and package spec are set by a bump placement, which is largely done in the early stage of chip development. In the early design stage, largely it is hard to get accurate power consumption and physical design information, which are indispensable requisites for P/G bump topology. Even if there is meaningful power consumption, performing power assignment as fine as post sign-off is impossible since even current distribution of block level is only available. That even current distribution can not reflect hot spot current crowding; largely lead to more optimistic result. Therefore, most commonly used way is to place P/G bumps with a minimum pitch which wafer bumping processes allow. As for a designer, bump placement with a minimum pitch regardless of chip constraints will be easier and safer in terms of power integrity. This is because the more P/G bumps exist, the smaller failures due to power noise are getting. Figure 1, however, describes such an unconditional placement as many P/G bump as possible always does not avoid power noise issues. In a certain part of chip with hot-spot current much higher than neighborhood like Figure 1, no matter how designers put as many P/G bump as possible with minimum bump pitch, it may be impossible to meet IR and DvD (Dynamic Voltage Drop) limit. In such a particular case, designers need to use a different method like placing more decap cells around the area or dispersing the cells causing high peak current.

Figure 1: The hot spot dynamic voltage drop area due to crowding of cell instances with much higher current than neighborhood

In another case, the outer area of a chip is not able to have enough P/G bumps than the inner of a chip due to routing constraints by the RDL and package like Figure 2(a). The left top area of Figure 2(a) with higher IR drop due to insufficient P/G bumps might not be covered by using a minimum bump pitch. It can be relieved by adding more P/G bumps like Figure 2(b). The cases stated on the above show how inefficient the existing P/G bump placement method is and some pitfalls due to an unbalanced bump placement in the traditional method. Currently, however, there is no way to determine an optimal P/G bump placement except using a minimum pitch which wafer process allows or based on previous experiences. Deciding design’s P/G bump placement with only block level lumped power budget and obscure physical information may bring risk of a potential power noise. Moreover, using excessive P/G bumps lead to rising in production cost, in particular, manufacturing cost of package/PCB and probing card for post silicon test. For these reasons, we had undertaken extensive studies to invent a method enabling designers to have an optimal P/G bump topology in the early design stage making up for the demerits in the conventional method as well as ensuring that power-noise risks are mitigated.

Overall Flow of P/G Bump Optimization Technique in the Early Stage Prior to apply the P/G bump optimization technique, we did more extra tuning work first to have a correlated early stage environment with the result of a post sign-off. Figure 3 shows how compatible static IR drop on the tuned early stage with that of the post sign-off is. The first column in Figure 3 equals static IR drop of prototyped design with only block level information in the early stage, while the second one is static IR drop in the post sign-off come from real physical design and instance level analysis. Static IR drop

Figure 2: IR drop comparison before and after adding extra P/G bump

(b) IR drop map of after adding extra P/G bump (a) IR drop map of original P/G bump

tendencies and shape of contour maps of both stages in Figure 3 are almost same and there is static IR drop difference about 6.6% between the early and post stage.

We developed the early stage P/G bump optimization flow based on the well-correlated environment illustrated on the Figure 3. Such a good correlated environment enabled the P/G bump optimization to be as accurate as a post sign-off. The P/G bump optimization flow in the early design stage consists of three major procedures; design prototyping, power map creation and P/G bump optimization. The following sections will introduce a respective stage in detail. Design Prototyping We developed some functions performing prototype of physical design as it is with limited input data. The design prototyping feature is based on TCL, it is able to be compatible with any kind of SVP(Silicon Virtual Prototyping) environment. Design prototyping feature in the P/G bump optimization technique can create various type of floorplan, power planning from upmost layer to power/ground standard cell pin as well as bump. It can do cell placement such as power gating or decap cell as well. The input requirements for design prototyping can be in the form of DEF/LEF or constant values such as the size of block or location info. Figure 4 shows outcome after design prototyping of a certain design target for mobile phones. The outcome of design prototyping in Figure 4 was generated with block level floorplan information and an initial version of RDL routing in the form of DEF. The squares in white or red-yellow denotes power and ground bump.

Figure 3: Correlation result of between early and post stage

Power Map Creation To obtain an optimal P/G bump placement, most important key factor is the amount of power consumption. When power consumption is overestimated, excessive P/G bumps are required. On the other hand, an optimistic power can bring more underestimated the number of P/G bump. Hence, creating proper power data which represents chip or block’s switching activity well is very important. However, creating meaningful power budget in the early design stage, particularly, when RDL and package routing are decided, is very difficult due to high probability of design change and insufficient principal requirements like loading cap and switching activity which are major factors for the amount of power consumption. Even if fairly certain requirements are ready, even current distribution on block level is only available due to insufficient of physical design information in the early design stage; consequently such an equal current distribution results in much more optimistic power integrity characteristic than in real. To overcome this optimistic and inaccurate power data, we invented a new method creating more accurate power data. The new method removes optimism due to even current distribution by dividing a block level power into a plenty of fine-grain bins. The power of a certain block is divided into a lot of a specific size of bins and the power of the block is recalculated based on the bin. The power value for new method is obtained from the previous sign-off run when the block is reused. Yet if there is no record of a block and a block or IP is first introduced, the power map creating feature in the P/G bump optimization flow creates a power map of new block based on Vectorless power calculation method. Figure 5 shows how instance based power in the previous run is reformed to fine-bin based power map and applied to the P/G optimization flow. The created power maps based on power data in the previous run or from Vectorless method are restored in the huge database like Figure 5(c). The P/G optimization flow draws the raw power map of each block from database, and then reforms a power map compatible with size, voltage and frequency target design requests. Figure 5(d) is the outcome of power assignment through P/G optimization flow’s power map creation feature.

Figure 4: Outcome of design prototyping with block level floorplan and RDL information

P/G Bump Optimization This section explains how the proposed technique optimizes P/G bump in pitch between bumps and placement. The P/G bump optimization stage consists of the following major works; performing several static IR drop analysis with created power map, determining an optimal P/G bump pitch, performing dynamic IR drop and bump oriented EM analysis, creating new P/G bump topology. The current and the number of P/G bump per each bin are determined through the first static IR drop run. The optimal P/G bump pitch is determined from the other static IR drop runs. An optimal P/G bump pitch is a diagonal distance between closest P/G bump to cause allowable static and dynamic IR drop more. Once the optimal P/G bump pitch is set, the P/G bump optimization flow determines where more P/G bumps should be added through dynamic IR drop and bump oriented EM analysis, finally, create a report file and a new P/G bump placement map. Figure 6 shows the P/G bump map before and after the

Figure 5: The procedure of creating fine-grain bin based power map and applying the power map to the P/G optimization flow.

(a) Instance based power density map at post sign-off

(b) Reformed power map per a certain bin size based on power data in the previous run

(c) Database having power maps of blocks (d) The outcome by power map creating method assigning respective power of each block

P/G bump optimization technique. The sample design in Figure 6 achieved about 60% P/G bump count reduction through the P/G bump optimization technique.

Static/Dynamic IR Drop Tendency According to P/G Bump Pitch To ensure accuracy of the proposed technique, we did various experiments on simulation level. As the first step, we implemented three cases of CPU design with different P/G bump interval. Figure 7 provides static IR drop tendency according to P/G bump pitch. The P/G bump pitch is a diagonal distance between two closest bumps. As shown in Figure 7, Static IR drop is getting increased as the P/G bump pitch is getting wider. However, IR drop is not linearly increased. The IR drop difference between 1X and 1.5X shows widening P/G bump pitch of 1.5X leads to more IR drop rising of 0.7~3mV, while 2X wider P/G bump distance draws more IR drop of 2.59~7mV which is somewhat bigger than 1.5X. That means if there is surplus P/G bumps, an optimal P/G bump pitch exists to cause allowable IR drop more. The proposed method has the feature to find such an optimal P/G bump pitch and performs P/G bump optimization based on the optimal point. In this case, the optimal P/G bump pitch is 1.5X wider than original. We performed the same experiment with 32nm SoC design target for mobile phone in terms of dynamic IR drop as well (the respective IR drop value is normalized based on MaxTW). We found there are the similar dynamic IR drop tendencies according P/G bump interval like static IR drop and a certain P/G bump pitch exists not to cause more dynamic IR drop. In the case, we found the optimal P/G bump pitch is 2X wider than original. Two experiment results on the above show an optimal P/G pitch can be different according to design. The CPU design in static IR drop experiment has quad core, while the SoC mobile design is based on dual core CPU. Four cores largely have much higher switching activity and power consumption than dual cores. The optimal P/G bump pitch in CPU with quad cores has narrower optimal P/G bump pitch than that of SoC design with dual cores seems to be proper phenomenon.

Figure 6: before and after of P/G bump optimization

(a) The original P/G bump map (b) New P/G bump map after P/G bump optimization applied

Figure 9: Dynamic IR drop at various viewpoints between 1X vs. 2X

Figure 7: Static IR drop tendency vs. P/G bump pitch

Figure 8: Dynamic voltage drop map 1X vs. 2X

(a) Dynamic IR drop with 2X (b) Dynamic IR drop with 1X

(a) Several types of dynamic IR drop[1] (b) Various dynamic IR drop results 1X vs. 2X

Several types of dynamic IR drop results are shown in Figure 9. Figure 9(a) illustrates what the respective type of dynamic IR drop in the table of Figure 9(b) means. Figure 9(a) provides the maximum dynamic IR drop of each type. As shown in Figure 9(b), all kinds of dynamic IR drop tendency and difference between 1X and 2X are almost same at the optimal P/G bump pitch. To ensure if dynamic IR drop on instance level has the same phenomenon at the optimal P/G bump pitch, we extracted dynamic voltage drop of each cell in the form of histogram like Figure 10. Figure 10 represents the number of instance being belong to a certain dynamic IR drop. Histogram between 1X and 2X in Figure 10 has different shape around 0~50mV. The phenomenon can be explained that 2X wider P/G bump pitch led to change in resistance and current distribution, consequently affected dynamic voltage drop on cell instance level. However, the difference in dynamic IR drop varying the number of instance can affect does not drastically increase dynamic IR drop of all instances.

The 2X wider P/G bump pitch in this case may not lead to increase in dynamic IR drop of cell instance. However, current per P/G bump may well increase than 1X due to wider distance between P/G bumps. Figure 11 shows how current per P/G bump changes according to P/G bump pitch. The 2X wider P/G bump in Figure 11(b) has more P/G bump in yellow and red colors which denote the amount of current is higher than blue or other colors. The proposed P/G optimization method restricts current per P/G bump not to exceed EM rule of bump. Even though there is negligible difference in static and dynamic IR drop at an optimal P/G bump pitch, if there are P/G bumps with higher current than EM rule, the proposed method figures out the new optimal P/G bump pitch or report more P/G bumps to be added. As shown in the above simulation experiments, the proposed optimization method enables designer to have an optimal P/G bump topology ensuring no drawback power

Figure 10: Histogram of DvD of Instance’s Min WC between 1X and 2X

(a) Instance dynamic IR drop histogram of IX (b) Instance dynamic IR drop histogram of 2X

noise by finding an optimal P/G bump pitch satisfying with static/dynamic limit and performing the P/G bump optimization based on the optimal point.

Verification from Simulation Trough Silicon to System Level To validate how the proposed optimization technique correlates with post silicon, we selected the mobile design used in dynamic IR drop experiment on the previous section as a sample chip, thence optimized P/G bump of the sample chip based on result from the proposed method. The sample chip, except P/G bump topology, is the same as embedded to the mobile phone which is currently sold in the market. The sample chip with 2X wider P/G bump pitch than the original was manufactured through the same processes as real product. The sample chip had passed the entire validation processes covering scan, ATE(Automatic Test Equipment) and software performance validation on system-level with showing the same level of performance as original. Figure 12 provides the comparison results of performance between 1X and 2X at a system level software validation. As shown in Figure 12, the sample chip with 2X wider P/G bump pitch gives a similar performance to 1X satisfying the limit of significant difference. In some of the sample lots, the sample design even shows better performance than 1X.

Figure 11: Pad current map after dynamic IR drop analysis

(a) Pad current map of 1X (b) Pad current map of 2X

Figure 12: The performance comparison results at system level software validation test between 1X vs. 2X

To see how power integrity characteristics change according to P/G bump pitch when package and system level information are involved, we performed co-analysis consisting of chip, package, and board as well. To reflect accurately on-die’s power integrity tendency, we created Chip Power Model(CPM) from RedHawk TM, thence we integrated CPM into package and board data. Package and board information are provided in the form of S-parameter. Figure 13, 14 and 15 demonstrates comparison results at specific power domain extracted from CPM versus P/G bump pitch. 1X and 2X denote the original and the sample chip respectively. Figure 13 illustrates time varying current profile versus P/G bump pitch. As shown in Figure 13, although the number of P/G bump is about 50% decreased and the amount of current per bump is increased, time varying current in 2X is rather reduced than 1X. The interesting results come from that 2X wider P/G bump space changed resistance, subsequently brought more well distributed current by relieving abnormal current distribution due to surplus P/G bump. Figure 14 provides frequency varying current spectrum according to P/G bump space. Frequency varying current spectrum shows a little bit different tendency with time varying current profile. As Figure 14 shows no difference at below 1GHz, but frequency varying current in 2X is considerably getting less than 1X as frequency is getting higher from around 1GHz as well.

Figure 13: Time varying current profile from CPM

We obtained impedance profile which is equals to RC on die from CPM in dimension of on-chip bump. Impedance according to P/G bump space in Figure 15 appears well as we expected. The P/G bump reduction due to 2X wider distance led to increase resistance. The difference in resistance is noticeable at the same frequency which 2X wider P/G bump has less current than 1X in Figure 14.

Figure 16 shows overall voltage plot and the peak to peak voltage in the dimension of on-die bump from a co-analysis including chip, package and board. The peak to peak voltage

Figure 14: Current spectrum at FFT extracted from CPM

Figure 15: Z-profile on on-chip bump extracted from CPM

of 2X is about 2% less than the original. The reduced current in 2X (refer to Figure 13 and 14) had a key role in fall-off of overall and peak to peak voltage drop.

We extracted Z-profile through the co-analysis covering chip, package and board as well. In this case, the impedance of both 1X and 2X are so identical that impedance curve of 1X is overlapped by that of 2X. Figure 17 shows well a slight change in resistance and current caused by changed P/G bump topology does not affect impedance.

As aforementioned, we made a sample chip based on result from the proposed method and verified that new P/G bump topology has the same level of performance with the original one. This new P/G bump topology even slightly improved power integrity characteristic of chip.

Figure 16: Vpeak-to-peak @ bump with chip (CPM) + Package + Board

Figure 17: Impedance with Chip (CPM) + Package + Board

Key Benefits of Early Stage P/G Bump Optimization Technique The proposed P/G bump optimization technique on the early design stage has been applied to most of our flip chip designs. By adopting the proposed method, we could avoid an excessive chip design since it largely leads to declining the number of P/G bump in the traditional method; consequently we could accomplish cost reduction of a package and manufacturing probing card on post silicon tests. In particular, the P/G bump optimization method can give a solution to constraints in RDL and package routing without increasing on-die or package. Figure 18 shows how a certain design’s P/G bump placement is reformed through the proposed method. Prior to apply the proposed method, the package routing of the sample design was impossible due to a great deal of P/G and signal bumps. Widening bump pitch as much as package needs was the only solution, however, it was supposed to increase chip size inevitably. To enable the RDL and package routing, the proposed method forced the signal P/G bump space to extend, it resulted in shrinking P/G bump area, and however, potential power noise due to outgrown P/G bump area could be compensated by adding 6 more pairs of P/G bumps. The chip in Figure 18 is laid in mass production. In terms of a post silicon test, the cost of manufacturing Vertical Probing Card(VPC) grows as the number of P/G bump. Thus, to have less the number of P/G probing pin is most key factor to reduce cost of a post-silicon stage. The proposed method has the feature finding optimal P/G bumps to be probed for post silicon tests. A design which the P/G bump optimization technique is unapplied is supposed to goes through optimal probing lists independently.

The P/G bump optimization method contributes to improve power integrity as well as cost reduction. Power map creation and design prototyping features in the optimization method can provide environment as accurate as a post sign-off, it enables designer to predict potential power noises and remove the issues earlier. Especially, since the P/G bump optimization finds where is more likely to have power noise issues due to

Figure 18: An example how the proposed method solves constraints due to RDL or package routing complexity

(a) The original P/G bump topology with package congestion

(b) The new P/G bump topology after applying P/G bump optimization

insufficient P/G bump and reports the information of P/G bump to be added, designer can prevent power noises due to insufficient of P/G bump in advance. In user environmental compatibility, the P/G bump optimization technique is developed with a TCL basis; it can be invoked in any commercial IR/DvD analysis environment. Besides, the approach does not need huge nodes and complicated current sink models, the run time including IR and DvD analysis is significantly faster than post sign-off analysis. The P/G bump optimization flow can be completed within a few hours with very large design target for digital TV and mobile application.

Summary To achieve the dominant position in the world market of a semiconductor chip, both product cost reduction and performance improvement of a chip are the prime needs. As a method to decrease product cost, particularly, in a flip-chip packaging design, we invented the proposed P/G optimization technique on the early design stage. Prior to deploy the proposed technique to the chips in mass production, we validated the P/G bump optimization technique on system as well as silicon level. Through the validation process, we achieved the new P/G bump topology with about 50% reduced P/G bump count compared to the original chip from the proposed technique has the same level of performance as the original one. The technique is being applied to most of SoC products with flip chip packaging below 32nm target for smart phone and digital TV. By the technique, we could detect potential power noises and strengthen power integrity of chip through package from early design stage. We have accomplished averagely over 30% P/G bump reduction compared with the traditional method, the reduction of P/G count has resulted in cost reduction by about 20% in a packaging and post-silicon validation.

Acknowledgements The authors would like to give a lot of appreciation to Kee-Sup Kim about the active support and management. In addition, the authors gratefully acknowledge the key insights provided by Seil Kim towards explaining the observed phenomenon in terms of co-analysis of chip, package and board. References [1] "RedHawkTM Vectorless Dynamic Analysis", Apache Design, a subsidiary of ANSYS