1 Hall D Drift Chamber ElectronicsFJ Barbosa Drift Chamber Review6-8 March 2007 Electronics for CDC and FDC Hall D 1.Motivation 2.ASIC Development 3.Preamp

1

Hall D Drift Chamber Electronics FJ Barbosa

Drift Chamber Review 6-8 March 2007

Electronics for CDC and FDCHall D

1. Motivation2. ASIC Development3. Preamp Cards4. Cabling5. Cooling6. fADCs7. TDCs8. HV, LV & Grounding9. Summary

F.J. Barbosa, Jlab

Central DriftChambers (CDC)

Forward Drift Chambers (FDC)

2



1. Motivation A Brief Summary of Specifications

Type Straw PlanarChannel Count 3200 anodes 2304 anodes

9216 cathodesPhysics Signal 225 e 94 eEnergy Resolution 15% 15%Time Resolution 2 ns 1 nsDetector Gain 2 x 104 105

Dynamic Range 100 fC → 3 pC 300 fC → 3pC anodes10 fC → 1 pC cathodes

dE/dx Yes NoPreamp Gain 2 mV/fC 2 mV/fC anodes

10 mV/fC cathodesSingle Channel 3kHz - 100 kHz < 280 kHz anodesRate < 600 kHz cathodesTDC No anodes: Yes115 ps cathodes: NofADC Yes anodes: No12-bit, 100MSPS cathodes: Yes

CDC FDC

3



+++

+++

- -- - --

+HV

RC

Cathode Strips

Anode Wire

Ionizing TrackPreamp

fADC

TDC

fADC

Pipelined DAQ

+++

+++

- -- - --

+HV

RC

Straw Tube

Anode Wire

Ionizing Track

fADC

GND

FDC

CDC

Generalized Readout Electronics

For the cathode strips, q+ ~ 1/5 q-

Disc

4



2. Application Specific Integrated Circuit (ASIC) Development

• The GlueX Preamp ASIC is Being Designed by Mitch Newcomer at U. Penn., the Designer of the ASDQ ASIC – used at CDF at FNAL.

• This Development is Based on the ASDQ ASIC:

Input

Protect

Preamp,

Shaper &

BLR

Discriminator

& dE/dx

Output

Driver

+

-

+

-

• The ASDQ ASIC was Fabricated in a Bipolar Technology which is no Longer Available (Maxim SHPi).

ASDQ Functional BlocksASDQ Photomicrograph

5



Block Diagram of the GlueX ASIC Prototype:

The GlueX ASIC

Input

Protect

Output

Driver

+

-

+

-Preamp ShaperInputs Outputs

• Input Protection – Protects Inputs from Discharge Spikes. →

• Preamp - Amplifies Detector Signals with Minimal Signal Shaping.

• Shaper – Ion Tail is Shortened by Pole-Zero Filtering Which Improves High Rate Operation.

• Output Driver – Provides Drive for Signals Through Cables.

N input

P input

• The GlueX ASIC Will be Fabricated Using the 0.25 µm TSMC CMOS Process.

6



Linearity is Maintained to a few %in the 0 - 400 fC Range.

Dif

fere

nti

al O

utp

ut

Am

plit

ud

e (m

V)

Some Simulation Results of the GlueX ASIC

• Output Linearity is Within a Few % Over the Range of Interest.

• ENC Has Been Simulated to be Nominally 2500 e- + 50 e-/pF, as a Function of Detector Capacitance.

7



InputTransistors

Cascodes

212um

44

0u

m

Channels 8

Inputs Type Dual (+ and -)

Impedance 80 Ohm

Protection Diode Protected

C Range 10-100pF

Shaping Peaking Time

11ns @ 10pF Cin

Unipolar – [CR-RC3]

Outputs Type Differential, Offset Bias

Range 0-1000 mVp-p

(-425mV to +575mV

Gain 2mV/fC

Range 0-400 fC Impulse or Point Ionization

Noise ENC 2500 e + 50 e/pF

Power Supply

+2.5V

Power 320 mW (40mW/Channel)

Process 0.25µm CMOS TSMC

Die Size 2.4mm x 3.2mm

Packaging QFN64 10x10 mm

The GlueX ASICSummary of Specifications

One Channel Layout

8



Status of the GlueX ASIC Prototype:

• Design and Layout Have Been Completed.

• Design Rule Check (DRC) is Underway.

• Design will be Submitted to MOSIS by Middle of March.

• TSMC Run, Through MOSIS, on 9 April 2007.

• MOSIS will Perform a Final DRC Before Fab Run.

9



Future Developments for the GlueX ASIC

• We will be testing the prototype GlueX ASIC Preamp during the Spring and Summer of 2007.

• What Will We Get?

1. Valuable information about the analog section on about 40 chips.

2. Validate the simulation models and the TSMC Process.

3. Verify proper operation with realistic detector conditions and adjust parameters as necessary:

Tests will be conducted on the FDC and CDC Prototypes.

10



• Towards the Final Design of the GlueX Preamp• Design work will continue for the next year:

Shaping Control – Allows tailoring of the ASIC characteristics to various detector characteristics.

Discriminators – Will be Added to Accommodate the FDC Anodes → Lower Cost

→ No External Discriminators.

Gain Control – Will be Added to Accommodate the FDC Cathodes.

Gain ShapingAmp/Disc

Vth

Diff. outputs

ASIC

Simplified Diagram of the Final GlueX ASIC

← 5 Pins Common to 8 Channels

11



3. Preamp Cards

Major Design Considerations

• Space Constraints

• Cooling

• Serviceability

Geometry of the Detectors, Cables, Gas Lines, Mechanical Structures.

The preamp card has to fit the FDC space requirements, which are the most severe of the wire chambers.

Cooling of any detector electronics is severely constrained due to limited space.

It is desirable to replace preamp cards with minimal down time.

• Standardization It is desirable to have a single preamp architecture.

12



Layout of the GlueX 24-Channel Preamp Card

Input Connector(located on translator board)

50-pinOutput Connector

There are two ASICs on the top side and one on the bottom side.

A supply regulator is on the bottom side.

GlueX ASICInput Protection

Material is FR-4, 4-layer and 0.8 mm thick.

Components on both sides of the PCB.

The 25th pair of pins will be used for pulse calibration.

Top View

Power Dissipation = 1.152 Watts

13



4. Cabling AMPHENOL SPECTRA-STRIP50-Conductor Cable

Twisted-Pair Impedance = 90 Ohm

• We are considering this cable for its dimensions and electrical characteristics.

FDC

14



5. Cooling

Cables areRouted OutUniformlyOver theSurface ofthe FDC

The FourFDC PackagesAre Located inThis Region

• The FDC Has 11,520 Preamp Channels 480 Preamp Cards

►► 553 Watts.

Cables areRouted OutFrom theCDC

CDC

15



• Cooling will be effected by heat conduction from the preamp cards to the cooling system.

• We also want to minimize convective losses to ambient air.

Cooling System

BarrelCalorimeter

• We are investigating various options as forced air is not adequate for cooling the preamp cards.

OutputConnector

ASIC

Cable

5 cm

Preamp Card

InputConnector

Copper Braid0.030” x 0.625” x 5”

6 mm Gap

Radiator Block

FDC Package(Side View)

16



Temperature Profile of the GlueX Preamp Card – Simulation at Ambient Temperature of 25 ºC

Still Air: ASIC Tj = 103C Conductive Cooling: ASIC Tj = 75C

120 ºC

40 ºC

120 ºC

40 ºC

• The preamp cards should not be operated without cooling provisions.

• Conductive cooling is effective at removing heat from the card.

• However, thermal performance is marginal as we would like to operate at lower Tj for improved reliability margins.

• An improved cooling system must be considered … … low pressure liquid cooling?

17



6. fADCs

• A flash ADC is currently under development for the CDC and FDC:

72 Channels 12-bit Resolution 80 or 105 MSPS (depending on final chip selection) Differential Inputs 2048 (19.5 μS) Acquisition Buffer Calibration Pulsing of Detector Electronics

• Programmable Window and Latency.

• Shaping and anti-aliasing input filter for cable loss equalization and low noise.

• VME64X & 2eVME (~320 MByte/s).

• A prototype board of the frontend shaping filter is being tested with the FDC prototype.

18



7. TDCs

• The F1TDC is a Multi-hit TDC developed at Jlab.

• VME64x Standard.

• 64 Channels – 115 ps rms.

• 32 Channels – 60 ps rms.

• Over 90 Modules in Use at Jlab.

19



3 fADC Racks

1 TDC Rack

4 Racks for

-HV-Low Voltage-Monitoring-Controls

on Lower Level

3 Racks for

-HV-Low Voltage-Monitoring-Controls

1 fADC Rack

CDC

FDC

• Cables are Shielded, Grounded & Routed to Minimize Exposure to Workers.

• Electronics Racks are Located Adjacent to Each of the Detectors.

• Platforms & Racks are Connected to Common Experiment Ground.

•Multiple Levels of Power Supply Current Limiting and Fusing.

= Safety

8. HV, Low Voltage & Grounding

20



9. Summary

• ASIC - Test the Prototype and Finalize the Design.

• Preamp Card - Will be Revised to Reflect the Final Design of the ASIC.

• Cooling System - Will be Carefully Considered Based on Cabling, the Heat Load Due to the CDC, FDC and the other Detectors.

• fADC - Development Will Continue Over the next Year and Prototype Tests Will be Used to Optimize the Design.

• TDC - Will be Modified to Accept LVDS Input Signals and To Provide Calibration Pulsing to the Detectors.

Documents

1 Hall D Drift Chamber ElectronicsFJ Barbosa Drift Chamber Review6-8 March 2007 Electronics for CDC and FDC Hall D 1.Motivation 2.ASIC Development 3.Preamp