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Digital Design: Sequential Logic Blocks

Credits:Slides adapted from:J.F. Wakerly, Digital Design, 4/e, Prentice Hall, 2006C.H. Roth, Fundamentals of Logic Design, 5/e, Thomson, 2004R.H. Katz, G. Borriello, Contemporary Logic Design, 2/e, Prentice-Hall, 2005

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Registers

A collection of 2 or more D flip flops with a common clock Registers are often used to store a collection of related

bits (e.g. a byte of data in a computer)

OUT4

Clr Clr Clr

D Q D Q D Q D Q

OUT1 OUT2 OUT3

CLK

IN1 IN2 IN3 IN4

Clr

Clear

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A “standard” 4-bit register IC

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A “standard” 8-bit register IC

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Registers with 3-state outputs

(a) Symbol (b) Functional Diagram

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A “standard” 8-bit register with 3-state outputs

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Registers with clock enable

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8

Q

DCE

Load Clk In

Out

ClrClrN

(a) Symbol

D Q

CK

0

1

D Q

CK

0

1

D Q

CK

0

1

In0

CE

ClrN

In7

Clk

In1

Out0

Out1

Out7

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A standard 8 bit register with clock enable (= “gated” clock)

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Registers application: Data Transfers

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Shift Registers It is a register that stores input values in sequence. At

each clock tick the values stored are shifted from one flip flop to the adjacent

block diagram

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Cascading Flip Flops

tFF1 < Tclock – Tsu2 + tskewSetup Constraint:

tFF1 > Th2 + tskewHold Constraint:

If flip flops were ideal (tFF = 0) shift registers would not work ! The hold time constraint would not be satisfied !!

For long shift registers, skew can easily become an issue and cause hold time constraint to be violated

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Shift Registers (cont’d)

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Shift Registers (cont’d)

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Shift registers (cont’d)

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clear sets the register contentsand output to 0

s1 and s0 determine the shift function

s0 s1 function0 0 hold state0 1 shift right1 0 shift left1 1 load new input

left_inleft_out

right_out

right_in

Universal shift register

serial or parallel inputs serial or parallel outputs permits shift left or right shift in new values from left or right

clear

output

input

s0s1

clock

Universal

Shift Register

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parallel inputs

parallel outputs

serial transmission

Shift register application

Parallel-to-serial conversion for serial transmission

Serial-to-parallel conversionParallel-to-serial conversion

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CLK

Shift register application (cont’d)

Pattern Recognizerin this case, recognizing the pattern 1001

D Q D Q D Q D QIN

OUT1 OUT2 OUT3 OUT4

OUT

CLR

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Ring Countercounters are systems that sequences through a fixed set of

patterns in this case the sequence is 1000, 0100, 0010, 0001

provided that one of the given patterns is forced as initial state (by loading or set/reset)

Shift register application (cont’d)

D Q D Q D Q D QIN

OUT1 OUT2 OUT3 OUT4

CLK

START S R R R

NOTE: with 4 FF we

make only 4 patterns

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Johnson (= Moebius = Twisted-ring) Counter

Shift register application (cont’d)

D Q D Q D Q D QIN

OUT1 OUT2 OUT3 OUT4

CLK

How does this counter work? Counts through the sequence: 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000

NOTE: with 4 FF we make 8 patterns. Adjacent patterns have

distance one (glitch free decoding)

we can use 0000 or

1111 as reset state

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Ring and Johnson counter Timings

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Binary Counters A counter is a clocked sequential circuit that sequences through

a fixed set of patterns A counter with m-states is called a modulo-m-counter, or

sometimes a divide-by-m counter The most commonly used counter type is an n-bit binary counter

(each of the states is encoded as the corresponding n-bit binary integer)

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Binary Counters (cont’d)

Ripple countersDon’t use them !!! The output of the flip-flops are fed

into the clock pin causing skew. As a result reliability becomes an issue (especially for high speed applications).

Synchronous countersThe operation of the flip flops is synchronized by a

common clock.

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Synchronous Binary Counters

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Synchronous Binary Counters (cont’d)

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Sync. Binary Counters with T-FF

QA toggles always (every clock tick)

QB toggles every time QA = 1

QC toggles every time QA AND QB are both 1

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Sync. Binary Counters with D-FF

XOR decides when bit should be toggled The toggling rule is as follows:

always for low-order bit; only when first bit is true for second bit; only when first and second bit are true for third bit; and so on

D Q D Q D Q D Q

OUT1 OUT2 OUT3 OUT4

CLK

"1"

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Example: Binary Up/Down Counter

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Binary Up/Down Counter (cont’d)