1 Computer Sci. & Engr. University of Notre Dame 1 Lectures 11-12 CSE 30321 MIPS Single Cycle Dataflow

1

Computer Sci. & Engr.University of Notre Dame

1Lectures 11-12

CSE 30321MIPS Single Cycle Dataflow

2


2Lectures 11-12

The goals of this lecture are…• …to show how ISAs map to real HW and affect the organization of processing logic…

• …and to set up a discussion of pipelining + other principles of modern processing…

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3Lectures 11-12

The organization of a computer

Control

Datapath

MemoryInput

Output

Von Neumann Model: • Stored-program machine instructions are represented as numbers• Programs can be stored in memory to be read/written just like numbers.

Processor

CompilerToday

we’ll talkabout these

things

4


4Lectures 11-12

Functions of Each Component• Datapath: performs data manipulation operations

– arithmetic logic unit (ALU)– floating point unit (FPU)

• Control: directs operation of other components– finite state machines– micro-programming

• Memory: stores instructions and data– random access v.s. sequential access– volatile v.s. non-volatile– RAMs (SRAM, DRAM), ROMs (PROM, EEPROM), disk– tradeoff between speed and cost/bit

• Input/Output and I/O devices: interface to the environment– mouse, keyboard, display, device drivers

5


5Lectures 11-12

The Performance Perspective• Performance of a machine determined by

– Instruction count, clock cycles per instruction, clock cycle time

• Processor design (datapath and control) determines:– Clock cycles per instruction– Clock cycle time

• We will discuss a simplified MIPS implementation

6


6Lectures 11-12

Review of Design Steps• Instruction Set Architecture => RTL representation

• RTL representation =>– Datapath components– Datapath interconnects

• Datapath components => Control signals • Control signals => Control logic

• Writing RTL: How many states (cycles) should an instruction take?– CPI– Datapath component sharing

7


7Lectures 11-12

MIPS Instruction Formats

• All MIPS instructions are 32 bits (4 bytes) long.

• R-type:

• I-Type:

• J-type

op (6) rs (5) rt (5) rd (5) shamt (5)

31 26 25 21 20 16 15 11 10 6 5 0

funct (6)

Op (6) rs (5) rt (5) Address/Immediate value (16)

31 26 25 21 20 16 15 0

Op (6) Target address (26)

31 26 25 0

8


8Lectures 11-12

Let’s talk about this generally on the board first…

• Let’s just look at our instruction formats and “derive” a simple datapath– (we need to make all of these instruction formats “work”)

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9Lectures 11-12

The MIPS Subset• To simplify things a bit we’ll just look at a few

instructions:– memory-reference: lw, sw– arithmetic-logical: add, sub, and, or, slt– branching: beq, j

• Organizational overview:– fetch an instruction based on the content of PC– decode the instruction– fetch operands

• (read one or two registers)

– execute • (effective address calculation/arithmetic-logical operations/comparison)

– store result • (write to memory / write to register / update PC)

At simplest level, thisis how Von Neumann,RISC model works

10


10Lectures 11-12

What we’ll do…• …look at instruction encodings…• …look at datapath development…• …discuss how we generate the control signals to make the datapath elements work…

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11Lectures 11-12

Implementation Overview

• Abstract / Simplified View:

• 2 types of signals: data and control• Clocking strategy: All storage elements clocked by

same clock edge.

A L U

PCPC AddressAddress

InstructionInstruction

InstructionMemory

InstructionMemory

RaRa

RbRb

RwRw

DataData

RegisterFile

RegisterFile

DataMemoryDataMemory

AddressAddress

DataData

ClkClk

ClkClk ClkClk

ClkClk

simplest view ofVon Neumann, RISC P

12


12Lectures 11-12

Review of Design Steps• Instruction set Architecture => RTL representation

• RTL representation =>– Datapath components– Datapath interconnects

• Datapath components => Control signals • Control signals => Control logic

• Writing RTL: How many states (cycles) should an instruction take?– CPI– Datapath component sharing

i.e. PC PC + 4(or $4 $3 + $2)

need these to do

need these to do

need these to do

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14Lectures 11-12

Single Cycle Implementation

• Each instruction takes one cycle to complete.

• We wait for everything to settle down, and the right thing to be done

– ALU might not produce “right answer” right away

– (why?)

– we use write signals along with clock to determine when to write

• Cycle time determined by length of the longest path

PCPC instr. fetch & execute

instr. fetch & execute

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15Lectures 11-12

Instruction Word32

Next AddrLogic

Instruction Fetch Unit• Fetch the instruction: mem[PC] , • Update the program counter:

– sequential code: PC <- PC+4– branch and jump: PC <- “something else”

PC

InstructionMemory

Address

ClkClk

16


16Lectures 11-12

Let’s say we want to fetch……an R-type instruction

(arithmetic)• Instruction format:

• RTL: – Instruction fetch: mem[PC]– ALU operation: reg[rd] <- reg[rs] op reg[rt]– Go to next instruction: Pc <- PC+ 4

• Ra, Rb and Rw are from instruction’s rs, rt, rd fields.

• Actual ALU operation and register write should occur after decoding the instruction.

op (6) rs (5) rt (5) rd (5) shamt (5)

31 26 25 21 20 16 15 11 10 6 5 0

funct (6)

17


17Lectures 11-12

BusA

32 ALU

Datapath for R-Type Instructions

• Register timing:– Register can always be read. – Register write only happens when RegWr is set to high and at

the falling edge of the clock

32 32-bit

RegistersClkClk

RaRa

RwRwRbRb

55rsrs

rdrdrtrt 55

55

RegWrRegWr

BusB

32

BusW32

ALUctrALUctr

18


18Lectures 11-12

I-Type Arithmetic/Logic Instructions

• Instruction format:

• RTL for arithmetic operations: e.g., ADDI– Instruction fetch: mem[PC]– Add operation: reg[rt] <- reg[rs] + SignExt(imm16)

– Go to next instruction: Pc <- PC+ 4

• Also, immediate instructions


31 26 25 21 20 16 15 0

19


19Lectures 11-12

BusA

32 ALU

Datapath for I-Type A/L Instructions

3232-bit

RegistersClkClk

RaRa

RwRwRbRb

55rsrs

rdrd

rtrt 55

55

RegWrRegWr

BusB

32

BusW32

MUXMUX

MUX

MUX

32

ExtenderExtender

1616

imm16imm16

rtrt

ALUSrcALUSrc

RegDstRegDst

ALUctrALUctr

BusW

32

BusW

32

In MIPS, destinationregisters are in different

places in opcode thereforewe need a mux

must “zero out” 1st 16 bits…

note that we reuse ALU…

20


20Lectures 11-12

I-Type Load/Store Instructions• Instruction format:

• RTL for load/store operations: e.g., LW– Instruction fetch: mem[PC]– Compute memory address: Addr <- reg[rs] + SignExt(imm16)

– Load data into register: reg[rt] <- mem[Addr]– Go to next instruction: Pc <- PC+ 4

• How about store?


31 26 25 21 20 16 15 0

same thing, just skip 3rd step(mem[addr] reg[rs])

21


21Lectures 11-12

Datapath for Load/Store Instructions

BusA

32 ALU3232-bit

RegistersClkClk

RaRa

RwRwRbRb

55rsrs

rdrd

rtrt 55

55

RegWrRegWr

BusB

32

MUXMUX

MUX

MUX

32

ExtenderExtender

1616

imm16imm16

rtrt

ALUSrcALUSrcRegDstRegDst

ALUctrALUctr

Data Memory

ClkClk

DataInDataIn3232

MemWrMemWr

WrEnWrEn AddrAddr

need a control signal

32 bits of data

address input

22


22Lectures 11-12

I-Type Branch Instructions• Instruction format:

• RTL for branch operations: e.g., BEQ– Instruction fetch: mem[PC]– Compute conditon: Cond <- reg[rs] - reg[rt]– Calculate the next instruction’s address:

if (Cond eq 0) thenPC <- PC+ 4 +

(SignExd(imm16) x 4)else ?


31 26 25 21 20 16 15 0

23


23Lectures 11-12

Datapath for Branch Instructions

BusA

32 ALU3232-bit

RegistersClkClk

RaRa

RwRwRbRb

55rsrs

rdrd

rtrt 55

55

RegWrRegWr

BusB

32

MUXMUX

MUX

MUX

32

ExtenderExtender

1616rtrt

ALUSrcALUSrcRegDstRegDst

ALUctrALUctr

Next AddrLogic

PCClkClk

ZeroZero

imm16imm16

To Instruction MemTo Instruction Mem

we’ll define this next;(will need PC, zero test

condition from ALU)

24


24Lectures 11-12

Next Address Logic

30ADD

MUX

MUX

30

SignExtSignExt

1616

“0”“0”

PCClkClk

imm16imm16BranchBranch ZeroZero

CarryInCarryIn“1”“1”

30 InstructionMemory

When does the correct new PC become available? Can we do better?When does the correct new PC become available? Can we do better?

May not want tochange PC if BEQcondition not met

(implicitly says:“this stuff happensanyway so we haveto be sure we don’tchange things we

don’t want to change”)

if branch instructionAND 0, can automaticallygenerate control signal

contains PC + 4(why 30? – subtlety – seeChapter 5 in your text)

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25Lectures 11-12

J-Type Jump Instructions• Instruction format:

• RTL operations: e.g., BEQ– Instruction fetch: mem[PC]– Set up PC: PC <- ((PC+ 4)<31:29> CONCAT(target<25:0>) x 4

Op (6) Target address (26)

31 26 25 0

26


26Lectures 11-12

Instruction Fetch Unit

30 ADD

MUX

MUX

30

SignExtSignExt

1616

“0”“0”

PCClkClk

imm16imm16 BranchBranch ZeroZero

CarryInCarryIn“1”“1”

30

InstructionMemory

PC<31:28>PC<31:28>

Instruction<25:0>Instruction<25:0>

MUX

MUX

JumpJump

Use:New address injump instruction

ORuse 4 MSBof PC

(why PC<31:28> – subtlety – see

Page 383 in your text)

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27Lectures 11-12

A Single Cycle Datapath

i

i

PC

Instructionmemory

Readaddress

Instruction

16 32

Add ALUresult

Mux

Registers

Writeregister

Writedata

Readdata 1

Readdata 2

Readregister 1Readregister 2

Shiftleft 2

4

Mux

3

RegWrite

MemRead

MemWrite

PCSrc

ALUSrc

MemtoReg

ALUresult

ZeroALU

Datamemory

Address

Writedata

Readdata M

ux

Signextend

Add

Add Jump.Add Jump.

ALUctrALUctr

28


28Lectures 11-12

Let’s trace a few instructions• For example…

– Add $5, $6, $7– SW 0($9), $10– Sub $1, $2, $3– LW $11, 0($12)

29


29Lectures 11-12

Control Logic

(I.e. now, we need to make the HW do what we want it to do - add, subtract, etc. - when we want it

to…)

30


30Lectures 11-12

The HW needed, plus control

PC

Instructionmemory

Readaddress

Instruction[31– 0]

Instruction [20 16]

Instruction [25 21]

Add

Instruction [5 0]

MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

BranchRegDst

ALUSrc

Instruction [31 26]

4

16 32Instruction [15 0]

0

0Mux

0

1

Control

Add ALUresult

Mux

0

1

RegistersWriteregister

Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Mux

1

ALUresult

Zero

PCSrc

Datamemory

Writedata

Readdata

Mux

1

Instruction [15 11]

ALUcontrol

Shiftleft 2

ALUAddress

When we talk about control,we talk about these blocks

Single cycle MIPS machine

31


31Lectures 11-12

Implementing Control

• Implementation Steps:

– Identify control inputs and control output (control words)

– Make a control signal table for each cycle

– Derive control logic from the control table

• Do we need a FSM here?

ControlPath

DataPath

Controlinput

Controloutput

Control inputs: Opcode (5 bits) Func (6 bits)

Control outputs: RegDst MemtoReg RegWrite MemRead MemWrite ALUSrc ALUctr Branch Jump

32


32Lectures 11-12

Implementing Control• Implementation Steps:

1. Identify control inputs and control outputs 2. Make a control signal table for each cycle3. Derive control logic from the control table

– This logic can take on many forms: combinational logic, ROMs, microcode, or combinations…

33


33Lectures 11-12

Single Cycle Control Input/Output

• Control Inputs:– Opcode (6 bits)– How about R-type instructions?

• Control Outputs:– RegDst– ALUSrc– MemtoReg– RegWrite– MemRead– MemWrite– Branch– Jump– ALUctr

these are columns

these are rows

Step 2:Make a control signaltable for each cycle

Step 1: Idenitfyinputs & outputs

34


34Lectures 11-12

Control Signal Table

Add Sub LW SW BEQ

Func (input)

100000 100010 xxxxxx xxxxxx xxxxxx

Op (input) 000000 000000 100011 101011 000100

RegDst 1 1 0 X X

ALUSrc 0 0 1 1 0

Mem-to-Reg 0 0 1 X X

Reg. Write 1 1 1 0 0

Mem. Read 0 0 1 0 0

Mem. Write 0 0 0 1 0

Branch 0 0 0 0 1

ALUOp Add Sub 00 00 01

R-type

(outputs)

(inputs)

35


35Lectures 11-12

The HW needed, plus control

PC

Instructionmemory

Readaddress


Instruction [20 16]

Instruction [25 21]

Add

Instruction [5 0]

MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

BranchRegDst

ALUSrc

Instruction [31 26]

4


0

0Mux

0

1

Control

Add ALUresult

Mux

0

1


Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Mux

1

ALUresult

Zero

PCSrc

Datamemory

Writedata

Readdata

Mux

1

Instruction [15 11]

ALUcontrol

Shiftleft 2

ALUAddress

For MIPS, we have tobuild a Main Control Blockand an ALU Control Block


36


36Lectures 11-12

Main control, ALU control

• Use OP field to generate ALUOp (encoding)–Control signal fed to ALU control block

• Use Func field and ALUOp to generate ALUctr (decoding)–Specifically sets 3 ALU control signals

• B-Invert, Carry-in, operation

MainControlMain

ControlALU

ControlALU

Control

ALU

ALUOpALUOp

FuncFunc

OPOPALUctrALUctr

66

66

2233

(opcode)

Our 2 blocksof control logic

Other cnt.signals

Other cnt.signals

37


37Lectures 11-12

Main control, ALU control

MainControlMain

ControlALU

ControlALU

Control

ALU

ALUOpALUOp

FuncFunc

OPOPALUctrALUctr

66

66

2233

Or in other words…00 = ALU performs add01 = ALU performs sub10 = ALU does what function code says

R-type lw sw beq

ALU Operation

“R-type”

add add subtract

ALUOp<1:0> 10 00 00 01

Outputs of main control,become inputs to ALU control

We have 8 bitsof input to our ALU controlblock; we need 3 bits of

output…

38


38Lectures 11-12

Generating ALUctr• We want these outputs:

ALUctr<2> = B-negate (C-in & B-invert)ALUctr<1> = Select ALU OutputALUctr<0> = Select ALU Output

ALU Operation and or add sub slt

ALUctr<2:0> 000 001 010 110 111 mux

and - 00

or - 01

adder - 10

less - 11

Invert B and C-in must be a 1 for

subtract

36 (and) = 1 0 0 1 0 037 (or) = 1 0 0 1 0 132 (add) = 1 0 0 0 0 034 (sub) = 1 0 0 0 1 042 (slt) = 1 0 1 0 1 0

can ignore these(they’re the same for

all…)

func<5:0>

• We have these inputs…ALUOp Funct field ALUctr

ALUOp1 ALUOp0 F5 F4 F3 F2 F1 F00 0 X X X X X X0 1 X X X X X X1 X X X 0 0 0 01 X X X 0 0 1 01 X X X 0 1 0 01 X X X 0 1 0 11 X X X 1 0 1 0

Inputs

lw/swbeq

R-type

010 (add)110 (sub)010 (add)110 (sub)

000 (and)001 (or)

111 (slt)

Outputs

39


39Lectures 11-12

The Logic

Ex: ALUctr<2>(SUB/BEQ)

orand

or

andor

(func<5:0>)

F0

F1

F2

F3

(ALUOp)ALUOp0

ALUctr<2>

ALUctr<1>

ALUctr<0>

ALUctr

ALUOp1

Could generate gates by hand, often done

w/SW.

ALUOp Funct field ALUctrALUOp1 ALUOp0 F5 F4 F3 F2 F1 F0

0 0 X X X X X X0 1 X X X X X X1 X X X 0 0 0 01 X X X 0 0 1 01 X X X 0 1 0 01 X X X 0 1 0 11 X X X 1 0 1 0

Inputs

lw/swbeq

R-type

010 (add)110 (sub)010 (add)110 (sub)

000 (and)001 (or)

111 (slt)

OutputsThis table is used togenerate the actualBoolean logic gatesthat produce ALUctr.

1/0X/1

0/X

0/X

1/X

0/X 0/X 0/0

1/0 1/1

1/1

0/0

110/110

40


40Lectures 11-12

Recall…

PC

Instructionmemory

Readaddress


Instruction [20 16]

Instruction [25 21]

Add

Instruction [5 0]

MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

BranchRegDst

ALUSrc

Instruction [31 26]

4


0

0Mux

0

1

Control

Add ALUresult

Mux

0

1


Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Mux

1

ALUresult

Zero

PCSrc

Datamemory

Writedata

Readdata

Mux

1

Instruction [15 11]

ALUcontrol

Shiftleft 2

ALUAddress

Recall, for MIPS, we have tobuild a Main Control Blockand an ALU Control Block


41


41Lectures 11-12

Well, here’s what we did…

PC

Instructionmemory

Readaddress


Instruction [20 16]

Instruction [25 21]

Add

Instruction [5 0]

MemtoReg

ALUOp

MemWrite

RegWrite

MemRead

BranchRegDst

ALUSrc

Instruction [31 26]

4


0

0Mux

0

1

Control

Add ALUresult

Mux

0

1


Writedata

Readdata 1

Readdata 2

Readregister 1

Readregister 2

Signextend

Mux

1

ALUresult

Zero

PCSrc

Datamemory

Writedata

Readdata

Mux

1

Instruction [15 11]

ALUcontrol

Shiftleft 2

ALUAddress


orand

or

andor

(func<5:0>)

F0

F1

F2

F3

(ALUOp)ALUOp0

ALUctr<2>

ALUctr<1>

ALUctr<0>

ALUctr

ALUOp1

We came up withthe information togenerate this logicwhich would fit herein the datapath.

42


42Lectures 11-12

(and again, remember, realistically logic, ISAs,

insturction types, etc. would be much more complex)

(we’d also have to route all signals too…which may affect how we’d like to organzie processing

logic)

43


43Lectures 11-12

Single cycle versus multi-cycle

44


44Lectures 11-12

Single-Cycle Implementation• Single-cycle, fixed-length clock:

– CPI = 1– Clock cycle = propagation delay of the longest datapath operations among all instruction types

– Easy to implement

• Single-cycle, variable-length clock:– CPI = 1– Clock cycle = (%(type-i instructions) * propagation delay of the type “i” instruction datapath operations)

– Better than the previous, but impractical to implement

• Disadvantages:– What if we have floating-point operations?– How about component usage?

45


45Lectures 11-12

Multiple Cycle Alternative• Break an instruction into smaller steps • Execute each step in one cycle.• Execution sequence:

– Balance amount of work to be done– Restrict each cycle to use only one major functional unit

– At the end of a cycle• Store values for use in later cycles, why?• Introduce additional “internal” registers

• The advantages:– Cycle time much shorter– Diff. inst. take different # of cycles to complete

– Functional unit used more than once per instruction

Documents

1 Computer Sci. & Engr. University of Notre Dame 1 Lectures 11-12 CSE 30321 MIPS Single Cycle Dataflow