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Microsoft PowerPoint - VHDL-intro2.ppt [Compatibility Mode]• concurrent signal assignment ()
di i l i l i• conditional concurrent signal assignment (when-else)
l d i l i• selected concurrent signal assignment (with-select-when)
t h f ti• generate scheme for equations (for-generate)
Microprocessors & Digital Systems Laboratory © 2009 National Technical University of Athens
MLU Block Diagramg
MLU Entity Declarationy
LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY mlu IS PORT(
NEG_A : IN STD_LOGIC; NEG B : IN STD LOGIC;NEG_B : IN STD_LOGIC; NEG_Y : IN STD_LOGIC; A : IN STD_LOGIC; B : IN STD LOGIC;B : IN STD_LOGIC; L1 : IN STD_LOGIC; L0 : IN STD_LOGIC; Y : OUT STD LOGICY : OUT STD_LOGIC
); END mlu;
MLU Architecture: Declarations
SIGNAL A1 : STD_LOGIC; SIGNAL B1 : STD LOGIC;SIGNAL B1 : STD_LOGIC; SIGNAL Y1 : STD_LOGIC; SIGNAL MUX_0 : STD_LOGIC; SIGNAL MUX_1 : STD_LOGIC; SIGNAL MUX_2 : STD_LOGIC; SIGNAL MUX 3 : STD LOGIC;SIGNAL MUX_3 : STD_LOGIC; SIGNAL L: STD_LOGIC_VECTOR(1 DOWNTO 0);
Microprocessors & Digital Systems Laboratory © 2009 National Technical University of Athens
MLU Architecture: Bodyy BEGIN
Y <= NOT Y1 WHEN (NEG Y='1') ELSE( _ ) Y1;
MUX_0 <= A1 AND B1; MUX 1 <= A1 OR B1;MUX_1 < A1 OR B1; MUX_2 <= A1 XOR B1; MUX_3 <= A1 XNOR B1;
L <= L1 & L0;L < L1 & L0;
with (L) select Y1 <= MUX_0 WHEN "00",
MUX_1 WHEN "01", MUX_2 WHEN "10", MUX_3 WHEN OTHERS;
Microprocessors & Digital Systems Laboratory © 2009 National Technical University of Athens
END mlu_dataflow;
FOR … GENERATE
END GENERATE;
PARITY Example
PARITY: Entity Declarationy
LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY parity IS PORT(
it i IN STD LOGIC VECTOR(7 DOWNTO 0)parity_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); parity_out : OUT STD_LOGIC
); END parity;
PARITY: Block Diagramg
Microprocessors & Digital Systems Laboratory © 2009 National Technical University of Athens
PARITY: Architecture ARCHITECTURE parity_dataflow OF parity IS
SIGNAL xor_out: std_logic_vector (6 downto 1);
BEGIN
t(1) it i (0) XOR it i (1)xor_out(1) <= parity_in(0) XOR parity_in(1); xor_out(2) <= xor_out(1) XOR parity_in(2); xor_out(3) <= xor_out(2) XOR parity_in(3); xor_out(4) <= xor_out(3) XOR parity_in(4); xor_out(5) <= xor_out(4) XOR parity_in(5); xor out(6) <= xor out(5) XOR parity in(6);_ ( ) _ ( ) p y_ ( ); parity_out <= xor_out(6) XOR parity_in(7);
END parity dataflow; Microprocessors & Digital Systems Laboratory
© 2009 National Technical University of Athens
END parity_dataflow;
PARITY: Architecture 2
SIGNAL xor_out: STD_LOGIC_VECTOR (7 downto 0);
BEGINBEGIN
t(4) < t(3) XOR it i (4)xor_out(4) <= xor_out(3) XOR parity_in(4); xor_out(5) <= xor_out(4) XOR parity_in(5); xor_out(6) <= xor_out(5) XOR parity_in(6); xor out(7) <= xor out(6) XOR parity in(7);xor_out(7) <= xor_out(6) XOR parity_in(7); parity_out <= xor_out(7);
END parity dataflow; Microprocessors & Digital Systems Laboratory
© 2009 National Technical University of Athens
END parity_dataflow;
SIGNAL xor_out: STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
xor out(0) <= parity in(0);_ ( ) p y_ ( );
G2: FOR i IN 1 TO 7 GENERATE xor out(i) <= xor out(i-1) XOR parity in(i);xor_out(i) < xor_out(i 1) XOR parity_in(i);
end generate G2;
END parity_dataflow;
Simple Rules
• concurrent signal assignment () • conditional concurrent signal assignment• conditional concurrent signal assignment
(when-else) • selected concurrent signal assignment• selected concurrent signal assignment
(with-select-when) • generate scheme for equations• generate scheme for equations
(for-generate)
Simple Rules
F i it d fFor circuits composed of - simple logic operations (logic gates) - simple arithmetic operations (addition, subtraction, multiplication)subt act o , u t p cat o )
- shifts/rotations by a constant useuse
• concurrent signal assignment ()
Simple Rules
useuse
diti l t i l i t• conditional concurrent signal assignment (when-else)
l t d t i l i t• selected concurrent signal assignment (with-select-when)
Microprocessors & Digital Systems Laboratory © 2009 National Technical University of Athens
Left vs Right Side of Assignmentsg g
<=Left side Right side <= when-else with-select <=
g
in a given architecture) • Ports of the mode
Expressions including: • Internal signals (defined
in a given architecture) • Ports of the mode
- out - inout
inoutinout - buffer
- inout - buffer
Arithmetic Operators
Synthesizable arithmetic operations:Sy t es ab e a t et c ope at o s Addition, + Subtraction, -Subtraction, Comparisons, >, >=, <, <= Multiplication *Multiplication, Division by a power of 2, /2**6
(equivalent to right shift)( q g ) Shifts by a constant, SHL, SHR
Microprocessors & Digital Systems Laboratory © 2009 National Technical University of Athens
Arithmetic Operators
The result of synthesis of an arithmetic operation is a - combinational circuitcombinational circuit - without pipelining.
The exact internal architecture used (and thus delay and area of the circuit)(and thus delay and area of the circuit) may depend on the timing constraints specified d i th i ( th t d iduring synthesis (e.g., the requested maximum clock frequency).
Microprocessors & Digital Systems Laboratory © 2009 National Technical University of Athens
QuestionsQuestions
Anatomy of a Processy
beging statement part
Microprocessors & Digital Systems Laboratory © 2009 National Technical University of Athens
Statement Part
Contains Sequential Statements to be Executed Each Time the Process Is Activated
Analogous to Conventional Programming Languages
Microprocessors & Digital Systems Laboratory © 2009 National Technical University of Athens
What is a Process
A process is a sequence of instructions referred to as sequential statements
A process can be given a unique name using an optional LABEL TESTING: process
sequential statements. The Keyword PROCESS
using an optional LABEL
p begin
TEST_VECTOR<=“00”; wait for 10 ns; TEST VECTOR<=“01”;
The keyword BEGIN is used to indicate the start of the process
TEST_VECTOR<= 01 ; wait for 10 ns; TEST_VECTOR<=“10”; wait for 10 ns; TEST VECTOR “11” All statements within the process are
executed SEQUENTIALLY. Hence, order of statements is important.
TEST_VECTOR<=“11”; wait for 10 ns;
end process;
Execution of Statements
The execution of statements
BEGIN test_vector<=“00”; WAIT FOR 10 ns; The execution of statements
continues sequentially till the last statement in the process.
After execution of the last r o f e
xe cu
tio n
WAIT FOR 10 ns; test_vector<=“01”; WAIT FOR 10 ns;
After execution of the last statement, the control is again passed to the beginning of the process
O rd
er test_vector<=“10”; WAIT FOR 10 ns; test vector<=“11”;process. test_vector< 11 ; WAIT FOR 10 ns;
END PROCESS;
Program control is passed to the first statement after BEGIN
Microprocessors & Digital Systems Laboratory © 2009 National Technical University of Athens
BEGIN
WAIT Statement
The last statement in the Testing: PROCESS PROCESS is a WAIT instead of WAIT FOR 10 ns.
This will cause the PROCESS
BEGIN test_vector<=“00”; WAIT FOR 10 ns;to suspend indefinitely when
the WAIT statement is executed.
WAIT FOR 10 ns; test_vector<=“01”; WAIT FOR 10 ns;
r o f e
xe cu
tio n
This form of WAIT can be used in a process included in a testbench when all possible
test_vector<=“10”; WAIT FOR 10 ns; test vector<=“11”;
O rd
er
combinations of inputs have been tested or a non-periodical signal has to be generated.
test_vector< 11 ; WAIT;
here
WAIT FOR vs WAIT
WAIT FOR: waveform will keep repeating p p g itself forever
0 1 2 3 0 1 2 3 …
WAIT : waveform will keep its state after theWAIT : waveform will keep its state after the last wait instruction.
… Microprocessors & Digital Systems Laboratory
Sensitivity Listy
List of signals to which the g process is sensitive.
Whenever there is an t f thevent on any of the
signals in the sensitivity list, the process fires.
label: process (sensitivity list) declaration part , p
Every time the process fires, it will run in its
ti t
Microprocessors & Digital Systems Laboratory © 2009 National Technical University of Athens
Process Suitabilityy
Processes Describe Sequential Behavior
Processes in VHDL Are Very Powerful Statements Allow to define an arbitrary behavior that may be difficult to
represent by a real circuit Not every process can be synthesized Not every process can be synthesized
Use Processes with Caution in the Code to Be Synthesized
Use Processes Freely in Testbenches
Microprocessors & Digital Systems Laboratory © 2009 National Technical University of Athens
Component Equivalent of a Process
yclk
w a z
priority b c
All signals which appear on the left of signal assignment statement (<=)
t t
IF w(3) = 1 THEN y <= "11" ;
ELSIF w(2) = '1' THEN y <= "10" ; are outputs e.g. y, z
All signals which appear on the right of signal assignment statement (<=)
y < 10 ; ELSIF w(1) = c THEN
y <= a and b; ELSE g g ( )
or in logic expressions are inputs e.g. w, a, b, c
All signals which appear in the
ELSE z <= "00" ;
END IF ; END PROCESS ; g pp
sensitivity list are inputs e.g. clk Note that not all inputs need to be
included in the sensitivity list
;
included in the sensitivity list
IF Statement - Syntaxy
end if;
Microprocessors & Digital Systems Laboratory © 2009 National Technical University of Athens
p
IF Statement: Example
SELECTOR: process begin
WAIT UNTIL Cl k'EVENT AND Cl k '1'WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF Sel = “00” THEN
f <= x1;f <= x1; ELSIF Sel = “10” THEN
f <= x2;; ELSE
end process;
2-to-4 Decoder
y 0
w 1
x x 0 0 0 0 0
( ) T th t bl (b) G hi l(a) Truth table (b) Graphical symbol
Microprocessors & Digital Systems Laboratory © 2009 National Technical University of Athens
Dataflow Description LIBRARY ieee ; USE ieee.std_logic_1164.all ;
ENTITY dec2to4 IS PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En : IN STD LOGIC ;En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END dec2to4 ;
ARCHITECTURE dataflow OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;
BEGIN Enw <= En & w ; WITH Enw SELECT
y <= “0001" WHEN "100", "0010" WHEN "101"0010 WHEN 101 , "0100" WHEN "110", “1000" WHEN "111", "0000" WHEN OTHERS ;
Microprocessors & Digital Systems Laboratory © 2009 National Technical University of Athens
0000 WHEN OTHERS ; END dataflow ;
Behavioral Description LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec2to4 ISENTITY dec2to4 IS
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;
END dec2to4 ;END dec2to4 ;
PROCESS ( w En )PROCESS ( w, En ) BEGIN
IF En = '1' THEN CASE w IS
WHEN "00" => y <= "1000" ;WHEN 00 => y <= 1000 ; WHEN "01" => y <= "0100" ; WHEN "10" => y <= "0010" ; WHEN OTHERS => y <= "0001" ;
END CASE ;END CASE ; ELSE
y <= "0000" ; END IF ;
END PROCESS ; END Behavior ;
7 Segment Displayg y LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY seg7 IS
PORT ( bcd : IN STD LOGIC VECTOR(3 DOWNTO 0) ;PORT ( bcd : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; leds : OUT STD_LOGIC_VECTOR(1 TO 7) ) ;
END seg7 ; ARCHITECTURE Behavior OF seg7 IS BEGINBEGIN
PROCESS ( bcd ) BEGIN
CASE bcd IS -- abcdefg WHEN "0000" => leds <= "1111110" ;WHEN 0000 leds 1111110 ; WHEN "0001" => leds <= "0110000" ; WHEN "0010" => leds <= "1101101" ; WHEN "0011" => leds <= "1111001" ; WHEN "0100" => leds <= "0110011" ;WHEN 0100 leds 0110011 ; WHEN "0101" => leds <= "1011011" ; WHEN "0110" => leds <= "1011111" ; WHEN "0111" => leds <= "1110000" ; WHEN "1000" => leds <= "1111111" ;WHEN 1000 leds 1111111 ; WHEN "1001" => leds <= "1110011" ; WHEN OTHERS => leds <= "-------" ;
END CASE ; END PROCESS ;
END PROCESS ; END Behavior ;
AeqB : OUT STD_LOGIC ) ; END compare1 ;
ARCHITECTURE Behavior OF compare1 IS BEGIN
PROCESS ( A, B ) BEGIN
END PROCESS ; END Behavior ;
END Behavior ;
Latch Inference LIBRARY ieee ; USE ieee.std logic 1164.all ;_ g _ ;
ENTITY implied IS PORT ( A B : IN STD LOGIC ;PORT ( A, B : IN STD_LOGIC ;
AeqB : OUT STD_LOGIC ) ; END implied ;
ARCHITECTURE Behavior OF implied IS BEGIN
PROCESS ( A B )PROCESS ( A, B ) BEGIN
IF A = B THEN AeqB <= '1' ;
END IF ; END PROCESS ;
END Behavior ;
Latch Inference
Combinational Circuits with Processes
Rules that need to be followed:
1. All inputs to the combinational circuit should be includedincluded in the sensitivity list
2. No other signals should be included g in the sensitivity list
3. None of the statements within the process should be sensitive to rising or falling edges
4. All possible cases need to be covered in the internal IF and CASE statements in order to avoidIF and CASE statements in order to avoid implied latches
Microprocessors & Digital Systems Laboratory © 2009 National Technical University of Athens
Covering all Combinations with IFg
Using ELSE
ELSE AeqB <= '0' ;
Using default values
AeqB <= '1' ;
Covering all Combinations with CASEg
Using WHEN OTHERS CASE ISCASE y IS
WHEN S1 => Z <= "10"; WHEN S2 => Z <= "01";
CASE y IS WHEN S1 => Z <= "10"; WHEN S2 => Z <= "01";WHEN S2 Z 01 ;
WHEN OTHERS => Z <= "00"; END CASE;
WHEN S3 => Z <= "00"; WHEN OTHERS => Z <= „--";
END CASE;
Z <= "00"; CASE y IS
WHEN S1 => Z <= "10";WHEN S1 => Z <= 10 ; WHEN S2 => Z <= "10";
END CASE;
Sequential Logic: D Latchg Truth table Graphical symbol
Clock D 0 1
Timing diagram
Time
Clk D
0 1
0 1
Timing diagram Q(t)
Time
LIBRARY ieee ; USE ieee std logic 1164 all ;USE ieee.std_logic_1164.all ;
ENTITY latch IS PORT ( D Clock : IN STD LOGIC ;
D Q
END latch ;
PROCESS ( D, Clock ) ( ) BEGIN
END IF ; END PROCESS ;
VHDL Code: D Flip-flop
LIBRARY ieee ; USE ieee std logic 1164 all ;USE ieee.std_logic_1164.all ;
ENTITY flipflop IS PORT ( D, Clock : IN STD LOGIC ;
D Q
END flipflop ;
PROCESS ( Clock ) BEGIN
END IF ; END PROCESS ;
VHDL Code: D Flip-flop
LIBRARY ieee ; USE ieee std logic 1164 all ;USE ieee.std_logic_1164.all ;
ENTITY flipflop IS PORT ( D, Clock : IN STD LOGIC ;
D Q
END flipflop ;
PROCESS ( Clock ) BEGIN
END IF ; END PROCESS ;
VHDL Code: D Flip-flop
LIBRARY ieee ; USE ieee.std_logic_1164.all ;
ENTITY flipflop IS PORT ( D Cl k IN STD LOGIC
D Q
END flipflop ;
PROCESSPROCESS BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ; Q <= D ;Q < D ;
END PROCESS ; END Behavior_2 ;
VHDL Code: D Flip-flop
LIBRARY ieee ; USE ieee std logic 1164 all ;USE ieee.std_logic_1164.all ;
ENTITY flipflop IS PORT ( D Clock : IN STD LOGIC ;
D Q
END flipflop ;
PROCESSPROCESS BEGIN
END PROCESS ; END Behavior_2 ;
VHDL Code: D Flip-flop Async Resety LIBRARY ieee ; USE ieee.std_logic_1164.all ;
ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ;
Q : OUT STD LOGIC) ;
Clock
Resetn
PROCESS ( Resetn, Clock ) BEGINBEGIN
IF Resetn = '0' THEN Q <= '0' ;
ELSIF Clock'EVENT AND Clock = '1' THENELSIF Clock EVENT AND Clock 1 THEN Q <= D ;
END IF ; END PROCESS ;
; END Behavior ;
VHDL Code: D Flip-flop Sync Resety LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fli fl ISENTITY flipflop IS
PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ;
END flipflop ;
D Q
ClockEND flipflop ;
Clock
Resetn
BEGIN PROCESS BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;WAIT UNTIL Clock EVENT AND Clock 1 ; IF Resetn = '0' THEN
Q <= '0' ; ELSEELSE
; END Behavior ;
Variables: Example
ENTITY Numbits IS PORT ( X : IN STD_LOGIC_VECTOR(1 TO 3) ;
Count : OUT INTEGER RANGE 0 TO 3) ; END Numbits ;
Microprocessors & Digital Systems Laboratory © 2009 National Technical University of Athens
Variables: Example
BEGIN
PROCESS(X) – count the number of bits in X equal to 1PROCESS(X) count the number of bits in X equal to 1 VARIABLE Tmp: INTEGER;
BEGIN Tmp := 0;p 0; FOR i IN 1 TO 3 LOOP
IF X(i) = ‘1’ THEN Tmp := Tmp + 1;p p
END IF; END LOOP; Count <= Tmp;
END PROCESS;
END Behavior ;
Variables: Features
Can only be declared within processes and subprograms (functions & procedures)subprograms (functions & procedures)
Initial value can be explicitly specified in the Initial value can be explicitly specified in the declaration
When assigned take an assigned value immediately
Variable assignments represent the desired behavior, not the structure of the circuit
Should be avoided, or at least used with caution in a synthesizable code
Microprocessors & Digital Systems Laboratory © 2009 National Technical University of Athens
synthesizable code
BEGIN
PROCESS(X) – count the number of bits in X equal to 1PROCESS(X) count the number of bits in X equal to 1 VARIABLE Tmp: INTEGER;
BEGIN Tmp := 0;p 0; FOR i IN 1 TO 3 LOOP
IF X(i) = ‘1’ THEN Tmp := Tmp + 1;p p
END IF; END LOOP; Count <= Tmp;
END PROCESS;
END Behavior ;
Microprocessors & Digital Systems Laboratory © 2009 National Technical University of Athens
Variable vs Signal – Signal Exampleg g ARCHITECTURE Behavior OF Numbits IS
SIGNAL Tmp : INTEGER RANGE 0 TO 3 ;
BEGIN
PROCESS(X) – count the number of bits in X equal to 1 BEGIN
Tmp <= 0; FOR i IN 1 TO 3 LOOP
IF X(i) = ‘1’ THEN 1Tmp <= Tmp + 1;
END IF; END LOOP; C t < TCount <= Tmp;
END PROCESS;
END Behavior ;
END Behavior ;
LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY NANDn IS GENERIC (n: INTEGER := 8) PORT ( X : IN STD_LOGIC_VECTOR(1 TO n);
Y : OUT STD_LOGIC); END NANDn;
Microprocessors & Digital Systems Laboratory © 2009 National Technical University of Athens
Variable vs Signal: NAND Gate - Varg ARCHITECTURE behavioral1 OF NANDn IS BEGINBEGIN
PROCESS (X) VARIABLE Tmp: STD LOGIC;VARIABLE Tmp: STD_LOGIC;
BEGIN Tmp := X(1);
AND_bits: FOR i IN 2 TO n LOOP Tmp := Tmp AND X( i ) ;
END LOOP AND bitEND LOOP AND_bits ;
Y <= NOT Tmp ;
END behavioral1 ;
Variable vs Signal: NAND Gate - Signalg g ARCHITECTURE behavioral2 OF NANDn IS
SIGNAL Tmp: STD LOGIC;SIGNAL Tmp: STD_LOGIC; BEGIN
PROCESS (X)PROCESS (X) BEGIN Tmp <= X(1);
AND_bits: FOR i IN 2 TO n LOOP Tmp <= Tmp AND X( i ) ;
END LOOP AND bitEND LOOP AND_bits ;
Y <= NOT Tmp ;
END behavioral2 ;
ARCHITECTURE dataflow1 OF NANDn ISARCHITECTURE dataflow1 OF NANDn IS
SIGNAL Tmp: STD_LOGIC_VECTOR(1 TO n);
BEGIN Tmp(1) <= X(1);
AND_bits: FOR i IN 2 TO n GENERATE Tmp(i) <= Tmp(i-1) AND X( i ) ;
END LOOP AND_bits ;
QuestionsQuestions
Structural VHDL
Major instructions
(for-generate)( g ) component instantiation with generic
(generic map, port map)(g p, p p)
Microprocessors & Digital Systems Laboratory © 2009 National Technical University of Athens
Structural VHDL
Major instructions
p (p p) component instantiation with generic
(generic map, port map)(g p, p p) generate scheme for component instantiations
(for-generate)( g )
Structural VHDL: Example s(0)
y 0
s(1)
Microprocessors & Digital Systems Laboratory © 2009 National Technical University of Athens
VHDL Code for 2-to-1 Multiplexer
LIBRARY ieee ;LIBRARY ieee ; USE ieee.std_logic_1164.all ;
ENTITY mux2to1 IS PORT (w0, w1, s : IN STD_LOGIC ;
f OUT STD LOGIC )f : OUT STD_LOGIC ) ;…