1

A 252Kgates/4.9Kbytes SRAM/71mW Multi-Standard

Video Decoder for High Definition Video Applications Motivation

A variety of video coding standardsIncreasing demands on versatile multimedia

devices Target

A multi-standard video decoder for real-time HD video (HD1080) applications

Design Goals Low hardware cost Low memory bandwidth

2

Proposed Techniques Reducing design complexity

Hybrid block level pipeline control Shared adder-based filter structure

Reducing memory bandwidth Hybrid block access Dual block access

Reducing memory access latencyOptimized 2-D block accessLow latency memory control scheme

Reducing 37~56% memory bandwidth

Reducing 40~60% complexity

Reducing 38~41% memory bandwidth

3

Chip Summary Chip implementation

Chip prototyping

HTDHPC

HVLD

System Controller

AG

AHB I/F

ILF

RDM

Acknowledgements National Science Council, Taiwan Minister of Economic Affairs, Taiwan Chip Implementation Center, Taiwan

Technology TSMC 0.13 m CMOS 1P8M

Core Area 4.2x1.2mm2

Logic Gates 252K (2-input NAND gate)

SRAM 4.9KB

Decoding standards

JPEG/MPEG-1/2/4/H.264

Operating Frequency

20MHz for D1

120MHz for HD1080

Power Consumption

7.9mW for D1 (0.8V)

71.1mW for HD1080 (1.0V)