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1.3 V low close-in phase noise NMOS LC-VCO with parallel PMOS transistors

Moon, H.; Nam, I.;Electronics LettersVolume 44, Issue 11, May 22 2008 Page(s):676 - 678 Digital Object Identifier 10.1049/el:20080404

Student : ming-long chuangDate:12/28/2009

National Changhua University Department of Graduate Institute of Integrated Circuit Design

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Outline

Abstract INTRODUCTION Circuit design Experimental results Conclusion

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Abstract A new NMOS cross-coupled LC-VCO with paralle

l PMOS transistors is proposed. The proposed LC-VCO is useful for suppressing flicker noise up conversion and very suitable for low voltage application.

It is implemented in 0.18 mm CMOS technology.

Measured phase noise is -93 dBc/Hz at 100 kHz and -116 dBc/Hz at 1 MHz offsets and its core current is only 2 mA for a 1.3 V supply voltage..

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INTRODUCTION The 1/f^3-shaped phase noise close to the carri

er in a CMOS LC VCO is dominated by flicker noise up conversion.

The two major mechanisms are the 1/f noise in the tail current source transistor and the differential pair FETs .

Recent reports have elaborated various techniques for suppressing the 1/f noise up conversion in CMOS LC oscillators.

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INTRODUCTION To suppress flicker noise up conversions

from a bias transistor and a differential pair, we need to replace a bias transistor with a poly silicon resistor that has no 1/f noise.

In addition, a decoupling capacitor can be used to obtain a negligible second-harmonic voltage at the source nodes as a source-coupled multi vibrator .

Two inductors are needed to provide a high level of impedance without degrading the Q-factor of the LC tank .

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INTRODUCTION The complementary LC-VCO, which is used

to exploit the symmetry of the oscillator circuit, is also useful because it can minimize the up conversion gain of low frequency noise .

This Letter propose a new technique for suppressing flicker noise up conversion in an LC-VCO. It is viable for a low supply voltage because the stacked PMOS transistors are not required to maintain a symmetric waveform characteristic.

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Circuit design To improve the close-in phase noise

characteristic of an NMOS LC-VCO, we focus on a differential pair.

The flicker noise of the differential pair modulates the second-harmonic voltage waveform at its common-source node.

To suppress the 1/f noise up conversion from differential pair transistors, we propose an NMOS LC-VCO structure with parallel PMOS transistors.

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Circuit design Schematic of proposed LC-VCO

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Circuit design Voltage waveforms at tail current-source node

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Circuit design Phase noise characteristics with ideal current source

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Circuit design Phase noise characteristics including 1/f noise of tail

bias transistor

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Experimental results The proposed NMOS LC-VCO with parallel

PMOS transistors was designed and fabricated in 0.18 mm CMOS process. To verify the performance of the proposed LC-VCO and to compare it with a conventional complementary LC-VCO, we implemented two LC-VCO under the same conditions, such as an LC tank and a bias current.

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Experimental results Chip photograph of proposed LC-VCO

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Experimental results Measured phase noise performance of proposed LC-

VCO and complementary LC-VCO

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Conclusions The proposed NMOS LC-VCO with parallel

PMOS transistors can reduce flicker noise up conversion from differential pair transistors and tail bias current transistors.

The proposed LC-VCO is fabricated in 0.18 mm CMOS process, and has a low close-in phase noise performance and is very suitable for a low supply voltage.

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Thank you for your attention