09 Manufacturing Process - Universiti Tunku Abdul Rahmanstaff.utar.edu.my/limsk/semiconductor technologies... · 9 Manufacturing Process - 2 - d s x ρ ρ= (9.1) Using a four-point

UNIVERSITI TUNKU ABDUL RAHMAN

Semiconductor

Technologies

Manufacturing Process

Dr. Lim Soo King

1/20/2012

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Chapter 9 ..............................................................................................1

Manufacturing Process .......................................................................1 9.0 Introduction ................................................................................................1 9.1 Analytical Measurements ..........................................................................1

9.1.1 Morphological Measurements ............................................................................1 9.1.2 Electrical Measurements .....................................................................................2 9.1.3 Chemical and Structural Measurements ...........................................................5 9.1.4 Mechanical Measurements ..................................................................................5

9.2 Assembly Techniques and Processes ........................................................6 9.2.1 Wafer Preparation ...............................................................................................7 9.2.2 Die Attach .............................................................................................................8

9.2.2.1 Eutectic Die Attach ............................................................................................................ 9 9.2.2.2 Epoxy Die Attach ............................................................................................................... 9

9.2.3 Wire Bonding......................................................................................................10 9.2.4 Molding/Glass Seal.............................................................................................11 9.2.5 Post Mold Cure/Leak Check .............................................................................13 9.2.6 Solder Dip/Tin Plate...........................................................................................13 9.2.7 Trim/Form ..........................................................................................................14 9.2.8 Inspection ............................................................................................................15

9.3 Packaging ..................................................................................................15 9.3.1 Electrical requirements .....................................................................................16 9.3.2 Mechanical and Thermal properties ................................................................16 9.3.3 Cost ......................................................................................................................17 9.34 Packaging Materials ...........................................................................................17 9.3.5 Interconnect Levels ............................................................................................17

9.3.5.1 Interconnect Level 1 - Die-to-Package-Substrate.......................................................... 18 9.3.5.2 Interconnect Level 2 - Package Substrate to Board...................................................... 20 9.3.5.3 Multi-Chip Modules - Die to Board................................................................................ 22 9.3.5.4 Thermal Consideration in Packaging ............................................................................ 24

9.4 Constraint of Design and Testing Concept............................................25 9.4.1 Constraint of Design ..........................................................................................26

9.4.1.1 Design Rule Checking......................................................................................................26 9.4.1.2 Layout versus Schematic ................................................................................................. 27 9.4.1.3 Latch-Up and Electrostatic Discharge ........................................................................... 27 9.4.1.4 Electrical Rule Checking ................................................................................................. 30

9.4.2 Testing Concepts ................................................................................................30 9.4.3 Automatic Test Equipment, Test Fixture, Test Program, and Automatic

Test Handler ......................................................................................................35 9.4.3.1 Automatic Test Equipment ............................................................................................. 35 9.4.3.2 Test Fixture ...................................................................................................................... 36 9.4.3.3 Automatic Test Handler .................................................................................................. 38

Exercises..........................................................................................................39 Answers of Exercises......................................................................................40 Bibliography ...................................................................................................42

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Figure 9.1: Cross sectional view of an n+ diffusion-to-aluminum contact showing current

crowding and current transfer length .................................................................3 Figure 9.2: The top view of a simple cross-bridge Kelvin structure used for measuring the

contact resistance ...............................................................................................4 Figure 2.3: Generic electronics packaging assembly sequence for plastic and ceramic

package ..............................................................................................................7 Figure 9.4: The basic structure of a silicon device die attach with a metal preform............9 Figure 9.5: Structure of ceramic dual inline package (cerdip) showing the base, the lead

frame and a lid with sealing glass ....................................................................11 Figure9.6: Schematics of a multi-pot transfer-mold system showing small mold

compound tablets with each large enough to fill a few cavities containing plastic strips .....................................................................................................13

Figure 9.7: Molded plastic package strip showing short between tips of the lead, tight bar and guide pin hole............................................................................................14

Figure 9.8: The formed molded plastic dip package strip shows that tight bar has not been removed............................................................................................................14

Figure 9.9: Rent’s constant for varies class of chip and system Figure .............................16 Figure 9.10: Interconnect hierarchy in traditional integrated circuit packaging ..................18 Figure 9.11: Wiring bonding connecting pad and lead ........................................................18 Figure 9.12: Typical conductance and inductance of package type and wire ......................19 Figure 9.13: Automated tap bonding (a) polymer with imprinted wire pattern and (b) die

attach using solder bump .................................................................................19 Figure 9.14: Flip-chip bonding.............................................................................................20 Figure 9.15: Printed circuit board mounting approach. (a) through-hole mounting and (b)

surface mounting..............................................................................................20 Figure 9.16: Commonly use package (1) leadless carrier, (2) DIP, (3) PGA, (4) small

outline IC, (5) quad flatpack, and (6) PLCC....................................................21 Figure 9.17: Parameters of various chip carriers..................................................................22 Figure 9.18: Ball grid array packaging; (a) cross-section, (b) photo of PGA bottom..........22 Figure 9.19: An Avionics processor module. Courtesy of Rockwell International .............23 Figure 9.20: The results of DRC for a silicon layout ...........................................................27 Figure 9.21: The refilled deep trench isolation between p-well and n-well isolations used to

reduce the occurrence of latch-up ....................................................................28 Figure 9.22: Illustration of n-well and p-substrate bias to prevent occurrence of latch-up..29 Figure 9.23: The flowchart of probe test and grading of die................................................32 Figure 9.24: A typical test flow of space/military grade VLSI device.................................34 Figure 9.25: A VLSI automatic test equipment showing test head and a mounted load board

..........................................................................................................................35 Figure 9.26: A top-view of a load board showing socket at the center to be mounted on the

ATH .................................................................................................................37 Figure 9.27: The picture shows a PLCC automatic test handler ..........................................38

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Chapter 9

Manufacturing Process _____________________________________________

9.0 Introduction In integrated circuit manufacturing process involves design, fabrication, assembly, and test processes. Besides these processes and quality control at in process step, analytical measurement is also needed to ensure physical and electrical parameters are in compliance with specifications. In this chapter student will learn analytical measurement steps, assembly process, and test process.

9.1 Analytical Measurements Analytical measurements normally are done in progress of integrated circuits fabrication or after the integrated circuits are fabricated. The purpose of the measurement is to ensure that the integrated circuits are fabricated according to the specifications such as right resistivity, right doping concentration etc. The analytical measurements include morphological, electrical, imaging, chemical, structural, and mechanical measurements. Normally the measurements made are thickness of oxide, sheet and contact resistance of interconnect including its reliability, thermal coefficient of expansion, surface state and structural information of the metallization and etc.

In section, student will learn the parameters that are measured, the measurement methods, and the techniques employed to achieve these measurements including the analysis of the results.

9.1.1 Morphological Measurements The morphology of material or structure refers to the thickness, surface roughness, and grain size of the material. The thickness of dielectric layer is usually measured using optical method. The properties of the interconnect layer is common measured using stylus/etch step or electrical resistance measurement methods.

The surface resistivity ρs is equal to resistivity ρ of the material divided by the thickness xd of the material, which is equal to equation (9.1).

9 Manufacturing Process

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d

s xρ=ρ (9.1)

Using a four-point probe measurement method probed on a test wafer, the thickness xd can be known, the sheet resistivity ρs is therefore is known with the known resistivity of the material. The test wafer normally has the interconnect material deposited at the same time with the device fabrication. Other methods that can be used to measure the thickness are acoustic or sonar measurement including laser generated sound wave and echo detection system. The good point of this method is that it does require test wafer because it is a non-destructively method that does not damage the metal interconnect line.

Surface roughness or local non-uniformity of interconnect material can be measured by either the stylus method or atomic force microscopy AFM. This method has extremely sharp tip scan over the surface and its vertical deflection is measured accurately using laser technique or piezoelectric sensor. The measurement sensitivity is high that the grain size can be determined. 9.1.2 Electrical Measurements The main electrical measurements made on the fabricated structure are the sheet resistance and contact resistance of the interconnect material, and the breakdown voltage of the dielectric material. In additional these measurements, reliability of the interconnect material is often measured electrically by accelerated electro-migration measurement.

The sheet resistance of the interconnect material directly affects electrical performance of the integrated circuit. As mentioned earlier, this parameter can be measured using four-point probe measurement or it can be measured using a resistor structure. The grain size of polycrystalline film also affects the resistivity. The smaller the grain size, the higher is the resistivity due more electrical scattering at the gain boundary. Depending on the crystal structure of titanium silicide TiS2, C49 phase has higher resistivity than C54 phase.

The contact resistivity ρc is not measured directly. Usually the contact

resistance RC is measured to deduce the contact resistivity. It is done by measuring the current I through the contact for a given voltage V across the contact interface. The contact resistivity ρC is then calculated using equation (9.2).

9 Manufactutring Process

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I

AVARCC ==ρ (9.2)

where A is the cross sectional area of the contact and contact resistance RC is also equal to V/I However, the cross sectional area of the contact can be highly non-uniform.

Figure 9.1 shows the cross section of an n+ diffusion-to-aluminum contact. The current flows to the aluminum metallization from the left of the contact to the right of the contact. Since the resistance of n+ diffusion is larger than the resistance of aluminum, current tends to flow closed to the left of n+ diffusion to aluminum due to lower series resistance at the left not at the right due larger series resistance. This phenomenon is also called current crowding like the case of current flow from emitter-to-base of a bipolar junction transistor. As a result, the effective cross sectional area of the contact decreases. Since the current is crowded at the left side of the n+ diffusion region, there is a transfer length li for the current, which is defined as

S

Ci σ

ρ=l (9.3)

where σS is the resistivity of semiconductor and ρC is the contact resistivity. Transfer length is also defined as the length from the edge of the contact to the place where the current density drops by 1/q of the current density at the edge.

Figure 9.1: Cross sectional view of an n+ diffusion-to-aluminum contact showing current

crowding and current transfer length Cross-bridge Kelvin structure is one of the many test structures used to measure the contact resistance. The simplest and the most common type is shown in Fig. 9.2. The voltage between point 1 and point 4 is measured at the right angle to the current flow I23 between point 2 and point 3 so that the average voltage V14


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is measured across the contact. The contact resistance Rk can then be calculated using equation (9.4).

2C

23

14C I

VR

l

ρ== (9.4)

where l2 is contact area of the via connecting the n+ diffusion and the aluminum metal.

The quality of the dielectric material is usually defined by its breakdown voltage or field strength. In the measurement, a voltage is applied across the dielectric layer and is ramped up at a constant rate. The voltage is monitored and at a certain where the voltage drops abruptly. This is the voltage where the dielectric breakdown, which is the breakdown voltage of the dielectric.

The common reliability problem found in aluminum line is void or hillock

formation. The reliability of aluminum lining can be done by electrical test. Measuring the electrical resistance would help to determine the condition of the aluminum lining. High resistance shall mean there is void etc.

Figure 9.2: The top view of a simple cross-bridge Kelvin structure used for measuring the

contact resistance


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9.1.3 Chemical and Structural Measurements There are many techniques can be utilized to obtain the chemical and structural information from the aluminum structure. The chemical information relates to the chemical or composition of the film including the doping concentration and its distribution. Structural information regarding about the micro-structure of the material can known from the lattice constant, density of the material, and crystallographic information.

Low angle or glancing X-ray Diffraction XRD is often used for structural measurements. By analysis the constructive and destructive interference of X-ray scattered from the thin film that can determine the lattice constant, orientation identification, also the stress level. Other method such as Electron Back-Scattering Diffraction EBSD can be used to find out the crystallographic orientation of the individual grains of aluminum interconnect line based on the diffraction pattern is generated on the screen.

Dielectric properties of the film particularly the dielectric constant can be

measured by ellipsometry. The density of film can be measured using buffered hydrofluoric acid HF by measuring the etching rate of the dielectric material. Similarly measuring the etching rate can be used to determine the phosphorous content in the phosphosilicate glass PSG film.

Pertaining to composition of the thin film, many techniques can be used to

determine it including Auger electron Spectroscopy AES, Rutherford Backscattering Spectrometry RBS, and Fourier Transform Infrared Spectroscopy FTIS methods.

9.1.4 Mechanical Measurements Stress developed in aluminum interconnecting layers and structures can generally affect the physical integrity of aluminum. This would lead to failure due to crack and loss of adhesion and reliability problem. A common source of stress is due to difference in the coefficient of thermal expansion CTE of the materials being used. The obvious one is deposition of aluminum on silicon diffusion region. Owing to hot and cold temperature, the expansion and shrinking of the films are different that would create adhesion and crack problem.

Another type of stress is the intrinsic stress. This type of stress is present after deposition at room temperature. At depositing temperature, there is


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difference in lattice constants between the film and the substrate material to deposited on, energetic ion bombardment, or gas or precipitation inclusion in the film. When temperature is a room temperature the stress level created is different due to both intrinsic and difference in coefficient of thermal expansion CTE.

A common ways to determine stress in the film is by measuring how much

the substrate bends after the film is being deposited. The amount of bending is dependent on Young’s modulus and Poisson ratio of the film. By measuring the amount of bend, with known mechanical constants like Young’s modulus and Poisson ratio, the stress level can be calculated.

9.2 Assembly Techniques and Processes This section describes the basic assembly processes and techniques used for assembly ceramic and plastic packaged VLSI device. The processes cover a number of assembly steps from wafer preparation through die attach, including wire bonding, encapsulation/molding, stabilization bake/post mold bake, temperature cycle to tin plating/solder plating, trim/form, and inspection. Student will learn these process steps based on the generic assembly sequence shown in Fig. 9.3 and at the same time understanding the physics of technique for process step.

The generic assembly process steps are mainly for ceramic and plastic packaged integrated circuit or die. The first step is the preparation of wafer step, which basically cuts and separates the die from the wafer. The second process step is the die attach. It is a process step that bonding the die to the paddle of the package. The third step is the wire bonding, which is the process of connecting the bond pad on the die to the lead of the package. This step allows the die to be connected to external world. Encapsulation is the step involves closing the die from the interference of external contaminant and protecting from damage etc. The encapsulation can be done by mean of molding for the plastic package or glass seal the lid of the package to the hermetic ceramic package. Post mold cure or baking process is a necessary step to cross linked the plastic resin material to provide hardening effect. Owing to high temperature process, lead of package would be tarnished due to heat. The next process step is either tin plate or solders plate, which involves removing the oxide and plating the leads for preventing oxidation and providing good solderability connecting contact to the circuit board. The second last process step involves removing the shorting bar from the hermetic package, or trims and forms the plastic package. The last process step is an inspection step that involves removing of the non-compliance


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device such as lead problem, package crack etc from the from the production batch.

Figure 2.3: Generic electronics packaging assembly sequence for plastic and ceramic package

9.2.1 Wafer Preparation Thickness of the fabricated wafer is normally around 650µm. It needs to be thinned before the assembly begins. Depending on the package style that the


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integrated circuit to be housed, it can be thinned to approximately 400µm. The thinning is necessary to reduce thermal stress due to mismatch of the coefficient of thermal expansion CTE between the silicon die and the packaging material . Again depending on the type of packaging material, the back-side of the wafer may require metallization deposition consisting of multilayer metallic elements like gold-nickel-silver Au-Ni-Ag or titanium-nickel-silver Ti-Ni-Au in order from silicon side. This helps in thermal conduction between the silicon die and the package, and provides the superior adhesion strength and electrical connection.

Every integrated circuit in the wafer is probed electrically to check its functionality. The malfunction dies are marked with a drop of red ink that they can be sorted out during die attach or die bonding process. Different color inking schemes may be adopted to distinguish between commercial/industrial compliance die and military compliance die. One of the schemes is to ink the die with green color for commercial/industrial compliance die, no color is to be used for military compliance die, and red color for fail die.

The probed wafer is then adhesively mounted to a tape that has been pre-

assembled to a frame using a wafer dispenser. The frame is then mounted on the dicing machine with a diamond blade to cut the scribe line for separating the dice. The thickness of diamond blade is typically 25µm thick rotating at a speed of 20,000rpm cuts the wafer from 90.0% to 100.0% saw-through allowing dicing street as narrow as 60µm, which is closed to the width of scribe line of between dice. 100.0% saw-though is necessary for VLSI devices, which have large area because it reduces the chance of chipping at the edge during die separation breaking process. In the modern VLSI assembly, the 100% saw-through dice allow automatic picking of good dice with the aid of optical visual system during die attach. 9.2.2 Die Attach It is a process of attaching the die permanently to the paddle of lead frame or ceramic package. One of the important conditions of the die attachment process and several other processes is the requirements of high temperature and cooling down to room temperature. This would cause thermal stress due to the difference of coefficient of thermal expansion CTE of the silicon die and material of package. The results are crack on the die and metallization peeling off. Material that has CTEs close to that of silicon crystal is preferable in package construction. Choosing the packaging materials that have CTEs the same as that of silicon would be ideal reducing thermal stress to zero. In real


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situation, there is no such material that can provide perfect match with the silicon. However, in the industrial ceramic (Al2O3) substrate and Alloy 42 (42% nickel-58% iron alloy) lead frame have been used for many years due to close TCE match for hermetic-ceramic package and plastic package. However, Alloy 42 is no longer the only choice in today’s assembly. Copper alloy lead frame is preferred today for logic and microprocessor devices because copper alloy has approximately ten times the thermal conductivity of Alloy 42. It allows better heat transfer from the die to package via die attach material. 9.2.2.1 Eutectic Die Attach Figure 9.4 illustrates the fundamental aspect of a die attach. Eutectic chip die attach is metallurgically attached from the die to substrate material typically made from Alloy 42 or attached to a ceramic substrate (90-99.5% Al2O3). Metallization is often required on the back of the chip so that it is wettable by die attach perform. The perform is a thin sheet of thickness less than 0.05µm consisting of solder-bonding alloy such as 98% gold-2% silicon. The paddle and lead of the ceramic package is usually plated with gold, while the paddle and lead of the alloy 42 lead frame or copper alloys lead frame is plated with silver.

Figure 9.4: The basic structure of a silicon device die attach with a metal preform

During the die attach, the preform is placed on the paddle heated to about 3700C. Mechanical scrubbing is done so that the preform melts and reacts with silicon to form an Au-Si composition bond between the backside of the die and the substrate of the ceramic. The bonding is considered complete when the Au-Si composition structure becomes rich in silicon. 9.2.2.2 Epoxy Die Attach Silver filled epoxy adhesive is the choice of polymer based material for die attach. The silver filler usually would flake that makes epoxy electrically conductive and thermally conductive to allow good thermal path between die and the rest of the package. In VLSI assembly, epoxy is fed onto the substrate material through a multi-nozzle or single nozzle dispenser to ensure the required


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bond line thickness is created avoiding void. The back side of the die often does not require metallization because epoxy provides better adhesion with bare silicon or silicon dioxide. The process time of die attach usually is 1 to 2 seconds at room temperature. The epoxy is thermosetting polymers, after the die attach, it must be cured at elevated temperature to complete the die bond. The cure conditions range from 1250C to 1750C and require 1 to 2 hours. 9.2.3 Wire Bonding Wire bonding is the most common method for connecting the bond pads on the die to the leads of the package. Aluminum or gold wires are usually the choice because they bond well to the bond pads on the die and to the metallized part of the package forming Au-Al and Al-Ag metallurgical diffused materials. Gold or aluminum wire of diameter 25 to 30µm is balled and wedge bonded by thermosonic or thermocompression, where the ball is bonded to the bond pad made of aluminum and wedge-bonded at the lead plated with either gold or silver. The temperature of wire bonding for thermosonic ranges from 1500C to 2500C, while for thermocompression process, the temperature ranges from 3000C to 3500C.

The metallurgical diffusion primary follows equation X2 = Dt (9.5) ( )RT/QexpDD 0 −= (9.6)

where X is the diffusion thickness, D is the diffusion constant, t is the storage time, D0 is the frequency factor, Q is the activation energy, R is the gas constant, and T is the storage absolute temperature.

Gold and aluminum form a variety of inter-metallic with Au-Al first formed and gradually change to Au-Al4 that will degrade the bond strength. Following equation (9.5) and (9.6), Au-Al inter-metallic growth would be severed at elevated temperature especially the temperature of molding and hermetic glass seal. Thus, aluminum-aluminum wiring bonding at bond pad is preferred for high reliable products.

Besides, using gold and aluminum wires to interconnect bond pads of the

die to lead of package, copper bond wire is also used in today’s modern VLSI assembly due to a few obvious reasons. They are cost, electrical and thermal


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conductivity, less inter-metallic growths, and better reliability of bond at elevated temperature.

Copper costs 90% less than gold. It is obvious in terms of cost of assembly.

It costs less. Copper wire has electrical resistivity of 0.017x10-4Ω-cm, which is about 30% better than the resistivity of gold, which is 0.022x10-4Ω-cm. The low electrical resistivity of copper results in better electrical performance in particular for bonding high current device. Copper has thermal conductivity of 395m-1K-1, which 25% better than the thermal conductivity of gold, which is 316Wm-1K-1. Thus, copper wire dissipates heat within the package faster than gold wire, Thus, it minimizes the thermal stress.

Copper has a lower tendency to form inter-metallic compound with

aluminum. Unlike gold, it forms inter-metallic compound with aluminum especially at elevated temperature due to inter-diffusivity of gold and aluminum (bond pad) . It can create voids at the bond interface that would weaken the bond and can lead to bond lifting as well as other wire bond problems.

9.2.4 Molding/Glass Seal Upon completion of wire bonding, the next operation is either molding or glass seal process, which depending on the package style used. Glass seal refractory technology relies on glass sealing a lead between two pressed ceramics as illustrated in Fig. 9.5 using low temperature glass. The glass used for glass sealing is PbO-ZnO-B2O3 type. Sealing is usually done at temperature above 4000C in an oxidizing ambient to avoid deoxidizing the metallic components of the glass that would degrade the electrical insulation. For VLSI device, sealing at temperature greater than 4000C would cause additional thermal diffusion at the junction of transistor that would shift slightly the electrical characteristics of the die. Thus, choosing glass-sealing technology for sealing must be carefully.

Figure 9.5: Structure of ceramic dual inline package (cerdip) showing the base, the lead

frame and a lid with sealing glass


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Plastic encapsulation involves a number of techniques. For an example, in glob-top-coating, the post wire bonded die is coated with liquid plastic resin and the plastic are cured for the cross liking.

In VLSI plastic packaging, a pre-molding technique is sometimes used. This technology is the plastic equivalent of the refractory ceramic cavity package. The package is molded together with a lead frame forming a plastic body and cavity, whereby the die is attached and bond pads to lead are wire bonded.

The post molding technology is a transfer molding method using

thermosetting epoxy resins to mold around the frame-die assembly to form package body. The molding process has to be controlled carefully because this process is relatively harsh that the die and bond wire are exposed to viscous molding material that may cause wire sweeping or lifted wire.

The molding material that is epoxy resin is made by condensing

epichlorohydrin with bisphenol-A to produce a material called Epoxy-A. An excess of epichlorohydrin was used to leave epoxy groups on each end of low molecular weight polymer. Today NOVOLAC epoxy is general preferred due to its higher functionality that makes heat resist.

The molding compound is usually pre-heated and transferred into pots of

large multi-cavity mold. After it enters the pot, the molding compound melts under pressure and heat, flows to fill the mold cavities containing frame strips with their attached dice. For molding of VLSI die, which has large area, longer bond wire, the multi-pot molding as shown in Fig. 9.6 is preferred aiming to reduce damage of wire due to viscosity of the mold compound and incomplete mold due to partial cross linking.


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Figure9.6: Schematics of a multi-pot transfer-mold system showing small mold compound tablets with each large enough to fill a few cavities containing plastic strips

9.2.5 Post Mold Cure/Leak Check For plastic packaged device, post mold cure or baking process is a necessary step to cross linked the plastic resin material to provide hardening effect. The curing is normally done in an oven set at temperature 1500C for three hours of curing time. As for the hermetic package, cure is not necessary for the package. For ceramic packaged device, leak test is usually done to check if there is any glass seal problem or micro-crack of the ceramic package. The leak tests are divided into gross leak and fine leak tests. The gross leak test is easy. It is done by immersing the ceramic package into water like the way we check the leak of a car wheel. Fine leakage is done by placing the ceramic devices in the pressure compressed chamber containing radioactive source for 1 to 2 hours. The devices are then checked for fine leak with a α particle counter. If the counter shows count result, it means that there is fine leak due to micro-crack whereby it cannot be visually detected by naked eyes. 9.2.6 Solder Dip/Tin Plate Owing to high temperature process, lead of package would be tarnished due to heat. Thus, it is necessary to remove the oxide before either solder dip or tin plate is done depending on package type. The leads of plastic package are


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normally solder dipped, while the leads of hermetic package is normally tin plated or solder plated. Solder dip or tin plate is necessary to protect the base metal of the package from oxidation in order to preserve its solderability.

For plastic device, upon removing the oxide and extra mold fresh, the short between the tips of the lead between adjacent packages is removed as shown in Fig. 9.7 and the package is formed to the desire shape as shown in Fig. 9.8 for plastic dual in-line (DIP) package. The device strips are dipped with solder flux and then into solder bath so that solder will cover the non-oxidized bare-leads of the plastic device.

As for the ceramic package, it is normally tin plated or solder plated via electrolysis. It is normal electrolysis process, whereby the hermetic devices are hung in a bracket at the negative electrode of the plating bath filled with electrolyte.

Figure 9.7: Molded plastic package strip showing short between tips of the lead, tight bar

and guide pin hole

Figure 9.8: The formed molded plastic dip package strip shows that tight bar has not been

removed

9.2.7 Trim/Form One already knows that generally the device is assembled either in plastic package style or hermetic package style. The leads of the device are shorted with a tight bar with the aims to prevent lead bending and also to protect the die


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from damage due to electrostatic discharge ESD so that every lead is at same potential with no potential difference for electron discharge that would damage the die. The short between the tips of the leads is trimmed off using puncher. The device is then formed according to the package style such the dual inline package DIP as shown in Fig. 9.8. Take for an example, the lead of the package is formed into gull-wing style for single outline package SOP.

For plastic package, trim and form are performed before solder dip process. As for the hermetic package, form is normally not necessary, while trim is done after tin plating or solder plating process to remove the shorting bar connecting the tips of all leads. 9.2.8 Inspection The tight bar of the plastic device is removed to singulate device. Inspection is done to sort out non-conformance device such as lead defect, package crack, package chip, insufficient solder coverage etc. before loaded into tube. The tube or tray loaded devices is then transferred to test operation for initial and final tests.

9.3 Packaging

Integrated circuit package plays a fundamental role in the operation and performance of a component. Besides providing a mean of bringing electrical signal and voltage supply via wires in and out of the silicon die, it also removes heat generated by the circuit and provides mechanical support. Besides, it also protects the die integrated circuit against environmental conditions such as humidity and heat. Furthermore the package has a major impact on the performance and power dissipation of the integrated circuit like the microprocessor and signal processor. This influence is getting more pronounced as technology scaling down progressed due to reduction of internal signal delays and on-chip capacitance. Up to 50% of the delay of a high-performance computer is due to packaging delay caused by inductive and capacitive parasitic from packing material. The increasing complexity of circuit integrated into a single die also translates into a need for ever more input-output pins because the number of connections is roughly proportional to the complexity of the circuitry on the chip. This relationship was first observed by E. Rent of IBM, who translated it into an empirical formula called Rent’s rule. This formula relates the number of input/output pins P to the complexity of the circuit as measured by the number of gates.


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P = kGβ (9.7) where k is the average number of I/Os per gate, G the number of gates, and β the Rent exponent. β varies between 0.1 and 0.7. The value is strongly dependent on the application area, architecture, and organization of the circuit, as shown in Fig. 9.9.

It is clearly shown that microprocessors display a very different input/output behavior compared to memories. The observed rate of pin-count increase for integrated circuits varies between 8% to 11% per year and it has been projected that packages with more than 2,000 pins will be required by the year 2010. For all these reasons, traditional dual-in-line, through-hole mounted packages have been replaced by other approaches such as surface-mount, ball grid array, and multichip module techniques. It is useful for the circuit designer to aware of the available options, and their advantages and disadvantages.

Chip/System β K Static memory 0.12 6.00 Microprocessor 0.45 0.82 Gate array 0.50 1.90 High speed computer - chip 0.63 1.40 High speed computer -circuit 0.25 82.0

Figure 9.9: Rent’s constant for varies class of chip and system Figure Owing to its multi-functionality, a good package must comply with a large variety of requirements namely the electrical, mechanical, thermal, and cost requirements.

9.3.1 Electrical requirements The pins should exhibit low capacitance - both inter-wire and to the substrate, resistance, and inductance. Large characteristic impedance should be tuned to optimize transmission line behavior and observe that intrinsic integrated circuit impedances are high. 9.3.2 Mechanical and Thermal properties The heat removal rate should be as high as possible. Mechanical reliability requires a good matching between the thermal properties like the coefficient of thermal expansion CTE of the die-integrated circuit and the chip carrier. Long-term reliability requires a strong connection from die to package as well as from package to printed circuit board.


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9.3.3 Cost Cost is always one of the most important requirements. Ceramic package has a superior performance over plastic package but it is also substantially more expensive. Increasing the heat removal capacity of a package also tends to raise the package cost. The least expensive plastic package can dissipate up to 1.0W of heat. More expensive but still cheap plastic package can dissipate up to 2.0W. Higher heat dissipation requires more expensive ceramic package. Chips dissipating over 50.0W require special heat sink attachment. Extreme techniques such as fans and blowers, liquid cooling hardware, or heat pipes, are needed for higher dissipation levels.

Packing density is a major factor in reducing the cost of the printed circuit

board. The increasing pin count either requires an increase in the package size or a reduction in the pitch between the pins. Both have a profound effect on the cost of package.

9.34 Packaging Materials The most common materials used for the package body are ceramic and polymer plastic. The latter has the advantage of being substantially cheaper but suffers from inferior thermal properties. For instance, the ceramic alumina Al 2O3 conducts heat better than silicon dioxide SiO2 and the polyimide plastic by factors of 30 and 100 respectively. Furthermore, its coefficient of thermal expansion is closer to the typical interconnect metals.

The disadvantage of alumina and other ceramics is their high dielectric constant, which results in large interconnect capacitances. 9.3.5 Interconnect Levels The traditional packaging approach uses a two-level interconnection strategy. The die is first attached to an individual chip carrier or package. The package body contains an internal cavity where the chip is mounted. These cavities provide ample room for many connections between chip and leads. The leads compose the second interconnect level and connect the chip to the external interconnect medium, which is normally the printed circuit board. Complex systems contain even more interconnect levels, since boards are connected together using backplanes or ribbon cables. The first two layers of the interconnect hierarchy are illustrated in the drawing of Fig. 9.10.


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Figure 9.10: Interconnect hierarchy in traditional integrated circuit packaging

The interconnect techniques used at levels one and two of the interconnect hierarchy are shown here. 9.3.5.1 Interconnect Level 1 - Die-to-Package-Substrate Traditionally wire bonding is the technique of choice to provide an electrical connection between die and package. In this approach, the backside of the die is attached to the substrate using glue with a good thermal conductance. Next, the chip pads are individually connected to the lead frame with aluminum or gold wire. An example of wire bonding is shown in Fig. 9.11. Although the wire-bonding process is automated, it has some major disadvantages.

Figure 9.11: Wiring bonding connecting pad and lead

Wire must be attached serially one after the other. The lead time is longer with increasing pin counts. Larger pin counts make it substantially more challenging to find bonding patterns that avoid shorts between the wires. Bonding wire has inferior electrical properties such as a high individual inductance (5nH or more) and mutual inductance with neighboring signals. The inductance of a bonding wire is typically about 1.0nH/mm, while the inductance per package pin ranges


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between 7.0 and 40.0nH per pin depending on the type of package as well as the positioning of the pin on the package boundary. Typical values of the parasitic inductances and capacitances for a number of commonly used packages are summarized in Fig. 9.12.

Package Type Capacitance pF Inductance nH

68 pin plastic DIP 4 35 68 pin ceramic DIP 7 20 256 pin grid array 1-5 2-15 Wire bond 0.5-1 1-2 Solder bump 0.1-0.5 0.01-0.1

Figure 9.12: Typical conductance and inductance of package type and wire The exact value of the parasitic component is hard to predict because of the manufacturing approach and irregular outlay. New attachment techniques are being used as a result of these deficiencies. In one approach is called Tape Automated Bonding TAB. The die is attached to a metal lead frame that is printed on a polymer film typically polyimide as shown in Fig. 9.13(a). The connection between chip pad and polymer film is wired by solder bump as shown in Fig. 9.13(b). The tape can then be connected to the package body using a number of techniques. One approach is using pressure connection.

(a) (b) Figure 9.13: Automated tap bonding (a) polymer with imprinted wire pattern and (b) die

attach using solder bump There are many advantages of the TAB process. Besides the process is highly automated, the sprockets in the film are used for automatic transport, and all wire connections are made simultaneously. The printed approach helps to reduce the wiring pitch, which results in higher lead counts. Elimination of the long bonding wires improves the electrical performance.


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Another approach is to flip the die upside down and attach it directly to the substrate using solder bumps. This technique, called flip-chip mounting, has the advantage of a superior electrical performance as shown in Fig. 9.14. Instead of making all the I/O connections on the die boundary, pads can be placed at any position on the chip. This can help to address the power and clock distribution problems, since the interconnect materials on the substrate are typically copper Cu or gold Au that have better quality than the aluminum (Al) on the chip.

Figure 9.14: Flip-chip bonding

9.3.5.2 Interconnect Level 2 - Package Substrate to Board When connecting the package to the printed circuit board PCB, through-hole mounting has been the packaging style of choice. A PCB is manufactured by stacking layers of copper and insulating epoxy glass. In the through-hole mounting approach, holes are drilled through the board and plated with copper. The package pins are inserted and electrical connection is made with solder as shown in Fig. 9.15(a). The traditional package in this class is the dual-in-line package DIP. The packaging density of the DIP degrades rapidly when the number of pins exceeds 64. This problem can be alleviated by using the pin-grid-array PGA package that has leads on the entire bottom surface instead of only on the periphery. PGA package can extend to large pin counts over 400 pins.

(a) (b) Figure 9.15: Printed circuit board mounting approach. (a) through-hole mounting and (b)

surface mounting The through-hole mounting approach offers a mechanically reliable and sturdy connection. However, the setback is the packaging density. For mechanical and sturdy reasons, a minimum pitch of 2.54mm between the through-holes is required. Even with this pitch, PGAs with large numbers of pins would also substantially weaken the printed circuit board. In addition, through-holes limit


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the board packing density by blocking lines that might otherwise have been routed below them, which results in longer interconnections. PGAs with large pin counts hence require extra routing layers to connect to the huge number of pins. Although the parasitic capacitance and inductance of the PGA are slightly lower than DIP, their values are still substantially large. These shortcomings of the through-hole mounting can be solved by using the surface mount technique. A chip is attached to the surface of the board with a solder connection without requiring any through-holes as shown in Fig. 9.15(b). Consequently, surface mount increases packing density due to elimination of through-holes mounting that provides more wiring space and mechanically strengthens the PCB. The lead pitch is reduced and chips can be mounted on both sides of the board.

The negative effects of the surface mount are many. The connection makes the connection of printed circuit board weak. It is also cumbersome to mount a component on a board that requires expensive mounting equipment, difficult for board repair, and finally testing of board is more complex because the package pins are no longer accessible at the backside of the board. Signal probing harder or even impossible.

A variety of surface mount packages is currently in use with different pitch

and pin count parameters. Four of these packages are shown in Fig. 9.16: the small-outline package SOIC with gull wings, the plastic leaded package PLCC with J-shaped leads, the leadless chip carrier LCC, and quad flat pack QFP.

Figure 9.16: Commonly use package (1) leadless carrier, (2) DIP, (3) PGA, (4) small outline

IC, (5) quad flatpack, and (6) PLCC An overview of the most important parameters for a number of packages is shown in Fig.9.17.


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Package Type Typical Lead Spacing Maximum Lead

Count Dual in Line DIP 2.54mm 64 Pin Grid Array PGA 2.54mm >300 Small Outline IC SOIC 1.27mm 28 Plastic Leadless Chip Carrier PLCC

1.27mm 124

Leadless Chip Carrier LCC 0.75mm 124

Figure 9.17: Parameters of various chip carriers Even surface mount packaging is unable to satisfy the quest for evermore higher pin counts. This is worsened by the demand for power connections in high performance chips, operating at low supply voltages, require as many power and ground pins as signal I/O. When more than 300 I/O connections are needed, solder balls replace pins as the preferred interconnect medium between package and board. An example of such a packaging approach, called ceramic ball grid array (BGA) is shown in Fig. 9.18. Solder bumps are used to connect both the die to the package substrate and the package to the board. The area array interconnect of the BGA provides constant input/output density regardless of the number of total package I/O pins. A minimum pitch between solder balls as low as 0.8mm can be obtained, and packages with multiple 1000’s of I/O signals are feasible.

(a) (b)

Figure 9.18: Ball grid array packaging; (a) cross-section, (b) photo of PGA bottom 9.3.5.3 Multi-Chip Modules - Die to Board The deep hierarchy of interconnect levels in the package is becoming unacceptable in modern complex circuit designs with higher levels of integration, large number of signals, and performance requirements. There is a need to reduce the number of levels.


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At the meantime, attention is focused on the elimination of the first level in the packaging hierarchy, which is eliminating die to package level by mounting the die directly on the wiring backplanes board or substrate. It offers a substantial benefit when performance or density is a major concern. This packaging approach is called multichip module MCM. As the result, there is a substantial increase in packing density as well as improved performance. A number of the previously mentioned die mounting techniques can be adapted to mount dice directly on the substrate. This includes wire bonding, Tape Automated Bonding TAB, and flip chip, although the later two are preferable. The substrate itself can be varying over a wide range of materials depending upon the required mechanical, electrical, thermal, and cost requirements. Materials of choice are epoxy substrates similar to printed circuit boards, metal, ceramics, and silicon. Silicon has the advantage of presenting a perfect match in mechanical and thermal properties with respect to the die material.

The main advantages of the MCM approach are; it increases packaging

density and and device’s performance. An example of an MCM module implemented using a silicon substrate; commonly dubbed silicon-on-silicon is shown in Fig. 9.19. The module that implements an avionics processor module and is fabricated by Rockwell International contains 53 ICs and 40 discrete devices on a 2.2″x2.2″ substrate with aluminum polyimide interconnect.

Figure 9.19: An Avionics processor module. Courtesy of Rockwell International

The interconnect wires of the module are only an order of magnitude wider than what is typical for on-chip wires because similar patterning approaches are used. The module itself has 180 I/O pins. Performance is improved by the elimination of the chip to carrier layer with variety of parasitic components, and


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through a reduction of the global wiring lengths on the die, a result of the increased packaging density. For instance, a solder bump has an assorted capacitance and inductance of only 0.1pF and 0.01nH respectively. The MCM technology can also reduce power consumption significantly, since large output drivers and associated dissipation become redundant due to the reduced load capacitance of the output pads.

While MCM technology offers some clear benefits, its main disadvantage is economic. This technology requires some advanced manufacturing steps that make the process expensive. The approach is only justifiable when either dense housing or extreme performance is essential. In the near future, this argument might become obsolete as MCM approaches proliferate. 9.3.5.4 Thermal Consideration in Packaging As the power consumption of integrated circuits rises, it becomes increasingly important to efficiently remove the heat generated by the dices. A large number of failure mechanisms in ICs are accentuated by increased temperatures. Examples are leakage in reverse biased diodes, electro-migration, and hot-electron trapping. To prevent failure, temperature of the die must be kept within certain ranges. The temperature range for commercial graded devices is between 0° and 70°C. Military parts are more demanding and require a temperature range varying from -55° to 125°C.

The cooling effectiveness of a package depends upon the thermal conduction of the package material, which consists of the package substrate and body, the package composition, and the effectiveness of the heat transfer between package and cooling medium.

As for the microprocessor device and other high performance device such

video device used in graphic card of a computer, thermal interface material TIM is used to reduce thermal impedance between the device and heat sink. TIM is a type of conductive paste used to fill any void or irregularity between the device and heat sink.

Standard packaging approaches use still or circulating air as the cooling medium. The transfer efficiency can be improved by adding finned metal heat sinks to the package. More expensive packaging approaches, such as those used in mainframes or super computers, force air, liquids, or inert gases through tiny ducts in the package to achieve even greater cooling efficiencies. As an example, a 40-pin DIP has a thermal resistance of 38°C/W and 25°C/W for


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natural and forced convection air. This means that a DIP can dissipate 2 watts (3 watts) of power with natural (forced) air convection, and still keep the temperature difference between the die and the environment below 75°C. For comparison, the thermal resistance of a ceramic PGA ranges from 15° to 30°C/W. Since packaging approaches with decreased thermal resistance are prohibitively expensive, keeping the power dissipation of an integrated circuit within bounds is an economic necessity. The increasing integration levels and circuit performance make this task nontrivial. An interesting relationship shown in equation (9.8) has been derived by Nagata. It provides a bound on the integration complexity and performance as a function of the thermal parameters.

E

T

t

N

p

G

θ∆≤ (9.8)

where NG is the number of gates on the chip, tp the propagation delay, ∆T the maximum temperature difference between chip and ambient environment, θ the thermal resistance between them, and E the switching energy of each gate.

Fortunately, not all gates are operating simultaneously in real systems. The maximum number of gates can be substantially larger, based on the activity coefficient in the circuit. For instance, it was experimentally derived that the ratio between the average switching period and the propagation delay ranges from 20 to 200 in mini- and large-scale computers.

Nevertheless, equation (9.8) demonstrates that heat dissipation and thermal

concern present an important limitation on circuit integration. Design approaches for low power that reduce either E or the activity coefficient are rapidly gaining importance.

9.4 Constraint of Design and Testing Concept In this section student will learn two concepts, which are constraints of design and test concepts. Constraints of design basically mentioning about limitations and restrictions while developing the design of an integrated circuit. In the test concepts, student will learn about test philosophy, methods, and strategies of testing VLSI integrated circuits so that they can be graded according to the sectors of applications namely commercial, industrial, and military/space applications.


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9.4.1 Constraint of Design In the design of VLSI integrated circuit (IC), a constraint of design refers to the limitations on the conditions under which the IC is developed or on the requirements of the IC such as its intended application. The constraint of design mainly can come from the function of the device or from the limitations of technology being used, materials properties, time taken to develop, overall costing, and etc. A constraint of design is normally imposed externally either by the organization or by external regulatory body. During design of integrated circuit, it is as important to identify each constraint of design as it is the requirement since the constraint of design places an overall boundary around the design process.

Let’s discuss some of technological limitations and constraints of device properties when designing an integrated circuit. We will also discuss the tools used to help in the development of the IC design with respect to these constraints and the methods used to overcome these constraints. 9.4.1.1 Design Rule Checking Every IC design technology has its own design rules. It consists of an interpretation about the possible geometrical implementation of the integrated circuit to be fabricated. These rules are given by foundry of IC fabrication, which often described in a document with polygon representing the layers available in that fabrication technology. It indicates the sizes, distance, and geometrical constraints allowed for a mentioned technology. Designer needs to execute a program called design rule check (DRC) to check if the design violating any rules defined by the foundry for that particular technology. This step of verification is as important as the simulation step of the design functionality. If design rules are not followed, the fabricated integrated circuit may have physical short such as metal short that would directly affect the electrical characteristic of the IC device. The device will fail gross function test at probe. Figure 9.20 illustrates the result of DRC applied to layout of an integrated circuit. The check finds that the polysilicon layer fails the design rule r(301), which is the spacing between polysilicon lines are too closed. It is less than 3λ spacing.


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Figure 9.20: The results of DRC for a silicon layout

9.4.1.2 Layout versus Schematic Layout versus schematic LVS is a tool to be used especially if the design is started with a schematic entry tool. The aim of the LVS tool is to check if the design at layout level corresponds to or consistent with the schematic drawing. Usually, the designer starts with a schematic drawing and then performs a simulation. If the simulation works are fine and complies with specifications of the device then only the designer will begin to design/draw the layout. However, in the case like full custom or semi-custom integrated circuit designs, the layout implementation of integrated circuit can differ from the schematic because of wrong simulation results or because of design errors that cannot be detected by simulation. LVS tool can then be used to check that if the designer designs/draws the layout according to the schematic drawing. To secure better results, a simulation of the layout using the same stimuli used for the schematic is preferred. Modern CAD software for VLSI designs is able to perform same type of simulation both at schematic design level and layout design/drawing level. 9.4.1.3 Latch-Up and Electrostatic Discharge Latch-up is an inherent problem of VLSI CMOS device due to presence of either parasitic bipolar junction transistor and substrate resistance. Indeed latch-up problem of an integrated circuit design has caused the delay of releasing the CMOS version IC device to the market in the electronic industry. Latch-up is also called silicon control rectifier(SCR effect and it can cause destruction of the integrated circuit or a part of the integrated circuit. In the severe case, it causes melting of bond wire due high current density. When latch-up occurred, the CMOS device becomes a switch on SCR whereby the power VDD line of the


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device is almost shorted to ground. Thus, high current density is registered that can burn the drain/source diffusion interface with substrate.

There is no real solution to solve this phenomena but a set of design techniques do exist to avoid the occurrence of latch-up such as the design the MOSFET sitting in its own isolated well and separately isolated the wells with refilled deep trench isolation between the wells as shown in Fig9.21.

Figure 9.21: The refilled deep trench isolation between p-well and n-well isolations used to

reduce the occurrence of latch-up The structure of n-MOSFET and p-MOSFET has two parasitic diodes form between drain/source and the substrate. An either npn or pnp parasitic bipolar junction transistor formed between the drain substrate and source depending on whether it is an n-MOSFET or p-MOSFET. In the case of wrong application of stimulant to the device such the input voltage is 0.7V (forward voltage of a diode) greater than the supply voltage (VDD), the voltage difference is sufficient enough to switch-on the emitter-to-base junction of the parasitic npn bipolar junction transistor. The consequence is the silicon-controlled rectifier SCR effect, would result a large current flowing from power supply (VDD) via a small value resistance between the collectors and emitters of pnpn thyristor structure. This high current will destroy the surrounding p-MOSFET and n-MOSFET and can melt the bond wire due to high current density.

Beside the isolation technique mentioned earlier to prevent the occurrence of latch-up, other most commonly used technique is to in-activate parasitic bipolar junction transistor by setting the emitter-to-base junction of the transistor to reverse bias mode. This is done by connecting n-well to power supply (VDD) voltage and connecting p-well and p-substrate to VSS ground rail. These techniques cannot totally eliminate the latch-up problem but it helps


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reducing its effect. The illustration of these techniques used in the layout is shown in Fig. 9.22

Figure 9.22: Illustration of n-well and p-substrate bias to prevent occurrence of latch-up

Another electrical constraint of the design is the problem of electrostatic discharge ESD. Owing to very small dimension of the MOSFET, its ESD susceptibility level is very low. Thus, handling CMOS integrated circuit device improperly can cause damage to due electrostatic charge generated by human being. One good way to prevent ESD is to ground people with a ground cord before handling ESD sensitive CMOS integrated circuit. Besides handling procedure, the designer usually designs in ESD protection circuit at the input circuit connecting to circuit at inner core of the device. A simple protection scheme is to connect two diodes at each input and output one connecting to supply voltage (VDD) and one connecting to VSS rail, and a series resistor connecting between input pad and the input buffer circuit. These two diodes protect the inner core circuit of CMOS transistor from ESD damage by discharging the excessive charge to either VSS or VDD, and the series resistor acts as current limiting resistor. There are many other protection schemes for VLSI integrated circuit against ESD such as design in gate-grounded p-channel MOSFET and n-channel MOSFET, thick oxide MOSFET, low voltage triggering silicon control rectifier etc. connecting at the input and output pads of the device.


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9.4.1.4 Electrical Rule Checking Electrical rule check ERC helps designer to consider all the minimum necessary implementations for an electrical free fault design. This tool verifies that the designer has used a sufficient number of well biases, design in appropriate ESD protection, used VDD and VSS at the right places etc.

The properties of the materials such as the resistivity of metal line, dielectric constant of the isolating material, and semiconductor material etc used in the fabrication of VLSI device would limit the performance of the device and decide the application of such design. Take for an example, aluminum metal line has inherent electro-migration problem that usually solved by adding 0.5-1.0 wt. per cent copper into aluminum. 9.4.2 Testing Concepts Testing is a process at the back-end after fabrication of integrated circuit wafer; the integrated circuit die has been assembled into packaged device. It is a process whereby the integrated circuit device is tested according to the intended application sector following specifications of the device. The intended application sector can be space/military, industrial, and commercial applications. Thus, the test strategy is to test the device and grade them into four categories that are space/military grade A, industrial grade B, commercial grade C, and failed/reject grade F. Other ways of naming of the grade can be different depending on organization.

After the integrated circuit has been fabricated, wafer probe test would screen the die (integrated circuit in chip form) into space/military grade, industrial grade, commercial grade, and of course the non-functional die. The screen test is like picking the best grade students to study to become doctor/engineer, the second best to be teacher/lawyer, and the third best to be technician. The flowchart of the screening test at probe is shown in Fig. 9.23. The test strategy is to test the die with the space/military grade first. If the die fails any of the tests, it is proceeded to test with the industrial test limits. If the die fails any of the industrial limit test, it is then tested with commercial grade test limits. If the die fails any of the commercial grade tests, it is then yielded as reject. The inking strategy to identify the die grade can be varied. Normally no ink on the surface of the die indicates the die is a space/military grade die. Green is used to identify the industrial grade die. Double inking – red and green, is used to identify the commercial grade die, and red ink is used to identify non-functional - failed to make any specification die. The inking strategy is


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necessary because the optical system of the die sorting process will pick the die according to the color and categorized them into space/military, industrial, and commercial grade. In the modern approach, inking can be ignored provided there is a grade mapping data of the wafer for each wafer that can be fed to computerized die sorter to pick the right grade die and place it accordingly to the designated tray.


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Figure 9.23: The flowchart of probe test and grading of die

In test operation, the process step after assembly, the test strategy follows the same grading systems as it has been described in die probe test. The military


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grade, industrial grade, and commercial grade device are sorted or binned (a term used by semiconductor manufacturer) separately by the sorter of an automatic test handler ATH. Sorted devices are then branded with the device part number and special digit to signify grading.

Commercial grade device is normally guaranteed to operate for temperature range between 00C to 700C. In order to reduce the cost of testing, commercial grade device is normally tested with ambient temperature only, which is taken as 250C. Since 00C and 750C temperature tests are not done. The test strategy is to test the device with guard banding for 00C and 750C characteristics. This shall mean that narrower test limits are used to test the device for ensuring the pass device at temperature 250C can pass sampling test at temperature 00C and 700C respectively. Commercial grade product is normally used in consumer product like computer, radio, washing machine etc. The average selling price (ASP) of the product is low and devices are not operated in harsh environment such as in the engine compartment of a car and in extreme temperature like a commercial plane. Therefore, one ambient test with proper guard banding for 00C and 750C tests is sufficient.

Industrial grade device is normally guaranteed to operate for temperature range between -400C to 850C. This grade of product is used in industrial application such as the control system of car fuel injector, components of instrument etc. Therefore, the test strategy is to test at least two temperatures i.e. ambient 250C tested with guard banding for 850C characteristics and -400C cold temperature. Depending on the criticality of the industrial operation, the product may have to be subjected to an accelerated burn-in to wipe out the infant mortality failure. The -400C temperature test is normally done in a cold temperature chamber of an automatic test handler (ATH) fitted with liquid nitrogen inlet.

Military/space grade device is normally guaranteed to operate for

temperature range between -550C to 1250C. This grade of device is normally used in space/military applications such as in the control system of weaponry system and computer of a commercial aircraft. The device normally has to undergo four tests i.e. one ambient before burn-in and three temperature tests after burn-in, which are ambient, 1250C, and -550C tests. The flowchart of the test sequence is shown in Fig. 9.24.


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Figure 9.24: A typical test flow of space/military grade VLSI device


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9.4.3 Automatic Test Equipment, Test Fixture, Test Program, and Automatic Test Handler

To test an integrated circuit die after fabrication before package at probe test and after package integrated circuit device requires automatic test equipment (ATE), a test fixture, a test program, and an automatic test handler ATH. 9.4.3.1 Automatic Test Equipment An ATE is used to apply a sequence of stimuli to die under probe DUP or device under test (DUT), monitor and/or record the results of response from the die or device, and make decision on pass/fail status within the test limits set according to specifications of the die/device. An ATE may have a single or dual test heads depending on the cost and purpose. A test head contains mainly the driver/receiver cards (pin cards), localized timing measurement units, power supply cards, current/voltage meter, control bits etc.

The ATE can be classified according to its intended purpose and product family to be tested. It can be a VLSI tester, an analogue tester, a mixed signal tester, a wireless/communication tester, microprocessor tester etc. Figure 9.25 shows a photograph of a VLSI Digital ATE that can be used to test VLSI microprocessor device.

Figure 9.25: A VLSI automatic test equipment showing test head and a mounted load board


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9.4.3.2 Test Fixture A test fixture is an interface board that contains interface circuitry connecting the assigned driver/receiver (I/O) cards, power supply cards, timing cards, control bits, and etc in the test head of ATE with the pin layout of chip/device under test. The test fixture may contain relays that can be controlled by control bits in test head of the ATE for switching-in different stimulant to the input/output pin or getting response from device, connecting external load to the die/device under test and etc.

A probe card is a test fixture. It is used to probe the integrated circuit die. A

mounted prober containing the probe pins arranged in bond pad layout pattern is used to make contact with the bond pads (bond pad is the input/output, clock input etc. that are to be connected via bond wire to the external world) of the die during probe test. The other end of the prober contains a bundle of wire connecting the prober and the probe card. The wafer is mounted on the x-y table that its x-y position is controlled by ATE. dc parameters of the die is normal probe tested but not ac test. The reason being that the probe pins normally have too high parasitic capacitance and contact resistance that can affect the reading of ac parameter.

A load board is a test fixture used for packaged device testing. For VLSI digital testing, a load board may contain simple configuration wiring between the input/output pins, clock pin, power supply pin etc. with the assigned pin card of ATE. For VLSI analogue device testing, a more complicated test fixture is required. This type of test fixture contains special test set-up circuitry according to device family. The bottom end of the load board contains contact pads when in use they are connected to the assigned pin cards etc of ATE via spring loaded pins or elastomeric contact. The top part contains a socket that can be mounted on the automatic test hander ATH for automatic feeding testing or temperature testing. A top view picture of a load board in Fig. 9.26 shows a socket to be mounted to automatic test handler.


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Figure 9.26: A top-view of a load board showing socket at the center to be mounted on the

ATH Automatic test equipment requires a test program. The program is normally written in a high level language for instance the IMAGE language used by Teradyne test system. The test program specifies a set of input test vector patterns and a set of output assertions. If an output does not match the asserted value at the corresponding time, the error logic of the ATE will report an error. Before the test vector patterns and assertions are applied, the test program has to set-up various attributes of an ATE as the following:

• Set the supply voltage according the specifications. • Assign mapping between stimulus file signal names and physical ATE

pin cards. i.e. configure the device pin layout and the assigned driver pins of TE.

• Set the pin cards on ATE to inputs or outputs for their respective VIL/VOH and VOL/VOH voltage levels.

• Set the clock frequency on ATE to be connected to device via load board to device under test (DUT).

• Set the input addressing mode, which can be both return to zero (RZ) and non return to zero (NRT) modes.

• Set input pattern and output assertions timing. and then on a device under test (DUT)


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• Apply supply voltages. • Apply digital stimulus, and record and compare responses. • Check responses against assertions • Report and log error. • Issue signal to automatic test handler to sort the device according to

grade. 9.4.3.3 Automatic Test Handler An IC automatic test handler ATH is responsible for feeding the device to test socket of a test fixture mounted to an ATE. Chutes or trays containing packaged device can be used to gravity-feed the device to the handler, which uses a variety of mechanical means to pick the device and place it in the test socket connected to load board. The ATE stimulus is then applied to the device and device is sorted (binned) depending on the grade that it has passed or reject if it fails functional test or device specifications. A photograph of a plastic leadless chip carrier PLCC automatic handler is shown in Fig. 9.27. The pilot light at the top left corner of the handler indicates the operating status of the handler. Green light means the handler is in operation. Yellow light indicates there is fault with the handler such as jamming. Red light indicates that handler is stop operation mode. This is necessary to attract attention of the maintenance crew when assistant is needed.

Figure 9.27: The picture shows a PLCC automatic test handler


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Exercises 9.1. Why is it necessary to measure the physical parameter of a fabricated

integrated circuit? 9.2. Calculate the current transfer distance (li) if the contact resistivity is

2.0x10-7Ωcm2 and the resistivity of silicon is 100Ω/ . 9.3. If the physical contact area of the n+ diffusion region is 1.0µm x 0.5µm,

using the result of question 2, calculate the contact resistance. 9.4. Using a cross-bridge Kelvin structure with a 1.0µm x 1.0µm contact, the

current is found to be 10.0µA through the contact and the voltage difference across the contact is 320µV, find the contact resistivity of this contact.

9.5. State the reason necessary to have coefficient of thermal expansion

matching materials for package and silicon die. 9.6. Why aluminum wire bonding is preferred than gold wire bonding? 9.7. If the Au-Al bond diffusion thickness is increased by 1.0µm during 1500C

time-temperature storage operation, calculate the period of time. You may use D0 = 2.2x10-4m2/s, Q= 134kJ/mol and R= 8.31J/mol-K to help you in the calculation.

9.8. For VLSI device plastic molding, state the reason why multi-pot molding

is necessary. 9.9. State the reasons why the leads of the package are normally shorted

together in a assembly operation. 9.10. Calculate the number of gates that can be included on a logic-array chip

which is to be assembled in 120 I/O package assuming that k = 4.5 and β = 0.5.

9.11. An integrated circuit has 800 gates, its nominal propagation delay for a

transistor is 5.0x10-15s, its junction to ambient maximum temperature difference is 550C, and junction to ambient thermal resistance is 1000C/W. Calculate the activation energy of each gate of this circuit.


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9.12. State the reason why it is necessary to have heat sink for conducting away extra heat from the package of integrated circuit?

9.13. State three problems that can be used to minimize design constraints due

to latch-up problem. 9.14. As a design engineer you know that there is an npn parasitic bipolar

junction transistor in the n-channel MOSFET strcuture. Name the method used to in-active this parasitic transistor.

9.15. State one method to minimize the occurrence of latch-up problem. 9.16. What is the purpose of test load board? 9.17. What is the purpose of burn-in test?

Answers of Exercises 9.1. It is necessary because the manufacturer would like to integrated circuit is

fabricated in accordance to the specifications.

9.2. The current transfer length (li) is equal to S

Ci σ

ρ=l =100

10x0.2 7−

= 0.447µm.

9.3. The area of current flow is 0.447µmx0.5µm = 2.235x10-9cm2. Given that

the contact resistivity ρC = 2.0x10-7Ωcm2, the contact resistance RC is 2.0x10-7Ωcm2/2.235x10-9cm2 = 89.48Ω.

9.4. The current across the contact is 320µV/10.0µA = 32Ω. The contact

resistivity ρC is 32x1.0x10-8cm2 = 32Ωcm2. 9.5. It is necessary because many assembly processes are high temperature

processes such as die attach, molding etc. In order to reduce the thermal stress on the die that may result in die crack etc., it is necessary to find a packaging material that has coefficient of thermal expansion (CTE) matches with CTE of silicon die.

9.6. The bond pad is made of aluminum. Gold will diffuse into aluminum to

form Au-Al inter-metallic compound. With temperature and time, it will eventually form Au-Al4 that will weaken the bond strength. Aluminum


- 41 -

diffuses well with aluminum bond pad so there is no issue of bond strength as long as the wire bonding process is controlled within specifications.

9.7. First of all is to calculate the diffusion constant using equation

( )RT/QexpDD 0 −= . Thus the diffusion constant is D = 2.2x10-4exp[-134x103/(8.31x423)] = 2.2x10-4x2.781x10-17 = 6.1195x10-21m2/s. The period time can then be calculated using equation t = X2/D = 1.0x10-12/6.1195x10-21 = 1.634x108s = 5.85 years.

9.8. The die size of VLSI integrated circuit is normally large and the length of

wire is long and the number of wire can be a few hundreds. In order to reduce wire sweeping problem, incomplete mold due early cross linked of the mold resin, and the flow duration of molten in the cavity, it is necessary to use multi-pot molding system to mold VLSI device.

9.9. The leads of the package are normally shorted because it helps in two

aspects namely preventing the bent lead problem during the process and to provide equal-potential for protection the die from the damage of electrostatic charge.

9.10. The number of gates can be calculated using Rent’s rule, which is P =

kGβ. Thus, 120 = 0.45(G)0.5. Therefore, the number of gate G is approximately equal to 711.

9.11. The activation energy can be calculated using Nagata equation E

T

t

N

p

G

θ∆≤ .

Thus, E100

55

10x0.5

80015

≤− . Therefore the activation energy of the gate is ≤

3.43x10-18J. 9.12. This is necessary because it needs to keep the constant temperature

difference between junction of the integrated circuit and ambient temperature to void junction failure and at the same time to reduce thermal resistance between junction and ambient for allowing higher power dissipation of the integrated circuit.

9.13. The latch-up problems can be minimized by designing-in the p-MOS and

n-MOS transistors using twin well concepts and using refilled deep trench isolation to separate the wells. At the application, ensure the gate input


- 42 -

voltage is not at anytime more than VDD voltage. This can be achieved by capacitor filtering and control the ground harmonic signal.

9.14. The parasitic npn transistor can be in-active by bias the p-substrate or p-

well with VSS voltage. The purpose is to bias the emitter-to-base junction of this transistor in reverse bias mode.

9.15. A method used to minimize latch-up to design in a refilled either with

polysilicon or silicon dioxide deep trench isolation to isolate the wells of p-MOSFET and n-MOSFET.

9.16. A test load board contains interface circuit that configures the pin cards of

the test head to pin layout of the device under test DUT. 9.17. Burn-in is an accelerated stress test that used to wipe out infant mortality

in speedy manner.

Bibliography 1. S.M. Sze, “VLSI Technology”, McGraw Hill, 2002. 2. Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic “Digital

Integrated Circuit – A Design Perspective”, 2nd edition, Prentice Hall. 2003.

3. C.Y. Chang and S.M. Sze, “ULSI Technology”, McGraw Hill, 1996. 4. N. H. Weste and D. Harris, “CMOS VLSI Design: A Circuits and Systems

Perspective”, third edition, Pearson Addison Wesley, 2005. 5. M. Machael Vai, “VLSI Design”, CRC Press LLC, 2001.

- 43 -

A

Alumina...................................................18 Atomic force microscopy..........................2 Auger electron Spectroscopy ....................5 Average selling price ..............................35

B

Ball grid array .........................................23 BGA ............................. See Ball-grid array Bond pad .................................................38

C

Ceramic ...................................................18 Coefficient of thermal expansion..............6 Contact resistivity .....................................2 Cross-bridge Kelvin structure ...................3

D

Design rule check....................................29 Device under test.....................................37 DIP ....................................See Dual-in line Dual-in-line .............................................22

E

E. Rent.....................................................17 Electrical rule check................................32 Electron Back-Scattering Diffraction .......5

F

Flip-chip mounting..................................21 Fourier Transform Infrared Spectroscop ..5

H

Hydrofluoric acid ......................................5

L

Layout versus schematic check...............29 LCC.....................See Leadless chip carrier Leadless chip carrier ...............................23 Load board ..............................................38

M

MCM.......See Multichip module technique

Multichip module technique...................24

N

Nagata .....................................................26

P

PGA .............................. See Pin-grid-array Phosphosilicate glass ................................5 Pin-grid-array..........................................22 Plastic leaded package ............................23 PLCC ...............See Plastic leaded package Poisson ratio .............................................6 Polyimide................................................18 Polymer...................................................18 Probe test ................................................32

Q

QFP...............................See Quad flat pack Quad flat pack.........................................23

R

Rent’s rule...............................................17 Rockwell International............................25

S

Silicon control rectifier ...........................30 Small-outline package ............................23 SOIC .................See Small outline package Surface-mount.........................................22

T

TAB ............. See Tape automated bonding Tape automated bonding...................20, 24 Test fixture..............................................38 Test program...........................................37 Titanium silicide .......................................2

W

Wire bonding ..........................................19

X

X-ray Diffraction ......................................5

Documents

09 Manufacturing Process - Universiti Tunku Abdul Rahmanstaff.utar.edu.my/limsk/semiconductor technologies... · 9 Manufacturing Process - 2 - d s x ρ ρ= (9.1) Using a four-point