08-SingleCycleProcessorDesign

8/10/2019 08-SingleCycleProcessorDesign

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Single Cycle Processor Design


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Outline

Designing a Processor: Step-by-Step

Datapath Components and Clocking

Assembling an Adequate Datapath

Controlling the Execution of nstructions

!he "ain Controller and A#$ Controller

Dra%back of the single-cycle processor design


3/51

&ecall' performance is determined by:

nstruction count

Clock cycles per instruction (CP)

Clock cycle time

Processor design %ill affect

Clock cycles per instruction

Clock cycle time

Single cycle datapath and control design:

Ad*antage: +ne clock cycle per instruction

Disad*antage: long cycle time

The Performance Perspective

I-Count

CPI Cycle


4/51


Analy,e instruction set . datapath requirements

!he meaning of each instruction is gi*en by the register transfers

Datapath must include storage elements for SA registers

Datapath must support each register transfer

Select datapath componentsand clocking methodology

Assemble datapathmeeting the requirements

Analy,e implementation of each instruction

Determine the setting of control signalsfor register transfer

Assemble the control logic


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Review of MPS nstruction !ormatsAll instructions are /0-bit %ide

!hree instruction formats: &-type' -type' and 1-type

+p2: 2-bit opcode of the instruction

&s3' &t3' &d3: 3-bit source and destination register numbers

sa3: 3-bit shift amount used by shift instructions

funct2: 2-bit function field for &-type instructions

immediate42: 42-bit immediate *alue or address offset

immediate02: 02-bit target address of the 5ump instruction

+p2 &s3 &t3 &d3 funct2sa3

+p2 &s3 &t3 immediate42

+p2 immediate02


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MPS Subset of nstructions

+nly a subset of the "PS instructions are considered

A#$ instructions (&-type): add, sub, and, or, xor, slt

mmediate instructions (-type): addi, slti, andi, ori, xori

#oad and Store (-type): lw, sw

6ranch (-type): beq, bne

1ump (1-type):j

!his subset does not include all the integer instructions

6ut sufficient to illustrate design of datapath and control

Concepts used to implement the "PS subset are used

to construct a broad spectrum of computers


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Details of the MPS Subsetnstruction "eaning 7ormat

add rd' rs' rt addition op2 8 rs3 rt3 rd3 8 8x08sub rd' rs' rt subtraction op2 8 rs3 rt3 rd3 8 8x00

and rd' rs' rt bit%ise and op2 8 rs3 rt3 rd3 8 8x09

or rd' rs' rt bit%ise or op2 8 rs3 rt3 rd3 8 8x03

xor rd' rs' rt exclusi*e or op2 8 rs3 rt3 rd3 8 8x02

slt rd' rs' rt set on less than op2 8 rs3 rt3 rd3 8 8x0a

addi rt' rs' im42 add immediate 8x8 rs3 rt3 im42

slti rt' rs' im42 slt immediate 8x8a rs3 rt3 im42

andi rt' rs' im42 and immediate 8x8c rs3 rt3 im42

ori rt' rs' im42 or immediate 8x8d rs3 rt3 im42

xori rt' im42 xor immediate 8x8e rs3 rt3 im42

l% rt' im42(rs) load %ord 8x0/ rs3 rt3 im42

s% rt' im42(rs) store %ord 8x0b rs3 rt3 im42

beq rs' rt' im42 branch if equal 8x89 rs3 rt3 im42

bne rs' rt' im42 branch not equal 8x83 rs3 rt3 im42

5 im02 5ump 8x80 im02


8/51

Register Transfer "evel #RT"$ &!# is a description of data flo% bet%een registers

&!# gi*es a meaningto the instructions

All instructions are fetched from memory at address PC

nstruction &!# DescriptionADD &eg(&d) ; &eg(&s) < &eg(&t)=

PC ; PC < 9

S$6 &eg(&d) ; &eg(&s) > &eg(&t)=

PC ; PC < 9

+& &eg(&t) ; &eg(&s) ? ,ero@ext(m42)=PC ; PC < 9

# &eg(&t) ; "E"B&eg(&s) < sign@ext(m42)=

PC ; PC < 9

S "E"B&eg(&s) < sign@ext(m42) ; &eg(&t)=

PC ; PC < 9


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nstructions are %&ecute' in Steps &-type 7etch instruction: nstruction ; "E"BPC

7etch operands: data4 ; &eg(&s)' data0 ; &eg(&t)

Execute operation: A#$@result ; func(data4' data0)

rite A#$ result: &eg(&d) ; A#$@result

Fext PC address: PC ; PC < 9

-type 7etch instruction: nstruction ; "E"BPC

7etch operands: data4 ; &eg(&s)' data0 ; Extend(imm42)

Execute operation: A#$@result ; op(data4' data0)

rite A#$ result: &eg(&t) ; A#$@result


6E 7etch instruction: nstruction ; "E"BPC7etch operands: data4 ; &eg(&s)' data0 ; &eg(&t)

Equality: ,ero ; subtract(data4' data0)

6ranch: if (,ero) PC ; PC < 9 < 9sign@ext(imm42)

else PC ; PC < 9


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nstruction %&ecution ( cont)' # 7etch instruction: nstruction ; "E"BPC

7etch base register: base ; &eg(&s)

Calculate address: address ; base < sign@extend(imm42)

&ead memory: data ; "E"Baddress

rite register &t: &eg(&t) ; data


S 7etch instruction: nstruction ; "E"BPC

7etch registers: base ; &eg(&s)' data ; &eg(&t)

Calculate address: address ; base < sign@extend(imm42)

rite memory: "E"Baddress ; data


1ump 7etch instruction: nstruction ; "E"BPC

!arget PC address: target ; PCB/4:0 ' mm02 ' G88H

1ump: PC ; target

concatenation


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Re*uirements of the nstruction Set"emory

nstruction memory%here instructions are stored

Data memory%here data is stored

&egisters

/0 /0-bit general purpose registers' &8 is al%ays ,ero

&ead source register &s

&ead source register &t

rite destination register &t or &d

Program counter PC registerandAdderto increment PC

Sign and Iero extenderfor immediate constant

A#$for executing instructions


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+e&t , , ,








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Combinational Elements

A#$' Adder

mmediate extender

"ultiplexers

Storage Elements nstruction memory

Data memory

PC register

&egister file

Clocking methodology

!iming of reads and %rites

Components of the Datapath

DataMemory

Address

Data@in

Data@out

"em&ead"emrit

e

/0

/0

/0

/0

Address

nstruction

Instruction

Memory

/0

m

u

x

8

4

select

Extend/042

Ext+p

Registers

&A

&6

6usA

&egrite

6us6

&

3

3

3

/0

/0

/0

6us

PC

/0 /0

A#$

A#$ control

A#$ result

,ero

/0

/0

/0

o*erflo%

Clock


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&egister

Similar to the D-type 7lip-7lop

n-bit input and output

rite Enable: Enable J disable %riting of register

Fegated (8): Data@+ut %ill not change

Asserted (4): Data@+ut %ill become Data@n after clock edge

Edge triggered Clocking

&egister output is modified at clock edge

Register %lement

&egister

Data@n

Clockrite

Enable

n bits

Data@+ut n bits


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&egister 7ile consists of /0 /0-bit registers

6usAand 6us6: /0-bit output busses for reading 0 registers

6us: /0-bit input bus for %riting a register %hen &egriteis 4

!%o registers read and one %ritten in a cycle

&egisters are selected by: &Aselects register to be readon 6usA

&6selects register to be readon 6us6

&selects the register to be %ritten

Clock input !he clock input is used+F#K during %riteoperation

During read' register file beha*es as a combinational logicblock

&A or &6 *alid . 6usA or 6us6 *alid after access time

RW RA RBMPS Register !ile

&egister

7ile&A&6

6usA

&egrite

6us6&

3

3

3

/0

/0

/0

6us

Clock


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Allo% multiple sources to dri*e a single bus

!%o nputs:

Data signal (data@in)

+utput enable

+ne +utput (data@out): f (Enable) Data@out Data@in

else Data@out Ligh mpedance state (output is

disconnected)

!ri-state buffers can be

used to build multiplexors

Tri-State uffers

Data@in Data@out

Enable

Data@8

Data@4

+utput

Select


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Details of the Register !ile

6usA

&4

&0

&/4

.

.

.

6us

Decoder&

3

Clock &egrite

MMM

&8 is

not

used

6us6

N8N N8N

&A

Decoder

3 &6

Decoder

3

/0

/0

/0

/0

/0

/0

/0

/0

/0

!ri-state

buffer


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uil'ing a Multifunction ."/

0

!

"

0

!

"

#ogic $nit

!

AFD 88

+& 84

F+& 48

O+& 44#ogical

+peration

Shifter

!Fone 88

S## 84S 48

S&A 44

Sh

ift

+peration

A "!

"!6

#dder

c8

"!

"!

ADD 8

S$6 4

Arithmetic

+peration

Shift 88

S#! 84

Arith 48

#ogic 44

A#$

Selection

"!

!

$%i&t #mount

A#$ &esult

lsb '

sign

,eroo*erflo%

S#!: A#$ does a

S$6 and check thesign and o*erflo%


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nstruction an' Data Memories nstruction memory needs only pro*ide read access

6ecause datapath does not %rite instructions

6eha*es as combinational logic for read

Addressselects nstructionafter access time

Data "emory is used for load and store "em&ead:enables output on Data@out

Addressselects the %ord to put on Data@out

"emrite:enables %riting of Data@in

Addressselects the memory %ord to be %ritten !he Clocksynchroni,es the %rite operation

Separate instruction and data memories

#ater' %e %ill replace them %ith caches

"emrit

e"em&ead

Data

"emory

Address

Data@in

Data@out/0

/0

/0

Clock

/0Address nstruction

nstruction

"emory

/0


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Cloc0ing Metho'ology Clocks are needed in a sequential

logic to decide %hen a state element

(register) should be updated

!o ensure correctness' a clocking

methodologydefines %hen data can

be %ritten and read

Combinational logic

&egister4

&egister0

clock

rising edge falling edge

e assume edge-

triggered clocking

All state changes

occur on the same

clock edge

Data must be*alidand stable

before arri*al of

clock edge

Edge-triggered

clocking allo%s a

register to be read

and %ritten during

same clock cycle


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Determining the Cloc0 Cycleith edge-triggered clocking' the clock cycle must be

long enough to accommodate the path from one registerthrough the combinational logic to another register

!cycle !clk-q< !max@comb< !s

Combinational logic&egister4

&egister0

clock

%riting edge

!clk-q !max@comb !s !h

!clk-q : clock to output delay

through register

!max@comb : longest delay

through combinational logic

!s: setup time that input to a

register must be stable

before arri*al of clock edge

!h: hold time that input to a

register must hold after

arri*al of clock edge

Lold time (!h) is normally

satisfied since !clk-q. !h


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Cloc0 S0ew

Clock ske%arises because the clock signal uses different

paths%ith slightly different delaysto reach state elements

Clock ske% is the difference in absolute timebet%een

%hen t%o storage elements see a clock edge

ith a clock ske%' the clock cycle time is increased

Clock ske% is reduced by balancing the clock delays

!cycle !clk-q< !max@combinational< !setup< !ske%


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+e&t , , ,








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e can no% assemble the datapath from its components

7or instruction fetching' %e need Q

Program Counter (PC) register

nstruction "emory

Adder for incrementing PC

nstruction !etching Datapath

!he least significant 0 bits

of the PC are G88Hsince

PC is a multiple of 9

Datapath does not

handle branch or

5ump instructions

mpro*ed datapath

increments upper

/8 bitsof PC by 4

PC

/0

Address

nstruction

Instruction

Memory

/0

/0/0

(Add

next PC

/0

Address

nstruction

Instruction

Memory

/0

/8

PC

88


25/51

Datapath for R-type nstructions

Control signals

A#$Ctrl is deri*ed from the functfield because +p 8 for &-type

&egriteis used to enable the %riting of the A#$ result

+p2 &s3 &t3 &d3 funct2sa3

A#$

/0

/0

A#$Ctrl

&egrite

Registers

&A

&6

6usA

6us6

&6us

/0

Address

nstruction

Instruction

Memory

/0

/8

PC

88


26/51

Datapath for -type ."/ nstructions

Control signals

A#$Ctrl is deri*ed from the +pfield

&egriteis used to enable the %riting of theA#$ result

Ext+p is used to control the extension of the 42-bit immediate

+p2 &s3 &t3 immediate42

A#$Ctrl

&egrite

/0

Address

nstruction

Instruction

Memory

/0

/8

PC

88


27/51

Combining R-type 1 -type Datapaths

Control signals

A#$Ctrl is deri*ed from either the +por the functfield

&egriteenables the %riting of theA#$ result

Ext+p controls the extension of the 42-bit immediate

&egDstselects the register destination as either &tor &d

A#$Src selects the 0ndA#$ source as 6us6or extended immediate

A mux selects &

as either &t or &d

Another mux

selects 0ndA#$

input as either

source register

&t data on 6us6

or the extended

immediate

A#$Ctrl

&egrite

Ext+p

A#$

A#$ result

/0

/0

Registers

&A

&6

6usA

6us6

&

3

/0

6us

/0

Address

nstruction

Instruction

Memory

/0

/8

PC

88


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A#$

A#$Ctrl

A#$ result

/0

/0

Registers

&A

&6

6usA

&egrite 4

6us6

&

3

/0

6us

/0

Address

nstruction

Instruction

Memory

/0

/8

PC

88


29/51

Details of the %&ten'er !%o types of extensions

Iero-extension for unsigned constants

Sign-extension for signed constants

Control signal Ext+pindicates type of extension

Extender mplementation: %iring and one AFD gate

Ext+p 8 $pper42 8

Ext+p 4

$pper42 sign bit

.

.

.

Ext+p

$pper

42 bits

#o%er

42 bits.

.

.

mm42


30/51

Additional Control signals

"em&eadfor load instructions

"emritefor store instructions

"emto&eg selects data on 6us asA#$ resultor "emory Data@out

6us6 is connected to Data@in of Data

"emory for store instructions

.''ing Data Memory to DatapathA data memoryis added for loadand storeinstructions

A /rdmux selects data on 6us as

either A#$ result or memory data@out

Data

Memory

Address

Data@inData@out

/0

/0A#

$

A#$Ctrl

/0

Registers

&A

&6

6usA

&egrite

6us6

&

3

6us

/0

Address

nstruction

Instruction

Memory

/0

/8

PC

88


31/51

A#$Ctrl GADDH to calculate data memory

address as &eg(&s) < sign-extend(mm42)

A#$Src G4H selects extended immediate as

second A#$ input

Controlling the %&ecution of "oa'

"em&ead G4H to read data memory

&egDst G8H selects &t

as destination register

Ext+p GsignH to sign-extend

mmmediate42 to /0 bits

&egrite G4H to %rite the memory

data on 6us to register &t

"emto&eg G4H places the data read

from memory on 6us

Data

Memory

Address

Data@in

Data@out

/0

/0

A#

$

A#$Ctrl ADD

A#$ result

/0

/0Registers

&A

&6

6usA

&egrite

4

6us6

&

3

6us

/0

Address

nstruction

Instruction

Memory

/0

/8

PC

88


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A#$Ctrl GADDH to calculate data memory

address as &eg(&s) < sign-extend(mm42)

A#$Src G4H to select the extended

immediate as second A#$ input

Controlling the %&ecution of Store

"emrite G4H to %rite data memory

&egDst GxH because

no destination register

Ext+p GsignH to sign-extend

mmmediate42 to /0 bits

&egrite G8H because no register is

%ritten by the store instruction

"emto&eg GxH because %e donHt

care %hat data is placed on 6us

Data

Memory

Address

Data@in

Data@out

/0

/0

/0

A#

$

A#$Ctrl ADD

A#$ result

/0

/0Registers

&A

&6

6usA

&egrite

8

6us6

&

3

6us

/0

Address

nstruction

Instruction

Memory

/0

/8

PC

88


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.''ing 2ump an' ranch to Datapath

Additional Control Signals

1' 6eq' 6nefor 5ump and branch instructions

Ierocondition of the A#$ is examined

PCSrc 4 for 1ump R taken 6ranch

Ext

Data

Memory

Address

Data@inData@out

"em&ead

"emrite

/0

A#

$

A#$Ctrl

A#$ result

/0Registers

&A

&6

6usA

&egrite

6us6

&

3

6us

/0

Address

nstruction

Instruction

Memory

PC

88


34/51

Details of +e&t PC

#

D

D

/8

/8

0

mux

1

nc PC

/8

mm42

mm02

/8SE

9msb

02

6eq

6ne

1

Iero

PCSrc6ranch or 1ump !arget Address

mm42 is sign-extended to /8 bits

1ump target address: upper 9 bits of PC are concatenated %ith mm02

PCSrc 1 < (6eq .Iero) < (6ne .Iero)

Sign-Extension:

"ost-significantbit is replicated


35/51

Controlling the %&ecution of 2ump

Ext

Data

Memory

Address

Data@inData@out

/0

A#$ result

/0

3

Registers

&A

&6

6usA

6us6

&6us

/0

Address

nstruction

Instruction

Memory

PC

88 /8

&s

3

&d

mm02

&t

m

ux

8

43

mux

8

4

m

ux

8

4

m

ux

8

4

/8

/8 1ump !arget Address

/8

mm42

Fext

PC

&egrite

8

"em&ea

d 8

"emrit

e 8

1 4

&egDst

x A#$Ctrl

x

A#$Src

x

"emto&eg

x

Ext+p

x

PCSrc

4


36/51

Controlling the %&ecution of ranch

Ext

Data

Memory

Address

Data@inData@out

/0

A#$ result

/0

3

Registers

&A

&6

6usA

6us6

&6us

/0

Address

nstruction

Instruction

Memory

PC

88 /8

&s

3

&d

mm02

&t

m

ux

8

43

mux

8

4

m

ux

8

4

m

ux

8

4

/8

/8 6ranch !arget Address

/8

mm42

Fext

PC

&egrite

8

"em&ea

d 8

"emrit

e 8

6eq 4

6ne 4

A#$Ctrl

S$6

A#$Src

8

&egDst

x

"emto&eg

x

Ext+p

x

PCSrc

4


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+e&t , , ,








38/51

Main Control an' ."/ Control

nput:

2-bit opcodefield from instruction

+utput:

48 control signalsfor datapath

A#$+pfor A#$ Control

nput:

2-bit functionfield from instructionA#$+pfrom main control

+utput:

A#$Ctrlsignal for A#$

A#$

Control

"ain

Control

Datapath/0Address

nstruction

Instruction

MemoryA#$

+p2

&egDst

&egrite

Ext+p

A#$Src

"em&ead

"emrite

"emto&eg

6eq

6ne

A#$+p

A#$Ctrl

funct2

1


39/51

Single-Cycle Datapath 3 Control

PCSrc

Ext

Data

Memory

Address

Data@inData@out

/0

A#$

A#$ result

/0

3

Registers

&A

&6

6usA

6us6

&6us

/0

Address

nstruction

Instruction

Memory

PC

88


40/51

Signal Effect %hen G8H Effect %hen G4H

&egDst Destination register &t Destination register &d

&egrite Fone Destination register is %ritten %ith thedata *alue on 6us

Ext+p 42-bit immediate is ,ero-extended 42-bit immediate is sign-extended

A#$Src Second A#$ operand comes from the

second register file output (6us6)

Second A#$ operand comes from the

extended 42-bit immediate"em&ead Fone Data memory is read

Data@out ; "emoryBaddress

"emrite Fone Data memory is %ritten"emoryBaddress ; Data@in

"emto&eg 6us A#$ result 6us Data@out from "emory

6eq' 6ne PC ; PC < 9 PC ; 6ranch target addressf branch is taken

1 PC ; PC < 9 PC ; 1ump target address

A#$+p !his multi-bit signal specifies the A#$ operation as a function of the opcode

Main Control Signals


41/51

+p &egDst

&egrite

Ext+p

A#$Src

A#$+p

6eq 6ne 1 "em&ead

"emrite

"emto&eg

&-type 4 &d 4 x 86us6 &-type 8 8 8 8 8 8

addi 8 &t 4 4sign 4mm ADD 8 8 8 8 8 8

slti 8 &t 4 4sign 4mm S#! 8 8 8 8 8 8

andi 8 &t 4 8,ero 4mm AFD 8 8 8 8 8 8

ori 8 &t 4 8,ero 4mm +& 8 8 8 8 8 8

xori 8 &t 4 8,ero 4mm O+& 8 8 8 8 8 8

l% 8 &t 4 4sign 4mm ADD 8 8 8 4 8 4

s% x 8 4sign 4mm ADD 8 8 8 8 4 x

beq x 8 x 86us6 S$6 4 8 8 8 8 x

bne x 8 x 86us6 S$6 8 4 8 8 8 x

5 x 8 x x x 8 8 4 8 8 x

Main Control Signal 4alues

O is a donHt care (can be 8 or 4)' used to minimi,e logic


42/51

&egDst &-type

&egrite (s% < beq < bne < 5)

Ext+p (andi < ori < xori)

A#$Src (&-type < beq < bne)

"em&ead l%

"emrite s%

"emto&eg l%

"ogic %*uations for Control Signals

+p2

&-type

addi

slti

andi

orixoril% s

%

6eq6ne

&egDst

&egrite

Ext+p

A#$Src

"em&e

ad

"emrite

"emto&

eg

#ogic

Equations

#+,o

)

1

Decoder


43/51

+p2 A#$ Control 9-bitEncodingA#$+p funct2 A#$Ctrl

&-type &-type add ADD 8888

&-type &-type sub S$6 8848

&-type &-type and AFD 8488

&-type &-type or +& 8484

&-type &-type xor O+& 8448

&-type &-type slt S#! 4848

addi ADD x ADD 8888

slti S#! x S#! 4848

andi AFD x AFD 8488

ori +& x +& 8484

xori O+& x O+& 8448l% ADD x ADD 8888

s% ADD x ADD 8888

beq S$6 x S$6 8848

bne S$6 x S$6 8848

5 x x x x

."/ Control Truth Table

+ther binary

encodings are also

possibleM !he idea is

to choose a binary

encoding that %illminimi,e the logic for

A#$ Control

!he 9-bit encoding

for A#$ctrl is chosen

here to be equal to

the last 9 bits of the

function field


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+e&t , , ,








45/51

Drawbac0s of Single Cycle Processor #ong cycle time

All instructions take as much time as the slo%est

Alternati*e Solution: "ulticycleimplementation

6reak do%n instruction execution into multiple cycles

nstruction 7etchStore A#$ "emory rite

nstruction 7etchA#$ &eg &ead A#$

nstruction 7etch6ranch

#oad "emory &eadnstruction 7etch

longest delay

A#$&eg &ead

&eg &ead

&eg &ead A#$

nstruction 7etch1ump Decode

&eg rite

&eg rite


46/51

Multicycle mplementation 6reak instruction execution into fi*e steps

nstruction fetch

nstruction decode and register read

Execution' memory address calculation' or branch completion

"emory access or A#$ instruction completion

#oad instruction completion

+ne step +ne clock cycle(clock cycle is reduced)

7irst 0 steps are the same for all instructions

nstruction T cycles nstruction T cycles

A#$ R Store 9 6ranch /

#oad 3 1ump 0


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Performance %&ampleAssume the follo%ing operation times for components:

nstruction and data memories: 088 ps

A#$ and adders: 48 ps

Decode and &egister file access (read or %rite): 438 ps

gnore the delays in PC' mux' extender' and %ires

hich of the follo%ing %ould be faster and by ho% muchU

Single-cycle implementation for all instructions

"ulticycle implementation optimi,ed for e*ery class of instructions

Assume the follo%ing instruction mix:

98V A#$' 08V #oads' 48V stores' 08V branches' R 48V 5umps


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Solutionnstruction

Classnstruction"emory

&egister&ead

A#$+peration

Data"emory

&egisterrite

!otal

A#$ 088 438 48 438 28 ps

#oad 088 438 48 088 438 8 ps

Store 088 438 48 088 W/8 ps

6ranch 088 438 48 3/8 ps

1ump 088 438 /38 ps 7or fixed single-cycle implementation:

Clock cycle

7or multi-cycle implementation:

Clock cycle

A*erage CP

Speedup

decode and update PC

8M99 < 8M03 < 8M49< 8M0/ < 8M40 /M

max (088' 438' 48) 088 ps (maximum delay at any step)

8 ps determined by longest delay (load instruction)

8 ps J (/M 088 ps) 8 J W28 4M42


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5orst Case Timing #"oa' nstruction$

ew PCld PC

Cl/-to-q

Instruction Memory #ccess ime

ld Instruction ew Instruction 1 2), Rs, Rt, Rd, 3unct, Imm4, Imm!45

Delay %roug% Control +ogic

ld Control $ignal 6alues ew Control $ignal 6alues 27xt), #+$rc, #+), 85

Register 3ile #ccess ime

ld 9us# 6alue ew 9us# 6alue 1 Register2Rs5

Delay %roug% 7xtender and #+ Mux

ld $econd #+ In)ut ew $econd #+ In)ut 1 sign-extend2Imm45

#+ Delay

ld #+ Result ew #+ Result 1 #ddress

Data Memory #ccess ime

ld Data Memory ut)ut 6alue ew 6alue

Mux delay : $etu) time : Cloc/

s/ew

;rite

ccurs

Cloc/ Cycle

Cl/


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5orst Case Timing ( Cont6' #ong cycle time: must be long enough for #oad operation

PCHs Clk-to-

< nstruction "emoryHs Access !ime

< "aximum of (

&egister 7ileHs Access !ime'

Delay through control logic < extender < A#$ mux)

< A#$ to Perform a /0-bit Add

< Data "emory Access !ime

< Delay through "emto&eg "ux

< Setup !ime for &egister 7ile rite < Clock Ske%

Cycle time is longer than neededfor other instructions

!herefore' single cycle processor design is not used in practice


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Summary 3 steps to design a processor

Analy,e instruction set . datapath requirements

Select datapath componentsR establish clocking methodology

Assemble datapathmeeting the requirements

Analy,e implementation of each instructionto determine control signals

Assemble the control logic

"PS makes Control easier

nstructions are of same si,e

Source registers al%ays in same place

mmediates are of same si,e and same location

+perations are al%ays on registersJimmediates

Single cycle datapath . CP4' but #ong Clock Cycle

Documents

08-SingleCycleProcessorDesign