04 Biasing Circuits of the BJTmsn/213332han04.pdf · Get device characteristics from the specification sheet of the BJT 2. Superimposed the line (straight line in case of fixed biased

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13/7/2004 Asst.Prof.Dr. MONTREE SIRIPRUCHYANUN 1

213332 Electronic Circuit and Devices I

AsstAsst.. Prof Prof. Dr.. Dr. Montree Montree SIRIPRUCHYANUN SIRIPRUCHYANUNDept. of Teacher Training in Electrical Engineering,King Mongkut’s Institute of Technology North Bangkok

Biasing Circuits of theBiasing Circuits of theBJTBJT


Biasing Circuits of the BJT:Normally, four types of circuits are used toestablish dc biasing in a BJT, these are;

(a) Fixed bias circuit(b) Emitter-Stabilized Bias Circuit(c) Voltage-Divider Bias Circuit(d) Voltage Feedback Bias Circuit

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Biasing Circuits of the BJT:Since the common emitter configuration ismost widely used therefore, all four biasingcircuits will be discussed for a commonemitter BJT.

(a) Fixed bias circuit(b) Emitter-Stabilized Bias Circuit(c) Voltage-Divider Bias Circuit(d) Voltage Feedback Bias Circuit

While designing the all four types of biasing circuits of BJT itis aimed to obtain Q-point parameters (IBQ, ICQ, VCEQ)


IC (mA)

VCEmaxVCECutoff

region

Saturationregion

VCEsat

Outputcharacteristics of

a commonemitter BJT

1

2

Desired point ofoperation maybe some wherein unshaded area

3

PCmax=300mW

ICmax

ICEO

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Biasing Circuits of the BJT (Continued)

(a) Fixed bias circuitThis circuit provides a relatively simple and straightforwardintroduction to BJT’s DC bias analysis.

• For the dc analysis theBJT network can be isolatedfrom the ac levels by replacingcoupling capacitors with anopen circuit equivalent.

• The dc supply VCCcan be separated into parts foranalysis purpose only.

The resulting network isshown in next slide.

Input

Output

Fig. Fixed biascircuit


(a) Fixed bias circuit (continued)

Fig. DC equivalentof Fixed biasingnetwork shown inprevious slide

Collector-EmitterLoop (Output Loop)

Base-EmitterLoop (InputLoop)

To get the Q-point parameters, theDC analysis is divided into parts(a) Base-Emitter Loop(b) Collector-Emitter Loop

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(a) Fixed bias circuit (continued)Base-Emitter Loop Analysis

Applying KVL in clockwisedirection

+ VCC - IBRB-VBE = 0 (1)On solving the eq(1) for IB onegets;

IB = (VCC - VBE)/RB (2)

Since VCC and VBE areconstant and hence selectionof RB sets the value of IB.

Hence from eq(2) IBQ = IBBase-Emitter Loop

KVLDirection


(a) Fixed bias circuit (continued)Collector-Emitter Loop Analysis

Collector-Emitter Loop

KVLDirection

The magnitude of the collector currentIC is related to magnitude of basecurrent IB by current amplificationfactor ? .

IC = ? IB

Since IB is controlled by the value ofRB, hence as IC = ? IB, IC is not functionof RC. Therefore, change RC to anylevel and it will not affect the level ofIB or IC as long as we remain in activeregion of BJT output char. However,RC will determine the magnitude ofVCE, which is also an importantQ-point parameter.

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13/7/2004 Asst.Prof.Dr. MONTREE SIRIPRUCHYANUN 9Collector-Emitter Loop

KVLDirection

(a) Fixed bias circuit (continued)Collector-Emitter Loop Analysis

On applying the KVL in clockwise direction,one gets;

+ VCE + ICRC-VCC = 0 (1)On solving the eq(1) for VCE one gets;

VCE = VCC - ICRC (2)

It means VCE is supply voltage (VCC) minus dropacross RC.

One can write;

VCE = VC - VE (3)

VCE = Voltage from collector to emitterVC = Voltage from collector to groundVE = Voltage from emitter to ground

Since, VE = 0, hence VCE =VCSimilarly, VBE = VB - VE = VB - 0 = VB

VCEQ =VC and ICQ = ? IBQ


(a) Fixed bias circuit (continued)Transistor Saturation

The tern saturation is applied to any system where levels have reached their maximum values.For a transistor operating in the saturation region, the current is a maximum value for the particular design.With change in the design and the corresponding saturation level may rise or drop. The highest saturationlevel is defined by the maximum collector current of the selected BJT.

Saturation conditions are normally avoided because the base-collector junction is no longerreverse-biased and the output amplified signal will be distorted. An operating point in the saturation regionis depicted in Fig.1(a) (in next slide). Note that it is in a region where the characteristic curves join and thecollector-to-emitter voltage is at or below VCEsat. In addition, the collector current is relatively high on thecharacteristics.

If we approximate the curves of Fig.1a (in next slide) by those appearing in Fig.1b (in next slide),a quick, direct method for determining the saturation level becomes apparent. In Fig.1b, the current isrelatively high and the voltage VCE is assumed to be zero volts. Applying Ohm's law the resistance betweencollector and emitter terminals can be determined as follows:

RCE = VCE/IC = (0V)/ICsat = 0 ?Applying the results (RCE = 0 and VCE = 0) the network schematic would result in the

configuration of Fig.2 (in next slide).Therefore, if there is an immediate need to know the approximate maximum collector current

(saturation level) for a particular design, simply insert a short-circuit equivalent between collector andemitter of the transistor and calculate the resulting collector current. In short, set VCE = 0 V. For thefixed-bias configuration of Fig. 3 (in next slide) , the short circuit has been applied, causing the voltageacross RC to be the applied voltage VCC. The resulting saturation current for the fixed-bias configuration is;

ICsat = VCC/RCOnce ICsat is known, the designer will have some idea of the maximum possible collector current for achosen design and the level to stay below if designer expects to obtain linear (distortion free output)amplification.

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(a) Fixed bias circuit (continued)Transistor Saturation (Figures discussed in previous slide)

ICsat ICsat

VCEsat

Fig.1(a) Actualsaturation region Fig.1(b) Approximate

saturation region

Fig.2 Determining Icsat in a BJToperating in saturation region

Fig.3Determining Icsatfor the fixedbiasedconfiguration


(a) Fixed bias circuit (continued)Load Line Analysis

You have two things;

(a) Network made of the device (BJT in common emitterconfiguration): Network equation; VCE = VCC - ICRC(b) Characteristics (output char.) of the device

IC (mA)

VCE (V)ICEO

Increasingvalue of inputsignal (IB)

Network

Device Char.

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Through load line analysis the designer of BJT circuit attempts toobtain common solution from BJT network and BJT characteristics.The common solution so obtained provides of Q-point parameters(IBQ, ICQ, VCEQ) of a common emitter BJT. The BJT network and BJTchar. result in a common solution or same values of Q-pointparameters (IBQ, ICQ, VCEQ), this is due the reason that both (networkand char.) make use of same variables (VCE and IC). This commonsolution occurs at point in output char. of the BJT where theconstraints establish by each other are simultaneously satisfied. It issimilar to finding solution of two equation one established by networkand other established by device characteristics.



Steps in establishing the load line:1. Get device characteristics from the specification sheet of the BJT

2. Superimposed the line (straight line in case of fixed biased circuit) obtained fromthe network equation; VCE = VCC - ICRC: solving the network equation for y-axisvariable (IC) in output char of the device.

IC = -VCE/RC +VCC/RC {1} (this equation is just like y = mx+c, equation ofa straight line)

3. Define the line obtained from network equation. Since it is a straight line thereforecan be defined by two points.3(a) If in eq(1), VCE=0,hence IC = VCC/RC (Ist point ofthe straight line)

3(b) If in eq(1) IC=0,hence VCE = VCC (IInd point ofthe straight line)

A straight line represented byy =mx+c can be defined by two points.

If x = 0, y = c (Ist point)

If y = 0, x = c/m (IInd point)

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Obeying the three steps discussed in previous slide the designer willget fixed bias load line as shown below;

The load line obtained fromnetwork solution (straightline equation of thenetwork is solved to getload line) cross the devicecharacteristics at Q-point.The O-point is for a fixedcurrent (IBQ) at thebase-emitter loop (inputport) of the network usedfor fixed bias).

Fig. Fixed bias load line



Once the load line is establishedand Q-point parameters (IBQ, ICQ,VCEQ) are obtained [IBQ is obtainedfrom knowledge of theBase-Emitter Circuit of the biasingckt, ICQ and VCEQ obtained fromcrossing point where load linecrosses the output char], thedesigned is good to operate thesystem under varying ac inputsignal imposed before the inputcoupling capacitor C1 and outputsignal is obtained after the outputcoupling capacitor C2. Howeverchange in the system parametersmay cause the Q-point to changefrom one set value to another setvalue.

Input

Output


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(a) Fixed bias circuit (continued)Load Line Analysis & Change in Q-point due to change in IB

If VCC and RC arefixed and the levelof IB is changed byvarying the value ofRB the Q-pointsmoves up and downalong the load line.

IB increasing

Fig. Movement of Q-point with increasing levels of IB


(a) Fixed bias circuit (continued)Load Line Analysis & Change in Q-point due to change in VCC

If IB and RC are fixed andVCC is varied, the Q-pointswill move on IBQ curve ofthe output characteristics.This is due to shifting ofthe defining points [onecorresponding to IC=0 andother corresponding toVCE=0 in the equation ofthe network:IC = -VCE/RC +VCC/RC ] ofload line

Fig. Effect of lower value of VCC on the load line and Q-Point

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(a) Fixed bias circuit (continued)Load Line Analysis & Change in Q-point due to change in RC

If IB and VCC are fixed andRC is varied, the Q-pointswill move on IBQ curve ofthe output characteristics.This is due to shifting ofone of the defining points[corresponding to VCE=0 inthe equation of thenetwork:IC = -VCE/RC +VCC/RC ] ofload line

Fig. Effect of increasing levels of RC on the load line & Q-point


We have seen that out of all three parameters (RB, RC and VCC), the change in RB causes IB to changefrom one value and therefore the Q-point moves along the load line for a fixed value of RC and VCC.Since IB is in order of ?A and produces almost heating effect on RB. Therefore it can be assumed thatonce IB is fixed from design it is highly unlikely to change. The VCC is the supply battery voltage andcan not change under normal operating condition. The collector resistor RC is responsible to pass thepower through BJT in order to amplify the input ac signals. Therefore, the collector resistor RC is mostsusceptible to heating effect and can change and thereby causing the instability of Q-point. With theincrease in the RC the point moves towards saturation region and may invite the problem of distortion inoutput signal of BJT amplifier. Therefore, answer to this problem is a more stable biasing circuit which

is called as Emitter-Stabilized Bias Circuit.

Input

Output


Main Objectives ofEmitter StabilizedBias Circuit: Theemitter stabilized circuitnot only provide goodstability for possiblevariations in RC but also itmake the value of IB almostconstant and less dependentof RB.

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(b) Emitter-Stabilized Bias CircuitIn emitter stabilizedbiasing circuit, thedc bias networkcontains an emitterresistor to improvethe stability levelover the fixed biasconfiguration.

C1

C2

Vo

Vi

Fig. Emitter-StabilizedBias Circuit

In this case also to get the Q-point parameters, the dc analysisis divided into parts(a) Base-Emitter Loop(b) Collector-Emitter Loop


(b) Emitter-Stabilized Bias Circuit (Continued)

C1

C2

Vo

Vi


Base-EmitterLoop Collector-Emitter

Loop

Replacing the accoupling capacitor byopen circuit (As for dcsignals 1/wc? ? ) theBase-Emitter loopcircuit could be drawnas shown in next slide.

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(b) Emitter-Stabilized Bias Circuit (Continued)Base-Emitter Loop Analysis

Writing KVL for base-emitter loop thedesigner gets;

+ VCC - IBRB-VBE - IERE= 0 (1)But IE= IB(?+1), substituting IE in eq(1)the designer gets;+ VCC - IBRB-VBE - (?+1)IBRE= 0 (2)Solving eq(2) for IB designer gets;

IB = (VCC - VBE)/[RB +(?+1)RE] (3)

It is interesting to note that the term(?+1)RE is the only difference betweenequations for IB in case of fixed biascircuit and emitter stabilized bias circuit

The eq(3) can be represented by anetwork as shown in next slide.



Fig. Network derived from equation IB = (VCC - VBE)/[RB +(?+1)RE]

The term (?+1)RE isreflected asimpedance at inputbase terminal.

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Fig. Network derived from equationIB = (VCC - VBE)/[RB +(?+1)RE]

Reflected impedance level of RE. Since?=50 to 400, hence RE appears at input sidewith a great large value



In an Emitter-Stabilized Bias Circuit thenetwork equation

IB = (VCC - VBE)/[RB +(?+1)RE]

suggests that net voltage in Base-Emitterloop is VCC - VBE. The resistance level areRB Plus RE reflected by (?+1) times.

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(b) Emitter-Stabilized Bias Circuit (Continued)Collector-Emitter Loop Analysis

Collector-Emitter Loop ofEmitter Stabilized Bias Circuit

Writing KVL+ IERE + VCE - ICRC+ VCC= 0 (1)

Since, IE ? IC (for ? ?1)

Hence, eq(1) can be written as;

+ ICRE + VCE - ICRC+ VCC= 0 (2)

Solving eq(2) for VCE the designer gets;

VCE = VCC - IC(RC+ RE)

VE = Emitter voltage with respect to ground= IERE

While, VCE = VC - VE (3)Hence, VC = VCE + VE orVC = VCC - ICRCVoltage at base with respect to ground can bedetermined fromVB = VCC - IBRB or

VB = VBE + VE


(b) Emitter-Stabilized Bias CircuitIn emitter stabilizedbiasing circuit, thedc bias networkcontains an emitterresistor to improvethe stability levelover the fixed biasconfiguration.

C1

C2

Vo

Vi


In this case also to get the Q-point parameters, the dc analysisis divided into parts(a) Base-Emitter Loop(b) Collector-Emitter Loop

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(b) Emitter-Stabilized Bias Circuit (Continued)

C1

C2

Vo

Vi


Base-EmitterLoop Collector-Emitter

Loop

Replacing the accoupling capacitor byopen circuit (As for dcsignals 1/wc? ? ) theBase-Emitter loopcircuit could be drawnas shown in next slide.



Writing KVL for base-emitter loop thedesigner gets;

+ VCC - IBRB-VBE - IERE= 0 (1)But IE= IB(?+1), substituting IE in eq(1)the designer gets;+ VCC - IBRB-VBE - (?+1)IBRE= 0 (2)Solving eq(2) for IB designer gets;

IB = (VCC - VBE)/[RB +(?+1)RE] (3)

It is interesting to note that the term(?+1)RE is the only difference betweenequations for IB in case of fixed biascircuit and emitter stabilized bias circuit

The eq(3) can be represented by anetwork as shown in next slide.

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Fig. Network derived from equation IB = (VCC - VBE)/[RB +(?+1)RE]

The term (?+1)RE isreflected asimpedance at inputbase terminal.



Fig. Network derived from equationIB = (VCC - VBE)/[RB +(?+1)RE]

Reflected impedance level of RE. Since?=50 to 400, hence RE appears at input sidewith a great large value

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In an Emitter-Stabilized Bias Circuit thenetwork equation

IB = (VCC - VBE)/[RB +(?+1)RE]

suggests that net voltage in Base-Emitterloop is VCC - VBE. The resistance level areRB Plus RE reflected by (?+1) times.


(b) Emitter-Stabilized Bias Circuit (Continued)Collector-Emitter Loop Analysis

Collector-Emitter Loop ofEmitter Stabilized Bias Circuit

Writing KVL+ IERE + VCE + ICRC - VCC= 0 (1)

Since, IE ? IC (for ? ?1)

Hence, eq(1) can be written as;

+ ICRE + VCE + ICRC - VCC= 0 (2)

Solving eq(2) for IC the designer gets;

IC = VCC/(RE+RC) - VCE/(RC+ RE)

VE = Emitter voltage with respect to ground= IERE

While, VCE = VC - VE (3)Hence, VC = VCE + VE orVC = VCC - ICRCVoltage at base with respect to ground can bedetermined fromVB = VCC - IBRB or

VB = VBE + VE

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(b) Emitter-Stabilized Bias Circuit (Continued)Transistor Saturation

The collector current in an EmitterStabilized biasing circuit is expressed as;

IC = VCC/(RE+RC) - VCE/(RC+ RE)

The saturation level or maximumcollector current results in by settingVCE =0 (putting a circuit across collectorand emitter terminals of the BJT).

ICsat = VCC/(RE+RC)


(b) Emitter-Stabilized Bias Circuit (Continued)Load Line Analysis (determining the Q-point parameters)In emitter stabilized biasing circuit the load line analysis followssame steps as we have done in case of fixed bias circuit.

Fig. Load line foremitter stabilizedbiasing circuit

The load line is represented by astraight line. This straight line isobtained by applying KVL atcollector-emitter and solving theequation for collector current (IC). Thecollector current in an EmitterStabilized biasing circuit is expressedas;

IC = VCC/(RE+RC) - VCE/(RC+ RE)[equation of a straight line].

This line can be represented by twopoints, one for IC=0 [this will giveVCE=VCC] and other for VCE=0 [thiswill give IC=VCC/ (RE+RC)]

The load line crosses the outputcharacteristics at Q-point

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(b) Emitter-Stabilized Bias Circuit (Continued)Parameter Sensitivity

In case of Emitter-Stabilized Bias Circuit the input current obtainedfrom the analysis of input loop (Base-Emitter Loop). This current isexpressed in terms of circuit parameters and BJT currentamplification parameter.

IB = (VCC - VBE)/[RB +(?+1)RE]The current IB =decides IBQ line in output char. of BJT.

Since IB is function of BJT parameter ? . The BJT parameter ? is verysensitive to temperature variation. Therefore is can be said that IBQcurve is sensitive to temperature variation. This results in VCEQ aswell as ICQ to be the temperature sensitive Q-point parameters.Therefore all three (ICQ, VCEQ, IBQ) Q-point parameters aretemperature sensitive in case of an Emitter stabilized biasing circuit.


(b) Emitter-Stabilized Bias Circuit (Continued)Parameter Sensitivity

We have seen that the Emitter-Stabilized Bias Circuit of the BJT isable to eliminate some of the problems faced in fixed bias circuit.However, the Emitter-Stabilized Biasing Circuits invites some newproblems that is temperature sensitivity of IBQ. The current IBQ in turnbrings in temperature sensitivity in parameters VCEQ and ICQ. This alldue to temperature dependent current amplification factor (? )appearing in input loop equation;

IB = (VCC - VBE)/[RB +(?+1)RE]The Voltage Divider Based Biasing Circuit is answer to this problem.This is due to the reason that in case of Voltage Divider BasedBiasing Circuit, the equation are less dependent or altogetherindependent of ? .

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(c) Voltage-Divider Bias CircuitIn the emitter stabilized configuration the bias current ICQ and biasvoltage VCEQ are function of current gain (? ) of the BJT.

Since ? is temperature sensitive, hence it is desirable to develop abias circuit that is less dependent, or in fact independent of ? . Thevoltage divider configuration of biasing circuits is such a network.

This circuit is lesssensitive to change in ? . Ifcircuit parameters areproperly chosen, theresulting level of ICQ andVCEQ can be almostindependent of ? .

Vo

R1

Vi

VCC

C2 C1

RE R2

RC

Fig: Voltage-Divider Bias Circuit


(c) Voltage-Divider Bias Circuit (Continued)Analysis of Base-Emitter Loop

The base-emitter loop of voltage divider bias circuit can be redrawnas follows; To obtain the input

current (IB) this networkmust be solved for IB. Tosolve this network forcurrent IB, we need toapply Thevenin theoremto obtain equivalentnetwork. To obtainequivalent network weneed to obtain Theveninequivalent voltage (VTH)and resistance (RTH) ofthe input network of thevoltage divider biasingcircuit.

Fig. Base-Emitter Loopof Voltage DividerBiasing Circuit

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(c) Voltage-Divider Bias Circuit (Continued)Analysis of Base-Emitter Loop

Determining the Thevenin Equivalent Resistance(RTH)

RTH=R1R2/(R1+R2)

Determining the Thevenin Equivalent Voltage(VTH)

ETH=R2VCC/(R1+R2)

Fig. Base-Emitter Loop with theveninequivalent for input circuit of voltage

divider biasing circuit

The input current equation will beexpressed as;

IB = (ETH-VBE)/[RTH+(?+1)RE]


(c) Voltage-Divider Bias Circuit (Continued)Analysis of Collector-Emitter Loop

The analysis of outer loop or collector-emitterloop results in an equation for load line. Theequation obtained from outer loop is expressed as;

VCE=VCC-IC(RC+RE)The equation for load line is expressed as;

IC=-VCE/(RC+RE) + VCC/(RC+RE) The two points defining the line are

Ist point: [0, VCC/(RC+RE)] for VCE=0

IInd point [VCC, 0] for ICE=0

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(c) Voltage-Divider Bias Circuit (Continued)Load Line Analysis

VCC

VCC/(RE+RC) Fig. Defining the Q-pointparameters in a Voltage DividerConfiguration of Biasing Circuit


(c) Voltage-Divider Bias Circuit (Continued)Transistor in Saturation

To decide the maximum value of the collectorcurrent and therefore to say that transistor hasreached the saturation limit. We must enter in therange where VCE ? 0.

We have load line equation in case of VoltageDivider Biasing Circuit as;

IC=-VCE/(RC+RE) + VCC/(RC+RE)To get saturation current we must VCE = 0.ICsat = ICmax =VCE/(RC+RE)

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(d) Voltage Feedback Bias CircuitAn improved level of stability can also be obtained by introducing a feedback path fromcollector to base. Although the Q-point is not totally independent of ? , the sensitivity tochanges in ? or temperature variations is normally less than encountered for thefixed-bias or emitter stabilized biasing circuits.

Vi

Vo

Fig. DC bias circuit withvoltage feedback

To analyze this circuit and to findout Q-point parameters using loadline concept, the analysis is dividedinto two parts(a) Base-Emitter (Input) Loop(b) Collector-Emitter (Output) Loop


(d) Voltage Feedback Bias CircuitBase-Emitter Loop Analysis

VCC

The Base-Emitter (input) loop of the voltage feedback bias circuit canbe drawn as shown below; On writing KVL for this loop the

designer gets;

VCC - IC1RC - IBRB- VBE -IERE=0 (1)

The current through RC is not IC butIC1 (where IC1=IC+IB). Since IB is in?A and IC is in mA. ThereforeIC1 ? IC = ? IB and IE ? IC (for ? ? 1).

On substituting theseapproximations, the eq(1) can bewritten as;

VCC - ? IBRC - IBRB- VBE - ? IBRE=0 (2)

Solving eq(2) for IB the designergets;

IB = (VCC - VBE)/[RB +? (RC+RE)]

iC1

iC

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(d) Voltage Feedback Bias CircuitDiscussion about input current in biasing circuits


(d) Voltage Feedback Bias CircuitCollector-Emitter Loop Analysis

iC1

Fig. Collector-Emitter Loop ofVoltage Feedback Bias Circuit

Writing KVL for Collector-Emitter (Output)Loop the designer gets;IERE + VCE + IC1RC - VCC = 0 (1)Since, IC1 ? IC and IE ? IC (for ? ? 1). The eq(1) can be rearrange as;IC(RC + RE) + VCE - VCC = 0 (2)Therefore, the equation for load line isexpressed as;IC=-VCE/(RC+RE) + VCC/(RC+RE) (3)This is same as obtained in case of EmitterStabilized bias circuit as well as VoltageDivider Bias Circuit. The two points defining the line areIst point: [0, VCC/(RC+RE)] for VCE=0IInd point [VCC, 0] for ICE=0

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VCC

VCC/(RE+RC) Fig. Defining the Q-pointparameters in a Voltage DividerConfiguration of Biasing Circuit

(d) Voltage Feedback Bias CircuitLoad-Line Analysis


(d) Voltage Feedback Bias CircuitSaturation Conditions

Using the approximation IC1 ? IC, the equation forsaturation conditions is same as obtained in case of emitterstabilized and voltage divider biasing circuits. To decidethe maximum value of the collector current and therefore tosay that transistor has reached the saturation limit. We mustenter in the range where VCE ? 0.

We have load line equation in case of Voltage FeedbackBiasing Circuit as;

IC=-VCE/(RC+RE) + VCC/(RC+RE)To get saturation current we must VCE = 0.ICsat = ICmax =VCE/(RC+RE)

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Bias Stabilization in BJT Circuits

The Q-point stability of a system is a measure of the sensitivity of aBJT circuit to variations in its parameters.

In any amplifier employing a transistor the collector current IC issensitive to each of the following parameters:

? : increases with increase in temperatureVBE: decreases about 7.5 mV per degree Celsius (?C) increase in

temperatureICO: (reverse saturation current): doubles in value for every 10°C

increase in temperature


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ICEO = ?ICBO ICEO = ?ICBO

Effect of Changes in Leakage Current (ICO) and Currentgain (? ) on dc bias point (Q-point)

At 250C At 1000C


Stability Factors: S(ICO), S(VBE), and S(? )

A stability factor, S, is defined for each of the parameters(ICO, VBE and ? ) affecting bias stability as listed below:

Here, symbol delta (? ) signifies changein the quantity. The numerator of eachequation is the change in collectorcurrent as established by the change inthe quantity in the denominator. Let ussay if a change in ICO fails to produce asignificant change in IC, the stabilityfactor defined by S(ICO) = ? IC/? ICO willbe quite small.

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Networks that are quite stable and relativelyinsensitive to temperature variations have lowstability factors.

The higher the stability factor; the moresensitive the network to variations in thatparameter.


Derivation of stability factor S(ICO)

See file Lect-Set.17.doc

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Stability Factor S(ICO) for different types of bias circuits

Emitterstabilized ckt

= (?+1) Fixedbias ckt

Voltage dividerbias ckt

Voltage feedbackbias ckt


Emitter StabilizedBias Circuit

Variation of Stability Factor S(ICO) with systemparameters of Emitter Stabilized Bias Circuit

Stability Factor S(ICO)of Emitter Stabilized

Bias Ckt

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Emitter Stabilized Bias Circuit: Variation of stabilityfactor S(ICO) with respect to RB/RE


(a) For RB/RE >>> (? +1)

S(ICO) = ?+1

(b) RB/RE <<1

(c) For the range: <1RB/RE < (? + 1),S(ICO) ? RB/RE

Stability Factor S(ICO) of EmitterStabilized Bias Ckt

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The stability factor S(ICO) will approach its lowest level as REbecomes sufficiently large. However, good bias control normallyrequires that RB be greater than RE. The result therefore is a situationwhere the best stability levels are associated with poor design criteria.Therefore, a trade-off must occur that will satisfy both the stabilityand bias specifications. It is also interesting to note in Figure belowthat the lowest value of S(ICO) is 1, this reveals that IC will alwaysincrease at a rate equal to or greater than ICO.


Stability Factor S(ICO) for Fixed Bias Circuit

The stability factor S(ICO) for fixed bias circuit isexpressed as;

S(ICO) = ?+1

The S(ICO) for fixed bias circuit matches to maximumvalue for emitter stabilized bias circuit. Therefore, it canbe said that fixed bias circuit exhibits a poor stabilityand high sensitivity to variations in ICO or in other wordsthe fixed bias circuit is most susceptible to temperaturevariations.

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Stability Factor S(ICO) for Voltage Divider Bias Circuit

Voltage DividerBias Circuit

Stability Factor S(ICO) ofVoltage Divider Bias Ckt


Here;

RTh = (R1R2)/( R1+ R2)

Therefore, S(ICO) has its greatest stability when ratioRTh/RE has smallest possible value. For voltage dividerbias circuit the resistance RTh can be much less than thecorresponding RB in emitter stabilized bias circuit and stillthe designer gets a good design.


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Stability Factor S(ICO) for Voltage Feedback Bias Circuit

Voltage FeedbackBias Circuit


In voltage feedback bias circuit thebiasing point (Q-point) is moststable when ratio RB/RC approachesto zero value or very close to zero.But this will result into a poordesign of ckt.

Documents

04 Biasing Circuits of the BJTmsn/213332han04.pdf · Get device characteristics from the specification sheet of the BJT 2. Superimposed the line (straight line in case of fixed biased