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    Verilog/Digital FAQS  By  Verilog Course Team  Email:[email protected]  Www.vlsifaqs.blogspot.com 

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  • 8/14/2019 Verilog/Digital FAQS By Verilog Course Team Email:[email protected] Www.vlsi faqs.blogspot.com

    1/7Verilog Course Team www.verilogcourseteam.com

    Verilog/DigitalFAQS

    By

    VerilogCourseTeam

    Email:[email protected]

    www.vlsi-faqs.blogspot.com

    www.verilogcourseteam.com

  • 8/14/2019 Verilog/Digital FAQS By Verilog Course Team Email:[email protected] Www.vlsi faqs.blogspot.com

    2/7Verilog Course Team www.verilogcourseteam.com

    DISCLAIMER

    Verilog Course Team does not warrant or assume any legal liability or responsibility for the

    accuracy, completeness, or usefulness of any information, apparatus, product, or process

    disclosed. No warranty of any kind, implied, expressed or statutory, including to fitness for

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    contents of this document or its hyperlinks to other Internet resources. Reference in this

    document to any specific commercial products, processes, or services, or the use of any

    trade, firm or corporation name is for the information, and does not constitute

    endorsement, recommendation, or favoring.

  • 8/14/2019 Verilog/Digital FAQS By Verilog Course Team Email:[email protected] Www.vlsi faqs.blogspot.com

    3/7Verilog Course Team www.verilogcourseteam.com

    About Verilog Course Team

    Verilog Course Team is a Electronic Design Services (EDS) for VLSI / EMBEDDED and

    MATLAB, delivering a wide variety of end-to-end services , including design ,

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  • 8/14/2019 Verilog/Digital FAQS By Verilog Course Team Email:[email protected] Www.vlsi faqs.blogspot.com

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    Verilog Course Team www.verilogcourseteam.com

    1.Designacircuit(positiveedge)thatdetectthesequencewheninputchanges

    from0to1,theoutputshouldgohighforonlyoneclockpulse.

    clk

    rst

    in

    out

    2.Designacircuittodetectwhenthe216bitsinputsaresame.

    3.Assumeb=3andc=5,afterthefirst@(posedgeclk)whatisthevalueofa?

    4.Afterthefirst@(posedgeclk),doesthisdoaswap?

  • 8/14/2019 Verilog/Digital FAQS By Verilog Course Team Email:[email protected] Www.vlsi faqs.blogspot.com

    5/7

    Verilog Course Team www.verilogcourseteam.com

    5.Considerthefollowingcode:

    `defineFALSE0

    `defineTRUE1

    initial

    begin

    a=`FALSE;

    a

  • 8/14/2019 Verilog/Digital FAQS By Verilog Course Team Email:[email protected] Www.vlsi faqs.blogspot.com

    6/7

    Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver

    14.Whatwillbethesynthesisstructure?

  • 8/14/2019 Verilog/Digital FAQS By Verilog Course Team Email:[email protected] Www.vlsi faqs.blogspot.com

    7/7

    Verilog Course Team www.verilogcourseteam.com

    15.Considerthefollowingcode,

    always@(posedgeclk)

    begin

    a=b;

    b=c;

    c=a;

    end

    Whatlogicdoesthecodeimplies.


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