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Preliminary Product Brief October 2001 70/)6XSHUPDSSHU/LWH 0ELWVV621(76'+[['6( Features Versatile IC supports 155/51 Mbits/s SONET/SDH interface solutions for T3 and T1/E1/J1. Implementation supports both linear (1 + 1, unpro- tected) and ring (UPSR) network topologies. Provides full-trail termination of up to 21 E1, 28 T1, or 28 J1. Low-power 3.3 V supply. 40 C to +85 C industrial temperature range. 456-pin ball grid array (PBGA) package. Complies with, but not limited to, the following: Telcordia Technologies , ITU, ANSI , ETSI, ATT-TR, and Japanese TTC standards. SONET/SDH Interface Termination of a single 155 Mbits/s STS-3/STM-1 or single 51 Mbits/s STS-1/STM-0. Built-in clock and data recovery circuit at 155 Mbits/s STS-3/STM-1 interface (can be dese- lected if external clock recovery is provided). Supports overhead processing for all transport and path overhead bytes. Optional insertion and extraction of overhead bytes via a serial transport overhead access channel. Configurable as dedicated DCC channels. Software-controlled linear 1 + 1 protection via dedi- cated interface-to-protection card. Full-path termination and SPE extraction/insertion. SONET/SDH compliant condition and alarm report- ing. Built-in diagnostic loopback modes. 8 kHz line frame sync output. STS/STM Pointer Interpreter Interprets STS/AU/TU-3 pointers. Synchronizes 8 kHz frame and 2 kHz superframe to system/shelf timing reference by setting the transmit STS-3/STM-1 pointers to a fixed value of 522. Monitors/terminates SPE path overhead. Telecom Bus Interface Telecom bus interface to mate devices including clock, data[8], parity, SPE-, J0-, J1-, and V1- timing indicator. Line and path RDI and REI signals passed to mate devices. VT Termination/Generation (x28/x21) Monitors/terminates VT path overhead for 28 VT1.5/TU-11 or 21 VT2/TU-12. Synchronizes VT/TU SPE to system/shelf timing ref- erence by setting the transmit VT/TU pointers to fixed values for asynchronous mapping or by dynamically changing the transmit VT/TU pointers for byte synchronous mapping. Fixed pointer generation in transmit side for asyn- chronous mapping. Dynamic pointer generation in transmit side for byte- synchronous mapping. Mapping/Multiplexing Modes (x28/x21) Maps DS3 clear channel or framed signal into STS-1 or TUG-3. Maps T1/E1/J1 into VT/TU (including DS1 into TU-12). Supports asynchronous, byte-synchronous, and bit- synchronous mapping. There is no signal support in the case of byte-synchronous mapping. Supports UPSR applications via the dedicated ring interface and an external tributary selector. Supports all valid T1/E1/J1 multiplexing structures into STS-1 and STS-3/STM-1: STS-3/STS-1/SPE/VTG/VTx STM-1/AU-3/TUG-2/TU-1x/VC-1x STM-1/AU-4/TUG-3/TUG-2/TU-1x/VC-1x Allows grooming of VTs/TUs in granularity of TUG-2s within the STS-3/STM-1 signal. Supports J2 trace identifier monitoring/insertion. Configurable VT/TU slot selection for DS1, E1, and J1 insertion and drop.

˘ ˇˆ ˙ ˙ ˇ - 达普IC芯片交易网,采购IC ... IC supports 155/51 Mbits/s SONET/SDH interface ... It provides a versatile interface for all STS-3/STM-1 ... This chip can be

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Page 1: ˘ ˇˆ ˙ ˙ ˇ - 达普IC芯片交易网,采购IC ... IC supports 155/51 Mbits/s SONET/SDH interface ... It provides a versatile interface for all STS-3/STM-1 ... This chip can be

Preliminary Product BriefOctober 2001

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Features

■ Versatile IC supports 155/51 Mbits/s SONET/SDH interface solutions for T3 and T1/E1/J1.

■ Implementation supports both linear (1 + 1, unpro-tected) and ring (UPSR) network topologies.

■ Provides full-trail termination of up to 21 E1, 28 T1, or 28 J1.

■ Low-power 3.3 V supply.■ �40 °C to +85 °C industrial temperature range.■ 456-pin ball grid array (PBGA) package.■ Complies with, but not limited to, the following:

Telcordia Technologies®, ITU, ANSI ®, ETSI, ATT-TR, and Japanese TTC standards.

SONET/SDH Interface

■ Termination of a single 155 Mbits/s STS-3/STM-1 or single 51 Mbits/s STS-1/STM-0.

■ Built-in clock and data recovery circuit at 155 Mbits/s STS-3/STM-1 interface (can be dese-lected if external clock recovery is provided).

■ Supports overhead processing for all transport and path overhead bytes.

■ Optional insertion and extraction of overhead bytes via a serial transport overhead access channel. Configurable as dedicated DCC channels.

■ Software-controlled linear 1 + 1 protection via dedi-cated interface-to-protection card.

■ Full-path termination and SPE extraction/insertion.■ SONET/SDH compliant condition and alarm report-

ing.■ Built-in diagnostic loopback modes.■ 8 kHz line frame sync output.

STS/STM Pointer Interpreter

■ Interprets STS/AU/TU-3 pointers.

■ Synchronizes 8 kHz frame and 2 kHz superframe to system/shelf timing reference by setting the transmit STS-3/STM-1 pointers to a fixed value of 522.

■ Monitors/terminates SPE path overhead.

Telecom Bus Interface

■ Telecom bus interface to mate devices including clock, data[8], parity, SPE-, J0-, J1-, and V1- timing indicator.

■ Line and path RDI and REI signals passed to mate devices.

VT Termination/Generation (x28/x21)

■ Monitors/terminates VT path overhead for 28 VT1.5/TU-11 or 21 VT2/TU-12.

■ Synchronizes VT/TU SPE to system/shelf timing ref-erence by setting the transmit VT/TU pointers to fixed values for asynchronous mapping or by dynamically changing the transmit VT/TU pointers for byte synchronous mapping.

■ Fixed pointer generation in transmit side for asyn-chronous mapping.

■ Dynamic pointer generation in transmit side for byte-synchronous mapping.

Mapping/Multiplexing Modes (x28/x21)

■ Maps DS3 clear channel or framed signal into STS-1 or TUG-3.

■ Maps T1/E1/J1 into VT/TU (including DS1 into TU-12).

■ Supports asynchronous, byte-synchronous, and bit-synchronous mapping. There is no signal support in the case of byte-synchronous mapping.

■ Supports UPSR applications via the dedicated ring interface and an external tributary selector.

■ Supports all valid T1/E1/J1 multiplexing structures into STS-1 and STS-3/STM-1:� STS-3/STS-1/SPE/VTG/VTx� STM-1/AU-3/TUG-2/TU-1x/VC-1x� STM-1/AU-4/TUG-3/TUG-2/TU-1x/VC-1x

■ Allows grooming of VTs/TUs in granularity of TUG-2s within the STS-3/STM-1 signal.

■ Supports J2 trace identifier monitoring/insertion.■ Configurable VT/TU slot selection for DS1, E1, and

J1 insertion and drop.

Page 2: ˘ ˇˆ ˙ ˙ ˇ - 达普IC芯片交易网,采购IC ... IC supports 155/51 Mbits/s SONET/SDH interface ... It provides a versatile interface for all STS-3/STM-1 ... This chip can be

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Features ��� � ����

■ Automatic receive monitor functions include VT/TU RDI-V, REI-V, BIP-2 errors, AIS-V, and LOP-V.

■ Complies with GR-253-CORE, GR-499, and ITU-T G.707, G.704, G.783, T1.105, JT-G707, and ETS 300 417-1-1.

M13 Features

■ Configurable multiplexer/demultiplexer for 28 DS1 signals, 21 E1 signals, or seven DS2 signals to/from a DS3 signal.

■ Operates in either M23 or C-bit parity mode.

■ Provisionable time-slot selection for DS1, E1, and DS2 insertion or drop.

■ Full alarm monitoring and generation (LOS, BPV, EXZ, OOF, SEF, AIS, RAI, FEAC, P-bit and C-bit par-ity errors, FEBE).

■ HDLC transmitter with 128-byte data buffer and HDLC receiver with 128-byte data FIFO for the C-bit parity path maintenance data link.

■ DS3, DS2, DS1, and E1 loopback and loopback request generation.

■ Complies with T1.102, T1.107, T1.231, T1.403, T1.404, GR 499, G.747, and G.775.

DS3/DS2/DS1/E1 Cross Connect

■ Highly configurable interconnect for up to 28 DS1 or 21 E1 signals to/from the PMON, external pins, M13, or VT mappers.

■ Supports up to seven DS2 signals to/from the exter-nal pins or M13.

■ Sources may be broadcast, looped back, or routed to/from a test-pattern generator or monitor.

■ Any DS1 or E1 channel may be routed through the jitter attenuator.

■ DS3 may be configured for the M13 to interconnect with the SPE, or for the external I/O to interconnect with the M13 or SPE.

Jitter Attenuation

■ PLL-free receive operation using built-in digital jitter attenuator (in VT/VC mode or M13 mode).

■ Configurable to meet jitter and MTIE requirements.

PDH Interfaces

■ One DS3.

■ x28/x21 framed DS1 or E1 interfaces.

■ One additional dedicated protection channel for DS1/E1.

Performance Monitor (PMON)

■ Alarm reporting and performance monitoring per AT&T ®, ANSI, ITU-T, and ETSI standards.

■ Monitors transmit and receive line data (DS1/E1).

■ Alarm conditions and error events report to the sys-tem via microprocessor registers.

System Test and Maintenance

■ A variety of loopback modes implemented on SONET/SDH side.

■ Built-in test pattern generator and monitor config-urable for simultaneously testing E1, DS1, and DS3 (one channel each).

Microprocessor Interface

■ 20-bit address and 16-bit data interface with 16 MHz to 66 MHz read and write access.

■ Compatible with most industry-standard processors.

Chip Testing and Maintenance

■ IEEE ® 1149.1 JTAG boundary scan.

Interface to Other Agere Systems Devices

Seamless interface to the following Agere Systems devices:

■ OC-3 optics (1417).■ STS-1/DS3 LIU (T7295, T7296).■ DS1/E1 LIU (T7698, TLIU04C1).■ ATM physical layer.■ TDAM 04265.

Page 3: ˘ ˇˆ ˙ ˙ ˇ - 达普IC芯片交易网,采购IC ... IC supports 155/51 Mbits/s SONET/SDH interface ... It provides a versatile interface for all STS-3/STM-1 ... This chip can be

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Overview

The SONET/SDH TMLF28155 device integrates the SONET/SDH line, path, and tributary termination functions with M13 multiplex functions and performance-monitoring features. It is designed to drive an OC-3/STM-1 optical signal directly, or to allow for modular growth in terminal or add/drop applications.

It provides a versatile interface for all STS-3/STM-1 and STS-1 termination applications in point-to-point scenarios and for ring applications. This chip can be used in tributary shelf applications for up to 28 T1, J1, or 21 E1 line cards providing all possible mappings into SONET/SDH. Because of the flexibility of the mappings, software upgrades from M13 mapped connections to VT/TU mapped connections are possible. This device can also be used for DS3 applications.

A single TMLF28155 is capable of processing the aggregate bandwidth of one STS-1 or DS3. By communicating to two other mate devices via the telecom bus interface, the TMLF28155 is capable of terminating a full STS-3/STM-1 signal.

5-8923(F)

Figure 1. Functional Diagram of the TMLF28155

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Overview (continued)

Note: MAPPER = VT mapper and M13 multiplexer5-8652(F)a

Figure 2. Transport Application of the TMLF28155

CROSS MAPPER

MAPPER

MAPPER

MAPPER

MAPPER

MAPPER

TMLF28155 #1 TMLF28155 #1

TMLF28155 #2 TMLF28155 #2

TMLF28155 #3TMLF28155 #3

MAPPERTELECOM

BUS

STS-3

LINEINTERFACE

LINEINTERFACE

T1/E1TERMINATION

(T7698)

CONNECT

CROSSCONNECT

CROSSCONNECT

DS1/E1INTERFACE

CROSSCONNECT

CROSSCONNECT

CROSSCONNECT

T1/E1TERMINATION

(T7698)

DS1/E1INTERFACE

Page 5: ˘ ˇˆ ˙ ˙ ˇ - 达普IC芯片交易网,采购IC ... IC supports 155/51 Mbits/s SONET/SDH interface ... It provides a versatile interface for all STS-3/STM-1 ... This chip can be

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Notes

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