© Digital Integrated Circuits 2nd Devices VLSI Devices Intuitive understanding of device operation Fundamental analytic models Manual Models Spice

© Digital Integrated Circuits2nd Devices

VLSI DevicesVLSI Devices

Intuitive understanding of device operation

Fundamental analytic models Manual Models Spice Models

Secondary and deep-sub-micron effects Junction Diode and FET Resistor and Capacitor


The DiodeThe Diode

n

p

p

n

B A SiO2Al

A

B

Al

A

B

Cross-section of pn-junction in an IC process

One-dimensionalrepresentation diode symbol

Occurs as parasitic element in Digital ICs


Depletion RegionDepletion Regionhole diffusion

electron diffusion

p n

hole driftelectron drift

ChargeDensity

Distancex+

-

ElectricalxField

x

PotentialV

W2-W1

(a) Current flow.

(b) Charge density.

(c) Electric field.

(d) Electrostaticpotential.


Forward BiasForward Bias

x

pn0

np0

-W1 W20p n

(W2)

n-regionp-region

Lp

diffusion

Forward Bias usually avoided in Digital ICs


Reverse BiasReverse Bias

x

pn0

np0

-W1 W20n-regionp-region

diffusion

Diode Isolation Mode


Diode CurrentDiode Current

)1( / kTVsD

DeII


Models for Manual AnalysisModels for Manual Analysis

VD

ID = IS(eVD/T – 1)+

–

VD

+

–

+

–VDon

ID

(a) Ideal diode model (b) First-order diode model

)1( / kTVsD

DeII


Junction CapacitanceJunction Capacitance


Diffusion Capacitance Diffusion Capacitance (Forward Bias)(Forward Bias)


Secondary EffectsSecondary Effects

–25.0 –15.0 –5.0 5.0

VD (V)

–0.1

I D (A

)

0.1

0

0

Avalanche Breakdown


Diode Model (Manual Analysis)Diode Model (Manual Analysis)

ID

RS

CD

+

-

VD


SPICE ParametersSPICE Parameters

Transit time models charge storage


What is a Transistor?What is a Transistor?

Resistor is poor model in saturation– current source

Source and Drain are symmetric N-channel: Source is most

negative of the two P-channel: Source is most

positive of the two Four Modes:

Off (leakage current only) Sub-Threshold (exponential) Linear (Resistive) Saturation (Current Source)

VGS VT

RonS D

A Switch!


The MOS TransistorThe MOS Transistor

Polysilicon Aluminum


MOS Transistors -MOS Transistors -Types and SymbolsTypes and Symbols

D

S

G

D

S

G

G

S

D D

S

G

NMOS Enhancement NMOS

PMOS

Depletion

Enhancement

B

NMOS withBulk Contact


Threshold Voltage: ConceptThreshold Voltage: Concept

n+n+

p-substrate

DSG

B

VGS

+

-

Depletion

Region

n-channel


The Threshold VoltageThe Threshold Voltage


The Body EffectThe Body Effect

-2.5 -2 -1.5 -1 -0.5 00.4

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

VBS

(V)

VT (

V)


QuadraticRelationship

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10

-4

VDS (V)

I D (

A)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Resistive Saturation

VDS = VGS - VT

Current-Voltage Relation Current-Voltage Relation


Transistor in LinearTransistor in Linear

n+n+

p-substrate

D

SG

B

VGS

xL

V(x) +–

VDS

ID

MOS transistor and its bias conditions


Transistor in SaturationTransistor in Saturation

n+n+

S

G

VGS

D

VDS > VGS - VT

VGS - VT+-

Pinch-offRegion


Current-Voltage RelationsCurrent-Voltage RelationsLong-Channel DeviceLong-Channel Device


A model for manual analysisA model for manual analysis


Current-Voltage Relations:Current-Voltage Relations:Deep-Submicron FETDeep-Submicron FET

LinearRelationship

-4

VDS (V)0 0.5 1 1.5 2 2.5

0

0.5

1

1.5

2

2.5x 10

I D (

A)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Early Saturation


Velocity SaturationVelocity Saturation

(V/µm)c = 1.5

n

(m/s

)

sat = 105

Constant mobility (slope = µ)

Constant velocity


PerspectivePerspective

IDLong-channel device

Short-channel device

VDSVDSAT VGS - VT

VGS = VDD


IIDD versus V versus VGSGS

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10

-4

VGS (V)

I D (

A)

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

-4

VGS (V)

I D (

A)

quadratic

quadratic

linear

Long Channel Short Channel


IIDD versus V versus VDSDS

-4

VDS (V)0 0.5 1 1.5 2 2.5

0

0.5

1

1.5

2

2.5x 10

I D (

A)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10

-4

VDS (V)

I D (

A)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

ResistiveSaturation

VDS = VGS - VT

Long Channel Short Channel


A unified modelA unified modelfor manual analysisfor manual analysis

S D

G

B


Simple Model versus SPICE Simple Model versus SPICE

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

-4

VDS

(V)

I D (

A)

VelocitySaturated

Linear

Saturated

VDSAT=VGT

VDS=VDSAT

VDS=VGT


A PMOS TransistorA PMOS Transistor

-2.5 -2 -1.5 -1 -0.5 0-1

-0.8

-0.6

-0.4

-0.2

0x 10

-4

VDS (V)

I D (

A)

VGS = -1.0V

VGS = -1.5V

VGS = -2.0V

VGS = -2.5V


Transistor Model Transistor Model for Manual Analysisfor Manual Analysis

0.5 m Vt Gamma Vd(sat) k’ (A/V2) Lambda

NMOS 0.7-0.8 0.48 3.1 50-60 0.04*

PMOS -0.91-

-0.97

0.59 -6.5 -17--20

-0.07*


The Transistor as a SwitchThe Transistor as a Switch

VGS VT

RonS D

ID

VDS

VGS = VD D

VDD/2 VDD

R0

Rmid

ID

VDS

VGS = VD D

VDD/2 VDD

R0

Rmid



0.5 1 1.5 2 2.50

1

2

3

4

5

6

7x 10

5

VDD

(V)

Req

(O

hm)




MOS CapacitancesMOS CapacitancesDynamic BehaviorDynamic Behavior


Dynamic Behavior of MOS TransistorDynamic Behavior of MOS Transistor

DS

G

B

CGDCGS

CSB CDBCGB


The Gate CapacitanceThe Gate Capacitance

tox

n+ n+

Cross section

L

Gate oxide

xd xd

L d

Polysilicon gate

Top view

Gate-bulkoverlap

Source

n+

Drain

n+W


Gate CapacitanceGate Capacitance

S D

G

CGC

S D

G

CGC

S D

G

CGC

Cut-off Resistive Saturation

Most important regions in digital design: saturation and cut-off


Gate CapacitanceGate Capacitance

WLCox

WLCox

2

2WLCox

3

CGC

CGCS

VDS /(VGS-VT)

CGCD

0 1

CGC

CGCS = CGCDCGC B

WLCox

WLCox

2

VGS

Capacitance as a function of VGS(with VDS = 0)

Capacitance as a function of the degree of saturation


Diffusion CapacitanceDiffusion Capacitance

Bottom

Side wall

Side wallChannel

SourceND

Channel-stop implant NA1

SubstrateNA

W

xj

LS


Junction CapacitanceJunction Capacitance


Linearizing the Junction CapacitanceLinearizing the Junction Capacitance

Replace non-linear capacitance bylarge-signal equivalent linear capacitance

which displaces equal charge over voltage swing of interest


MOS Capacitances in 0.25/0.5 MOS Capacitances in 0.25/0.5 m m CMOS processesCMOS processes

0.5um

AMI/C5

Cox

fF/m2

C0

fF/m

Cj

fF/m2

mj b

V

Cjsw

fF/m

mjsw bsw

V

NMOS 2.5 0.20 0.44 0.34 0.90 0.28 0.35 0.89

PMOS 2.4 0.28 0.73 0.5 0.91 0.33 0.32 0.90


The Sub-Micron MOS TransistorThe Sub-Micron MOS Transistor

Threshold Variations Subthreshold Conduction Parasitic Resistances


Threshold VariationsThreshold Variations

VT

L

Long-channel threshold Low VDS threshold

Threshold as a function of the length (for low VDS)

Drain-induced barrier lowering (for low L)

VDS

VT


Sub-Threshold ConductionSub-Threshold Conduction

0 0.5 1 1.5 2 2.510

-12

10-10

10-8

10-6

10-4

10-2

VGS (V)

I D (

A)

VT

Linear

Exponential

Quadratic

Typical values for S:60 .. 100 mV/decade

The Slope Factor

ox

DnkT

qV

D C

CneII

GS

1 ,~ 0

S is VGS for ID2/ID1 =10


Sub-Threshold Sub-Threshold IIDD vs vs VVGSGS

VDS from 0 to 0.5V

kT

qV

nkT

qV

D

DSGS

eeII 10


Sub-Threshold Sub-Threshold IIDD vs vs VVDSDS

DSkT

qV

nkT

qV

D VeeIIDSGS

110

VGS from 0 to 0.3V


Summary of MOSFET Operating Summary of MOSFET Operating RegionsRegions

Strong Inversion VGS > VT

Linear (Resistive) VDS < VDSAT

Saturated (Constant Current) VDS VDSAT

Weak Inversion (Sub-Threshold) VGS VT

Exponential in VGS with linear VDS dependence


Parasitic ResistancesParasitic Resistances

W

LD

Drain

Draincontact

Polysilicon gate

DS

G

RS RD

VGS,eff


Latch-upLatch-up


Future PerspectivesFuture Perspectives

25 nm FINFET MOS transistor


Problems HW3Problems HW31. Rabaey Chap. 3 on-line problems: 2, 3(do not do the spice simulation), 6,

9(L=0.5um)

2. Consider an inverter built with 1/0.5 (nmos W/L) and 2/0.5 (pmos) transistors. Draw a sue schematic for the inverter driving a 10fF load capacitor (other terminal is grounded). Using your model for the AMI FET transistors, determine the peak current flowing into the FET after both an abrupt rising and falling edge on the inverter input, given a supply voltage of 3.3 Volts and using the Mosis extracted parameters from the MOSIS or the class website. Simulate these transitions using spice from the Sue schematic.

3. Complete the Max layout of the full adder cells and build a schematic in sue for each cell and for an 8-bit ripple carry adder. Be sure to use the same transistor sizes in the schematic as you had in your layout. Simulate the adder for the following transition: a=0->1, b=255 Plot the sum and carry outputs and estimate the total carry chain delay and delay per stage.

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© Digital Integrated Circuits 2nd Devices VLSI Devices Intuitive understanding of device operation Fundamental analytic models Manual Models Spice