Lecture 2 - MOS Devices SPICE Fabrication

8/2/2019 Lecture 2 - MOS Devices SPICE Fabrication

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Lecture 2 - 1Introduction to Digital Integrated Circuit DesignMOS Theory, SPICE, Fabrication

Lecture 2

Basic MOS Theory, SPICE Simulation,CMOS Fabrication

Konstantinos MasselosDepartment of Electrical & Electronic Engineering

Imperial College London

URL: http://cas.ee.ic.ac.uk/~kostas

E-mail: [email protected]


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Based on slides/material by

P. Cheung http://www.ee.ic.ac.uk/pcheung/teaching/ee4_asic/index.html

J. Rabaey http://bwrc.eecs.berkeley.edu/Classes/IcBook/instructors.html

Digital Integrated Circuits: A Design Perspective, Prentice Hall

D. Harris http://www.cmosvlsi.com/coursematerials.html

Weste and Harris, CMOS VLSI Design: A Circuits and SystemsPerspective, Addison Wesley


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Recommended Reading

J. Rabaey et. al. Digital Integrated Circuits: A Design Perspective:Chapter 2 (2.1 2.3), Chapter 3 (3.3)

Weste and Harris, CMOS VLSI Design: A Circuits and SystemsPerspective: Chapter 2, Chapter 3 (3.2), Chapter 5.


4/70Lecture 2 - 4Introduction to Digital Integrated Circuit DesignMOS Theory, SPICE, Fabrication

Outline

MOS transistors

SPICE simulation

CMOS fabrication process

Layout rules


5/70Lecture 2 - 5Introduction to Digital Integrated Circuit DesignMOS Theory, SPICE, Fabrication

MOS Transistor

Shown here is the cross-section of an n-channel enhancement transistor: Substrate is moderately doped with p-type material. Substrate in digital

circuit is usually connected to VGnd (ground).

The source and drain regions are heavily doped with n-type materialthrough diffusion. These are often referred to as the diffusion regions.


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Conduction Characteristics of MOS Transistors(for fixed Vds)

MOS transistors are majority-carrier devices. For n-channel transistors, the majority carriers are electrons conducted

through a channel.

A positive gate voltage (w.r.t. substrate) enhances the number ofcarriers in the channel, and increases conduction.

Threshold voltage Vtn denotes the gate-to-source voltage above whichconduction occurs.

For enhancement mode devices, Vtn is positive; for depletion modedevices, Vtn is negative.

p-channel devices are similar to n-channel devices, except that all

voltages and currents are in opposite polarity.


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Cross-Section of CMOS Technology


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MOS transistors - Types and Symbols

D

S

G

D

S

G

G

S

D

NMOS Enhancement NMOS Depletion

PMOS Enhancement

D

S

G B

NMOS withBulk Contact


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Threshold Voltage: Concept

n+n+

p-substrate

DSG

B

VGS

+

-

Depletion

Region

n-channel


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MOS transistor (1)

Between the diffusion regions is the gate area form from a layer of polycrystalinesilicon (known as polysilicon). This is separated from the substrate by a layer ofthin oxide (made of silicon dioxide). Polysilicon is reasonable conductor and

form the gate electrode. Underneath the thin oxide and between the n+ regions is the channel. Thechannel is conducting when a suitable electric field is applied to the gate.

Due to geometric symmetry, there are no distinctions between the source and

drain regions. However, we usually refer the terminal with more positive voltagethe drain (for n-type) and less positive voltage the source. For a zero gate bias and a positive VDS, no current flows between the drain and

source because of the two reverse biased diodes shown in the diagram. Thedrain and source are therefore isolated from each other.

Assuming that the substrate is always at the most negative supply voltage, thesetwo diode should never become forward bias under normal operation.


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MOS transistor (2)

When a positive voltage is applied to the gate, an electric field is producedacross the substrate which attracts electrons toward the gate. Eventually, thearea under the gate changes from p-type to n-type, providing a conduction pathbetween the source and drain.

The gate-source voltage VGS when a channel starts to form under that gate iscalled the threshold voltage VT.

The surface underneath the gate under this condition is said to be inverted. Thesurface is known as the inversion layer.

As larger bias is applied to the gate the inversion layer becomes thicker An other p-n junction exists between the inversion layer and the substrate. This

diode junction is field induced. Contrast this with the p-n junction between thesource (or drain) and the substrate, which is created by a metallurgical process.


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The Threshold Voltage

0


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Current-Voltage Relations

n+n+

p-substrate

DS G

B

VGS

xL

V(x) +

VDS

ID

MOS transistor and its bias conditions


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Current-Voltage Relations


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Transistor in Saturation

n+n+

S

G

VG S

D

VDS > VGS - VT

VG S - VT+-


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MOS transistor (3)

As a voltage is applied between the source and drain, the inversion layerbecomes thinner at the drain terminal due to interaction between VG and VD.

If VDS < VGS - VT, then the drain current Id is a function of both VGS and VDS.

Furthermore, for a given VDS, ID increases linearly with (VGS - VT). The transistoris said to be operating in its linear or resistive region. If VDS > VGS - VT, then VGS < VT and no inversion layer can exist at the drain

terminal. The channel is said to be 'pinched-off'. The transistor is operating inthe saturation region, where the drain current is dependent on V

GS

and is almostindependent of VDS.


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I-V Relation


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A model for manual analysis


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Dynamic Behavior of MOS Transistor

DS

G

B

CGDCGS

CSB CDBCGB


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The Gate Capacitance


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Average Gate Capacitance

Different distributions of gate capacitance for varyingoperating conditions

Most important regions in digital design: saturation and cut-off


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Issues concerning Sub-Micron MOS Transistors

Threshold Variations

Parasitic Resistances

Velocity Saturation

Mobility Degradation


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Threshold Variations

VT

L

Long-channel threshold Low VDSthreshold

Threshold as a function ofthe length (for low VDS)

Drain-induced barrier lowering(for low L)

P i i R i


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Parasitic Resistances

V l it S t ti (1)


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Velocity Saturation (1)

V l it S t ti (2)


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Velocity Saturation (2)

VDS (V)

ID(mA)

LinearDependenc

e

VGS = 5

VGS = 4

VGS = 3

VGS = 2VGS = 1

0.0 1.0 2.0 3.0 4.0 5.0

0.5

1.0

1.5

(a) ID as a function of VDS (b) ID as a function of VGS(for VDS = 5 V).

0.0 1.0 2.0 3.0VGS (V)

0

0.5

ID(mA)

Linear Dependence on VGS

S b Threshold Cond ction


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Sub-Threshold Conduction

0.0 1.0 2.0 3.0VGS (V)

1012

1010

108

106

104

102

ln(ID)(A)

Subthreshold exponential region

Linear region

VT

Latch up problem (1)


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Latch-up problem (1)

The p+ region of the p-transistor, the n-well and the p- substrate form aparasitic pnp transistor T1.

The n- well, the p- substrate and the p+ source of the n-transistor forms

another parasitic npn transistor T2. There exists two resistors Rw and Rs due to the resistive drop in the well

area and the substrate area.

Latch up problem (2)


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Latch-up problem (2)

T1 and T2 form a thyristor circuit. If Rw and/or Rs are not 0, and for some

reason (power-up, current spike etc), T1or T2 are forced to conduct, Vdd will beshorted to Gnd through the smallresistances and the transistors.

Once the circuit is 'fired', both transistors

will remain conducting due to the voltagedrop across Rw and Rs. The only way toget out of this mode is to turn the poweroff.

This condition is known as latch-up. To avoid latch-up, substrate-taps (tied to

Gnd) and well-taps (tied to Vdd) areinserted as frequently as possible. This

has the effect of shorting out Rw and Rs.

Outline


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Outline

MOS transistors

SPICE simulation


Layout rules

What is SPICE Circuit Simulator?


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What is SPICE Circuit Simulator?

SPICE is a widely-used circuit-level simulator, originally from Berkeley. SPICE uses numerical techniques to solve nodal analysis of circuit. It

supports the following: Textual input to specify circuit & simulation commands Text or graphical output format for simulation results

You can use SPICE to specify these circuit components: Resistors, Capacitors, Inductors

Independent sources (V, I), Dependent sources (V, I) Transmission lines Active devices (diodes, BJTs, JFETS, MOSFETS)

You can use SPICE to perform the following types circuit analysis: non-linear d.c. non-linear transient linear a.c.

Noise & temperature

SPICE MODELS


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SPICE MODELS

Level 1: Long Channel Equations - Very Simple

Level 2: Physical Model - Includes VelocitySaturation and Threshold Variations

Level 3: Semi-Emperical - Based on curve fittingto measured devices

Level 4 (BSIM): Emperical - Simple and Popular

MAIN MOS SPICE PARAMETERS


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MAIN MOS SPICE PARAMETERS

SPICE Parameters for Parasitics


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SPICE Parameters for Parasitics

SPICE Transistors Parameters


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SPICE Transistors Parameters

Fitting level-1 model for manual analysis


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Fitting level 1 model for manual analysis

VGS = 5 V

VDS = 5 V VDS

ID

Long-channel

approximation

Short-channelI-Vcurve

Region of

matching

Select kand such that best matching is obtained @ Vgs= Vds= VDD

Technology Evolution


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Technology Evolution

VDD decreases Save dynamic power Protect thin gate oxides and short channels

No point in high value because of velocity sat. Vt must decrease to

maintain device performance

But this causes exponentialincrease in OFF leakage Major future challenge

Outline


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Outline

MOS transistors

SPICE simulation


Layout rules

CMOS Fabrication


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CMOS transistors are fabricated on silicon wafer

Lithography process similar to printing press

On each step, different materials are deposited or etched

Easiest to understand by viewing both top and cross-section of wafer ina simplified manufacturing process

Inverter Cross-section


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n+

p substrate

p+

n well

A

YGND

VDD

n+ p+

SiO2

n+ diffusion

p+ diffusion

polysiliconmetal1

nMOS transistor pMOS transistor

Typically use p-type substrate for nMOS transistors

Requires n-well for body of pMOS transistors Qp

Qn

Vi

Vo

VDD

Well and Substrate Taps


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p

Substrate must be tied to GND and n-well to VDD

Metal to lightly-doped semiconductor forms poor connection calledShottky Diode

Use heavily doped well and substrate contacts / taps

n+

p substrate

p+

n well

A

YGND V

DD

n+p+

substrate tap well tap

n+ p+

Inverter Mask Set


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Transistors and wires are defined by masks Cross-section taken along dashed line

GND VDD

Y

A

substrate tap well tap

nMOS transistor pMOS transistor

Detailed Mask Views


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Six masks n-well Polysilicon n+ diffusion p+ diffusion Contact Metal

Metal

Polysilicon

Contact

n+ Diffusion

p+ Diffusion

n well

Fabrication Steps


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Start with blank wafer Build inverter from the bottom up First step will be to form the n-well

Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2

p substrate

Oxidation


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Grow SiO2 on top of Si wafer 900 1200 C with H2O or O2 in oxidation furnace

p substrate

SiO2

Photoresist


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Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light

p substrate

SiO2

Photoresist

Lithography


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Expose photoresist through n-well mask Strip off exposed photoresist

p substrate

SiO2

Photoresist

Etch


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Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!!

Only attacks oxide where resist has been exposed

p substrate

SiO2Photoresist

Strip Photoresist


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Strip off remaining photoresist Use mixture of acids called piranah etch

Necessary so resist doesnt melt in next step

p substrate

SiO2

n-well


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n-well is formed with diffusion or ion implantation Diffusion

Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si

Ion Implantation Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si

n well

SiO2

Strip Oxide


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Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps

p substraten well

Polysilicon


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Deposit very thin layer of gate oxide < 20 (6-7 atomic layers)

Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon Heavily doped to be good conductor

Thin gate oxidePolysilicon

p substraten well

Polysilicon Patterning


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Use same lithography process to pattern polysilicon

Polysilicon

p substrate

Thin gate oxidePolysilicon

n well

Self-Aligned Process


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Use oxide and masking to expose where n+ dopants should be diffusedor implanted N-diffusion forms nMOS source, drain, and n-well contact

p substrate

n well

N-diffusion


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Pattern oxide and form n+ regions Self-aligned processwhere gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesnt

melt during later processing

p substraten well

n+ Diffusion

N-diffusion cont.


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Historically dopants were diffused Usually ion implantation today But regions are still called diffusion

n wellp substrate

n+n+ n+

N-diffusion cont.


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Strip off oxide to complete patterning step

n wellp substrate

n+n+ n+

P-diffusion


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Similar set of steps form p+ diffusion regions for pMOS source and drainand substrate contact

p+ Diffusion

p substraten well

n+n+ n+p+p+p+

Contacts


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Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed

p substrate

Thick field oxide

n well

n+n+ n+p+p+p+

Contact

Metalization


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Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires

p substrate

Metal

Thick field oxide

n well

n+n+ n+p+p+p+

Metal

Outline


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MOS transistors

SPICE simulation


Layout rules

Layout


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Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence

speed, cost, and power) Feature size f= distance between source and drain

Set by minimum width of polysilicon

Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules

Express rules in terms of = f/2 E.g. = 0.3 m in 0.6 m process

Design Rules


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Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width

scalable design rules: lambda parameter absolute dimensions (micron rules)

CMOS Process Layers


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Layer

PolysiliconMetal1

Metal2

Contact To PolyContact To Diffusion

Via

Well (p,n)Active Area (n+,p+)

Color Representation

YellowGreen

RedBlue

Magenta

BlackBlack

Black

Select (p+,n+) Green

Intra Layer Design Rules


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Metal2 4

3

10

9

0Well

Active

3

3

Polysilicon

2

2

Different PotentialSame Potential

Metal1

3

3

2

Contactor Via

Select

2

or6

2Hole

Transistor Layout


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1

2

5

3

Tran

sistor

Vias and Contacts


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1

2

1

Via

Metal toPoly ContactMetal to

Active Contact

1

2

5

4

3 2

2

Select Layer


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1

3 3

2

2

2

WellSubstrate

Select3

5

CMOS Inverter Layout


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A A

np-substrate Field

Oxidep+

n+

In

Out

GND VDD

(a) Layout

(b) Cross-Section along A-A

A A

Summary


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MOS transistor: majority carrier device building block of integratedcircuits

SPICE: popular circuit level simulator that applies nodal analysis ofcircuit

CMOS transistors are fabricated on silicon wafer

Lithography process Different materials are deposited or etched in each step

Layout rules: contract between IC designer and process engineer Guidelines for constructing process masks

Documents

Lecture 2 - MOS Devices SPICE Fabrication