© 2010 Altera Corporation—Public Enabling High System Performance with Advanced Silicon and Memory IP 2010 Technology Roadshow

© 2010 Altera Corporation—Public

Enabling High System Performance with Advanced Silicon and Memory IP

2010 Technology Roadshow


ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Agenda Dynamic RAM and Static RAM Altera external memory solutions: UniPHY Altera external memory solutions: High

Performance Controller II Design flow for DDR and QDR external

Memory controller Demo Summary

2



Static Ram V.S. Dynamic Ram Static RAM (SRAM) is a type of

semi-conductor memory Pros:

Retains all information as long as power is maintained

Reads stored data at a faster rate since they accept all address bits at the same time (DRAM accepts high to low)

Cons: Construction includes four transistors

and two cross-coupled inverters and two additional access transistors that serve to control the access to a storage cell during read and write operations

A six-transistor

CMOS SRAM cell

3



Static Ram V.S. Dynamic Ram Dynamic RAM (DRAM) stores

each bit of memory in a separate capacitor

Pros: Only one transistor and capacitor

are required per bit Allows for RAM to reach very high

density Lowest cost per bit

Cons: Capacitors leak electrons Information is lost unless charge is

refreshed periodically The latency is uncertain

1-70RTZ3

4



Type of external RAM DDR/DDR2/DDR3 SDRAM

Very low cost external RAM Higher latency : multiplexed address bus Lower efficiency: need refresh periodically Need Complex Controller

RLDRAM I/II Reduced latency DRAM Partitioned into 8 banks to reduce parasitic capacitance of address and

data lines Non-multiplexed address to save bus cycles

QRD/QRD II/QRDII+ SRAM SRAM based: density is not high Low latency: 1 clock cycle; True dual port: independent read/write bus running with DDR clock Simple controller

5



Market-Specific Requirements

Application 40G/100G Basestations Video processing Disk array, servers. accelerators

Low power / portable devices

Need High performance Low latency Increased efficiency

More functions Low power

Memory Standard

DDR3, RLDRAM II, QDR II/+

DDR2/3 Multi-port efficiency, DDR3 @ 533 MHz

RDIMM, ONFI, Flash, QDR II/+

LPDDR, mobile DDR

Different Solutions Fit Market Applications

Over 70% of FPGA applications have some form of external memory

Broadcast MilitaryComputer/Storage

WirelessWireline

6



Dynamic Ram dominate the market Highest density/Cheapest memory

solution Widely used

PC and Server applications Also widely used in many market segments

Wireless: baseband processing; Remote Radio Head;

Wireline: packet processing; Traffic management;

Video processing; Security applications

7



External Memory Roadmap

Logic Density

800-MHzDDR3

533-MHz DDR3DDR1/2/3, QDR II/+,

RLDRAM II

800-MHz DDR3DDR2/3, QDR II/+, RLDRAM

II

Per

form

ance

400-MHz DDR3DDR1/2/3, QDR II/+

200-MHz DDR2DDR1/2

8



External RAM Design Challenge Board design:

Clock Speeds reaching 800MHz Parallel buses reaching the speeds of serial

technology: 1.6Gbps Crosstalk, impedance, EMI, and jitter issues Noise susceptibility

Controller Design and verification Tighter timing margins require calibration and

bus training for DRAM, Controller and Analyzer capture

Debug is difficult High data rate Memory interface is Double data rate; and

not easy understand with additional control

9



Altera help you with Complete Memory Solutions

Dedicated circuits to enable higher performance

Best in class signal integrity

Advanced FPGA ArchitectureAdvanced FPGA Architecture

Support for common memory standards (DDR 1/2/3, QDR, RLDRAM)

Low latency high performance Included in the Free IP Base Suite

External Memory IP MegaCoresExternal Memory IP MegaCores

Automatic Generated Constraints System Level Timing Analysis Spice and IBIS Simulation Models

Software SupportSoftware Support

Device Handbook, Application Note

Support CollateralSupport Collateral

Reference designs Board Design Guidelines

Development Kits &Hardware Reference PlatformsDevelopment Kits &Hardware Reference Platforms

10



External Memory IP MegaCore

QDRII/QDRII+/RLDRAMIII/DDR2/3 High Performance Controller II (HPMCII) HPMCII : Higher bus efficiency with advanced bank management UniPHY: Lower latency

Multi-Port Front End is available as a reference design Intelligent multi-class arbitration Effectively share bandwidth between several masters

MPFE(Ref Design)

MemoryController(HPMCII)

Memory PHY

(UniPHY)

Memory IP

Multi-Port Controller

External MemoryA

valo

n M

M

Ava

lon

MM AF

I

QDR II, QDR II+, RLDRAM II/ III, DDR2/3

11


UNIPHY Architecture



External Memory – What’s New

Result of Re-architected Memory PHY and Controller

HPMC II = 2x the controller efficiency UniPHY = ½ the ALTMEMPHY latency

Memory Type Controller UniPHY

DDR 2/3 QII 9.1 QII 10.0

QDR II/II+ QII 9.1(1) QII 9.1

RLDRAM II QII 9.1(1) QII 9.1

(1) Controller designed to support UniPHY. This is not HPMCII

13



Altera Memory PHY Solutions

Feature UniPHY ALTMEMPHY

Available as a MegaCore Support for DDR2/3 Support for QDR II/II+ and RLDRAM II X

PLL/DLL sharing X

Smart calibration algorithms X

Latency 0.5 1.0

UniPHY Provides Higher Flexibility With Half the Latency

14



PHY Architectures (UniPHY and ALTMEMPHY)

DLL

PLL

Address/cmd path

Read Path

Write path

Mimic path

Re-config

I/O Structure

Clock gen

DSQ I/O

block

DQ I/O

block

Auto Cal

I/O

block

Altmemphy

Me

mo

ry

Memory IP

Controller

Stratix III

Address/cmd Path

Read Path

Write Path

Re-configI/O Structure

Clock Gen

DQSPath

DQ I/O

Block

DQ I/O

CalibrationSequencer

I/O BlockI/O

Me

mo

ry

MemoryController

ALTMEMPHY

PLL

DLL

Mimic Path

Me

mo

ryM

em

ory

Hard read/write path Guaranteed timing closure at 800 MHz Soft I/O grouping and sequencer Flexibility for supporting multiple configurations Re-architected UniPHY Lower latency, shared resources (PLL, DLL) for multiple

interfaces

SoftHard

DLL

PLL

Address/cmd path

Read Path

Write path

Mimic path

Re-

configI/O Structure

Clock gen

DSQ I/O

block

DQ I/O

block

Auto Cal

I/O

block

Altmemphy

Memory IP

Controller

DLL

Address/cmd Path

Read Path

Write Path

DQSPath

DQ I/O

FIFO

DQ I/O

CalibrationSequencer

I/O BlockI/O

UniPHY

MemoryController

PLL

Re-config

Clock Gen

I/O Structure

UniPHY

15



UniPHY Benefits Universal PHY applicable to all families

Seamless replacement for ALTMEMPHY at PHY interface (AFI) UniPHYavailable starting QII 9.1 for QDR, RLDRAM, QII 10.0 for DDRx

Enhanced Features Lower read latency ~ half that of ALTMEMPHY PLL/DLL instantiated at top level to support sharing across multiple

interfaces More DIMM and Rank support Auto calibration

Improve ease-of-use UniPHYavailable as cleartext(unencrypted) Niosbased calibration sequencer for easier debug Convenient application of timing and pin constraints Verilogtestbenchesfor understanding core Flexible timing models –provide transparency and higher accuracy

16



De-skew Calibration

Utilizes Stratix III/IV FPGA dynamic trace compensation (programmable delay chains) to de-skew DQ data bus

Provides extra margin at capture stage Track VT to maintain maximum data valid window (DVW)

17



PHY Calibration

18



PLL/DLL Sharing Building multiple memory interfaces can put a strain on

scarce resources (e.g. PLL, DLL, global clocks)

UniPHY supports convenient sharing of PLL & DLL PLL & DLL instantiated at top-level of PHY & Controller Can choose “PLL Master” or “PLL Slave” mode Interfaces must use same configuration

PLL Master: PLL Slave:

19



UniPHY: Industry-leading Latency

Latency * (measured in full rate clock cycles)

ProtocolHalf/Full

RateController

(Addr/Cmd)

PHY

(Addr/Cmd)

Memory

(Max Read)

PHY

(Read Return)

Round TripRound Trip

(less memory)

RLDRAM II

(x36)

Full 2 † 2 8 5 17 9

Half 4 † 3 8 7 2214

(7 HR)

QDR II+

(x18)

Full 1 2 2.5 5.5 11 8.5

Half 2 4 2.5 7.5 1613.5

(7 HR)

DDR 2/3(QII 10.0 estimate)

Full 5 † 2DDR2: 5DDR3: 11

5DDR2: 17 DDR3: 23

12

Half 10 † 3DDR2: 5DDR3: 11

7DDR2: 25 DDR3: 31

20(10 HR)

ALTMEMPHY(~DDR2)

Full 5 † 3.5 DDR2: 5 10 DDR2: 23.5 18.5

Half 10 † 8 DDR2: 5 18 DDR2: 4136

(18 HR)

† Best case shown; latency may be higher due to protocol requirements (tRC, bus turnaround, open/precharge)

20



Sequencer (Calibration) Architecture Built as an SOPC system

with AVALON components

Processor + H/W accelerators

NIOS performs the algorithmic side of calibration

Faster development & better debug

NIOS II

SCCMgr

RWMgr

PHYMgr

PLLMgr

RAM(SW)

DebugInterface

to I/OsAFI

interfacePHY

paramsPLL

control

to/fromdebug module

AVALON Bus

21



IP That Calibrates, De-Skews, and Tracks to Eliminate PVT Variation Calibration—removes process variation from FPGA and memory

Sweep all resync phases for all DQ pins Build map: pin-by-pin basis Select best resync phase

DQ

DQS

Known training pattern

Sweptresynchronization

phase

Comparator

Reconfigurable PLL

Capture

Resynch

0 15 30 45 60 … … … … 315 330 345 360dq0dq1dq2dq3dq4dq5dq6dq7

Valid data window

Ideal resync phase: maximum setup and hold margin

Set phase

Read DQ

Compare

Pass/Fail

Record result

(Phase set dependant upon frequency)

22



VT Tracking and Compensation Create one additional reference map (mimic path) Periodically keep sweeping this mimic path If mimic path map has moved (compared to reference), adjust

resynch for DQ read path 0 15 30 45 60 … … … … 315 330 345 360dq0dq1dq2dq3dq4dq5dq6dq7

Mimic ref

Measure

Adjust resynch if mimic path reference is moving

Mem

ory

PLL

Mimic path

Re-config

I/O Structure

Clock gen Auto Cal

PLLRe-config

I/O Structure

Clock gen Auto cal

Mem

ory

Mimic path

Static timing analysis – small safe window

Dynamic tracking – large window

23



Notes on Reconfigurable PLL Used during calibration stage and adjusted for

voltage and temperature tracking

No interruption of external memory interface operation when PLL reconfigured

One PLL drives all clock signals required for interface Stratix III/IV PLLs have 7 to 10 outputs DDR uses 3 to 7 clocks; QDR uses 4 to 5 clocks Only one PLL required per interface

Two required for >200 MHz in Stratix II FPGA

24



Calibrated Dynamic OCT available in Stratix and Arria FPGA Cyclone has on chip serial termination Provides proper line termination and power savings Mixed termination values in same bank Dynamically turn ON and OFF parallel termination

Saves significant power 1.6 watts over 72-bit DDR2 bus

Properly terminates line for bidirectional busses Reduces costs

Eases routing congestion Puts the memories closer Saves external component cost

Write

FPGA Memory

Read

Dynamic OCT

1. Stratix IV FPGAs also support on-chip differential termination (covered earlier)

2. Final values and tolerances pending characterization

Function Serial - Rs Parallel - Rt Dynamic Calibratation

Value2 25 / 50 default (20 to 60 w/ Ext R)

50Turn Rt off during

writesRs and Rt

Comment All banks +/- 5% All banks +/- 5% Saves power (Also off during bus idle)

PVT compensation (requires external

resistor)

Single-ended termination 1

25



Programmable Control Per I/O Controllable slew rate

Four settings to match desired I/O standard, and control noise and overshoot

Programmable output drive strength Match desired I/O standard

Adjustable output buffer delay Separate from main I/O delay Deliberately add for skew to shift adjacent

edges and reduce total number of simultaneous switch outputs (SSO)

Independently control rise / fall times (i.e. adjust duty cycle)

I/O standard mA mA mA mA mA mA

SSTL18 Class I 4 6 8 10 12

SSTL18 Class II 8 16

Settings depend on standard; SSTL18 example shown

Delay parameter Setting UnitsNo delay 0 ps

50 ps100 ps150 ps50 ps100 ps150 ps50 ps100 ps150 ps

Rising edge delay

Falling edge delay

Both rising and falling edge delay

26



Variable Input and Output Delay for De-Skew

Path Run-time configurable

Step size

Set at compile Step size

Output buffer

Step size Total

Input 1,100 ps 50 ps 2,800 ps 400 ps 3,900 ps

Output 1,050 ps 50 ps 150 ps 50 ps 1,200 ps

dqs0 15 30 45 60 75 90 105 120 135 150 165 180

dq0dq1dq2dq3dq4dq5dq6dq7

dqs0 15 30 45 60 75 90 105 120 135 150 165 180


dqs0 15 30 45 60 75 90 105 120 135 150 165 180


dqs0 15 30 45 60 75 90 105 120 135 150 165 180


Example automatic de-skew algorithm in DDR3 IP for centering data around DQS

Resolution and absolute value pending characterization

Set at compile time

Hold- time requirements400ps stepping , 7 settings0.4ps ~ 2.8ns

D Q T9 T10

T2T3T1Q D

Read calibration50ps stepping , 16 settingsIntrinsic delay ~ 750ps

Fine tuning of DQ path delay50ps stepping , 8 settingsIntrinsic delay ~ 350ps

Write calibration50ps stepping , 16 settingsIntrinsic delay ~ 750ps

Reduce SSN and fine tune for write leveling50ps stepping , 7 settingsIntrinsic delay ~ 300ps

Hold- time requirements400ps stepping , 7 settings0.4ps ~ 2.8ns

D Q T9 T10

T2T3T1Q D





D Q T9 T10

T2T3T1Q D





27



Read Leveling Built Into I/O Bank for DDR3

DLLCLK

DQS

DQ

Next DQS group eg another x8

DQS group eg x8

DLLCLK DLLCLK

DQS

DQ

Next DQS group eg another x8

DQS group eg x8

Resync ClkMax phase delay

Mid phase delay

Represents resync-clock phase shifts—not I/O delays

•Not in the datapath

•PVT-compensated phase shifts

•Each DQS group has its own phase shift

•All output data across the bus can be aligned

•Individual DQ signals within a DQS group can be aligned with I/O delay elements

Fastest data back

Most delay required

Slowest data back

Least delay required

Min phase delay

Fly-by topology used for

clk

28



Write Leveling Built Into I/O Bank for DDR3

DQS groups launched at separate times to coincide with clock arriving at devices on the DIMM

8

8

Write clk

DQS group 1

DQS group 0

Phase delay 0

Phase delay 1

29



Stratix IV FPGA DDR3 at 1,067 Mbps DDR3 across PVT

available for 1,067 Mbps

DDR3 speeds in lab now at 620 MHz (1,240 Gbps) Demonstration of

capability and margin, not a commitment to productize

Stratix V will support DDR3 at 1,600 Mbps Stratix IV FPGA DDR3 memory interface eye at

1,067 Mbps (533 MHz)

30


HPMCII Architecture

High Performance Memory Controller II (HPMCII)



External Memory IP MegaCore

QDRII/QDRII+/RLDRAMIII/DDR2/3 High Performance Controller II (HPMCII) HPMCII : Higher bus efficiency with advanced bank management UniPHY: Lower latency

Multi-Port Front End is available as a reference design Intelligent multi-class arbitration Effectively share bandwidth between several masters

MPFE(Ref Design)

MemoryController(HPMCII)

Memory PHY

(UniPHY)

Memory IP


External MemoryA

valo

n M

M

Ava

lon

MM AF

I

QDR II, QDR II+, RLDRAM II/ III, DDR2/3

32



Altera Memory Controller Solutions

New Features Enable Better Controller Efficiency and Performance

Features HP Memory Controller II

HP Memory Controller

ECC with sub-word write

Power management

5-cycle controller latency (6 w/ ECC)

Support 800-MHz DDR3 memory X

Advanced bank management w/ command look-ahead X

Flexible system interface X

Run-time programmable X

Multi-cast writes X

33



RLDRAM-II & QDR-II/II+ Controllers w/ UniPHY

Feature Description

Performance Half Rate - Up to 400MHz

Full Rate – Up to 300MHz

Device Interfaces x9, x18, x36 devices

Burst Lengths Full Rate: 2, 4, & 8 / Half Rate 4 & 8

Other Features Common I/O (CIO) Non-multiplexed addressing Avalon® Memory-Mapped (Avalon-MM) local interface

Feature Description

Performance Half Rate - Up to 400MHz fokr QDR II+ and 350 MHz for QDR II

Full Rate – Up to 300MHz

Device Interfaces x9, x18, x36 devices

Burst Lengths Full Rate: 2 & 4 / Half Rate: 4

Other Features Avalon® Memory-Mapped (Avalon-MM) local interface

RLDRAM-II Controller Megacore

QDR-II/II+ Controller Megacore

34



Memory Controller Technology Roadmap

Per

form

ance

Memory Controller Architecture

HPMC I Next-Generation

Adv Bank Mgt

HPMC II

In-Order Cmd, R/W

MPFE Ref Design

DDR1/2/3

Run-time Reconfig

Multi-cast

Data Reordering

1T/2T Addr/Cmd

Priority Bypass

DDR12/3 DDR2/3

LPDDR/2

Soft IP

Soft IP

Hard/Soft IP

Higher Bandwidth


35



Memory Interface Enhancements

Memory Fmax

400 MHz

Auto calibration

0 MHz

533 MHz

Deskew with 50ps resolution

800 MHz Hard Read/Write paths High resolution VT compensated delays Duty cycle correction Complete path tracking (memory + board + FPGA) Advanced calibration algorithms On-die, on-package decoupling

Advanced Silicon and IP FeaturesEnabling Higher Performance!

36



Stratix V Memory Stratix V Memory Performance

Available on All Sides - Over PVT Conditions

Memory Standard fMAX (MHz)

DDR3 SDRAM 800

DDR2 SDRAM 533

RLDRAM II 533

QDR II+ SRAM 550

QDR II SRAM 350

DDR2+ SRAM 550

LPDDR2 SDRAM 533

37



Altera High Performance Memory Controller II DDR1/2/3 SDRAM High Performance Memory Controller

II (HPMC II) 2x the controller efficiency More features, increased throughput

Features HP Memory Controller II

HP Memory Controller

MegaCore in QII 9.1

ECC with sub-word write

Power Management

Advanced bank management w/ command look-ahead

Flexible system interface

Run time programmable

Multicast writes

38



Architecture Block DiagramHigh Performance Memory Controller II

Clock and reset outputs

Memory command engine

Avalo

n-MM

slave

AF

I Interface

Command queue

Command issuing state machine

Bank management

logic

Timer logic

Write data FIFO

CSR portAvalon-MM slave

Low power, refresh controls

Clock & reset

Address and

command decode

ALTMEMPHY

AF

I Interface

DD

Rx S

DR

AM

In

terface

CS

R p

ortA

valon-M

M slave

PLL

Clock and

reset inputs

Advanced Bank Management

Flexible System Interface

Run Time Programmability & Power Management

39




Look-ahead bank management Efficient bank interleaving support Issue activate and precharge

commands early Use auto-precharge where possible In-order read/writes (no re-ordering)

Per access open or close page policy Read/write accesses with auto-

precharge Automatic cancellation of auto-

precharge on page hits



Avalon-M

M slave

AF

I Interface

Command queue


Bank management

logic

Timer logic

Write data FIFO



Clock & reset

Address and

command decode

ALTMEMPHY

AF

I Interface

DD

Rx S

DR

AM

Interfa

ce

CS

R port

Avalon

-MM

slave

PLL

Clo

ck and

reset inputs


40



Flexible System Interface Avalon Memory Mapped Interface

Adaptor for Native interface Avalon slave interface for access to

CSR

Burst size adaptation for efficient DRAM accesses Built-in burst adapter Combines short local transactions into

memory bursts Split long local transactions into

memory bursts

Integrated low latency half rate system interface Support an optional half system

interface speed Maintain the controller in the faster

clock domain to reduce latency



Avalon-M

M slave

AF

I Interface

Command queue


Bank management

logic

Timer logic

Write data FIFO



Clock & reset

Address and

command decode

ALTMEMPHY

AF

I Interface

DD

Rx S

DR

AM

Inte

rface

CS

R port

Avalon-M

M slave

PLL

Clock and

re

set inputs

Flexible System Interface

41



Other Advanced Features Run time programmable

Timing parameters, configurations (row, col, bank, cs) and mode regiter settings

ECC with sub-word writes 32+8 and 64+8 bits

Multicast write to mitigate effects of tRC Write to multiple-ranks, read from any open

rank

Refresh timing control Programmable periodic refresh User requested auto-refresh

Power Management User requested self-refresh Automatic entry / exit power down mode



Avalon-M

M slave

AF

I Interface

Command queue


Bank management

logic

Timer logic

Write data FIFO



Clock & reset

Address and

command decode

ALTMEMPHY

AF

I Interface

DD

Rx S

DR

AM

Interface

CS

R port

Avalon-M

M slave

PLL

Clock and

reset inputs

Run Time Programmability & Power Management

42



Multi-Port Front-End (MPFE) Reference Design

MPFE reference design Multi-class arbitration, sharing bandwidth between masters Time-critical accesses, Sharing bandwidth

Non-criticaldata slave

Time-critical data slave




Master port

Non-criticaldata slave

DDRx SDRAM Memory controller

Arbitration logic

12

3 4

?

2 1

34

Debug slave

43



Efficiency Improvement Techniques

Look-ahead Bank Management Look-ahead Auto-Precharge Transaction Combining

44



Behavior of the existing DDR HP controller Commands are fetched and processed sequentially Both the command and the DQ bus are not fully utilized

Existing DDR HP: No Look-ahead

Command Address Condition

Read Bank 0 Activate required

Read Bank 1 Precharge required


Not Efficient!!

Idle cmd bus

45



v9.1 Controller: Look-ahead Bank Management

Behavior of the v9.1 controller While waiting for tRCD (activate to read) to expire, bank management

commands are issued to banks for read/write commands in the queue When each command reaches the front of the queue, the bank should be

ready Look-ahead bank management happens during idle command cycles

Command Address Condition

Read Bank 0 Activate required



Use of idle cycles for bank-management

46



Existing DDR HP: User Controls Auto-Precharge

Behavior of the existing DDR HP controller No look-ahead auto-precharge support On every row change, the controller will close and then open the row

before the write or read burst Users can control auto-precharge on a per burst basis, but this is harder

Command Bank Row Condition

Write Bank 0 Row 0

Write Bank 1 Row 0 Activate required


Write Bank 0 Row 1 Precharge required

PCH before next WR

47



WR with AP knowing that next WR to bank 0 is to a different row

v9.1 Controller: Look-ahead Auto-Precharge

Look-ahead auto-precharge Controller decides whether to do auto-precharge read/write by looking ahead While doing write to bank 0, row 0, the controller issues an auto-precharge write Subsequent reads or writes to same bank/different row only require an activate This frees up valuable command bandwidth

User still can control auto-precharge as in existing controller

Command Bank Row Condition

Write Bank 0 Row 0



Write Bank 0 Row 1 Precharge required

Writes to the same bank, different row

48



Existing DDR HP: Multiple Single Transactions

Behavior of the existing DDR HP controller Four local requests to incrementing addresses (full-rate) Gap between writes limited by tCCD, but only one quarter of the DQ

bandwidth is actually used

Command Burst length

Bank Row Column

Write 2 Bank 0 Row 0 Col 0




Wasted bandwidth

49



Efficiency Results: Read & Write

Preliminary Efficiency Measurements, v9.0 compared to v9.1Cycling banks, 64 writes, 64 reads, BL8, half-rate , DDR3

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

1 2 3 4 5 6 7 8

Number of banks cycled

DQ

bu

s e

ffic

ien

cy

Theoretical maximum DQ efficiency

v9.1 DDRx measured DQ efficiency (with AP)

v9.1 DDRx measured DQ efficiency (without AP)

v9.0 DDR HP Measured DQ efficiciency (with AP)

DDRx is ~60% more efficient than HP controller

50


High Performance Memory Controller Design with Altera MegaCore: DDR2



DDR2 High Performance Controller Design Flow

52



DDR2 SDRAM High Performance Controller—Memory Settings

53



DDR2 SDRAM High Performance Controller—PHY Settings

54



DDR2 SDRAM High Performance Controller—Board Settings

55



DDR2 SDRAM High Performance Controller—Controller Settings

56


High Performance Memory Controller Design with Altera Megacore: QDRII



QDRII SRAM High Performance Controller—General Settings Define the external

RAM clock rate PHY interface type:

full/half rate Address/command

line clock phase IO standard Burst Length

58



QDRII SRAM High Performance Controller- Memory Parameters Define memory

interface bus width

59



QDRII SRAM High Performance Controller- Memory Timing Define external

memory timing parameter according to the external memory spec.

60



QDRII SRAM High Performance Controller- Board Timing Input the board timing

inform The software will

generate proper timing constraint based on the memory timing and board timing

61



Functional Verification : Example Design TBMemory IP (PHY & Controller): Cleartext RTL Standardized Interfaces (AFI, Avalon) Convenient timing & pin constraints

Example Design: Generated with IP Matches user parameterization Includes PHY, Controller, Driver

Example Driver (Traffic Generator): Issues parameterizable read & write traffic Synthesizable for boards and simulation

Example Testbench: Integrates memory model with example design Provides base level of functional verification

Pass Fail

User definedstages (optional)

Initialize

Individual reads/writes

Block reads/writes

Sequentialaddresses

Randomaddresses

Sequential/Random

addresses

User definedaddresses(optional)

Me

mo

ry M

od

el

ControllerPHY

Driver(Traffic

Generator)

Avalon

PHY+ Controller

Memory

AFI

Example Design

Example Testbench

Pass/Fail

62



DDR Controller Demo with Stratix III Development Board

63



Summary

Altera provides complete external Memory Controller solution to help you design fastest, robust DDR,QDR and RLDRAM memory interface

UniPHY and High Performance Controller II deliver low latency and high efficiency which will largely improve DDR 2/3 DRAM interface performance

MegaCore generator generates complete design file: RTL netlist, simulation bench, Timing constraint for easier use

For more information, Please refer to

http://www.altera.com/technology/memory/mem-index.jsp

64


Thank You!

For more information visit: www.altera.com

Documents

© 2010 Altera Corporation—Public Enabling High System Performance with Advanced Silicon and Memory IP 2010 Technology Roadshow