VHDL Coding Styles and Methodologies

Second Edition

VHDL Coding Styles and Methodologies

Second Edition

Ben Cohen

KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

eBook ISBN: 0-306-47681-9Print ISBN: 0-7923-8474-1

©2002 Kluwer Academic PublishersNew York, Boston, Dordrecht, London, Moscow

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CONTENTS

1.0 VHDL OVERVIEW AND CONCEPTS

1.11.21.31.41.5

WHAT IS VHDLLEVEL OF DESCRIPTIONS

METHODOLOGY AND CODING STYLE REQUIREMENTS

VHDL TYPES

VHDL OBJECT CLASSES

1.5.11.5.21.5.3

ConstantSignal and VariableFile

1.6 VHDL DESIGN UNITS

1.6.1 ENTITY1.6.1.1 Style

1.6.1.1.11.6.1.1.21.6.1.1.31.6.1.1.41.6.1.1.51.6.1.1.61.6.1.1.71.6.1.1.8

CommentHeaderGenericsIndentationLine lengthStatements per lineDeclarations per lineAlignment of declarations

1.6.1.2 Entity Ports1.6.2 ARCHITECTURE

1.6.2.1 Process1.7 COMPILATION, ELABORATION, SIMULATION

1.7.11.7.21.7.3

Compilation ExampleSimulation ExampleSynthesis Example

2.0 BASIC LANGUAGE ELEMENTS

2.1 LEXICAL ELEMENTS2.1.1 Identifiers

2.1.1.12.1.1.22.1.1.32.1.1.4

Port IdentifiersIdentifier Naming ConvensionAccessing Identifiers Defined in PackagesCapitalization

2.2 SYNTAX2.2.12.2.2

DelimitersLiterals

2.2.2.12.2.2.22.2.2.32.2.2.42.2.2.5

Decimal literalsBased literalsCharacter literalsString literalsBit string literals

2.2.3 Operators and Operator Precedence2.2.3.12.2.3.22.2.3.32.2.3.4

Logical operatorsRelational OperatorsShift OperatorsThe Concatenation "&" Operator

1

123456799

1010111212131313131414161720232425

29

29293132363738394040404041414243434446

vi VHDL Coding Styles and Methodologies

2.2.3.5 Remainder and Modulus2.3 TYPES AND SUBTYPES

2.3.1 Scalar Type2.3.1.12.3.1.2

Integer Type and SubtypesEnumeration Types

2.3.1.2.12.3.1.2.22.3.1.2.3

User Defined Enumeration TypesPredefined Enumeration TypesBoolean Type

2.3.1.32.3.1.42.3.1.5

Physical typesDistinct Types and Type ConversionReal type

2.3.2 Composite2.3.2.1 Arrays

2.3.2.1.12.3.2.1.22.3.2.1.32.3.2.1.42.3.2.1.52.3.2.1.6

One Dimensional ArraysUnconstrained Array TypesMulti-dimensional Array typesAnonymous ArraysImplicit Functions for Array DeclarationsArray Slices and Ranges

2.3.2.2 Records2.3.3 Access Type

2.42.52.6

FILE

ATTRIBUTES

ALIASES

3.0 CONTROL STRUCTURES

3.13.2

EXPRESSION CLASSIFICATION

CONTROL STRUCTURES3.2.13.2.2

The "if" StatementThe Case Statement

3.2.2.1 Rules for the Case Statement3.2.33.2.43.2.5

Latch InferenceRegister InferenceLoop Statement

3.2.5.13.2.5.23.2.5.3

The Simple LoopThe while loopThe for loop

3.2.5.3.1 for loop Rules

4.0 DRIVERS

4.14.2

RESOLUTION FUNCTION

DRIVERS4.2.14.2.24.2.3

Definition and InitializationCreation of DriversDrivers and Resolved Signal Types

4.2.3.1 Driving Data from multiple Processes onto a Non-Resolved Signal4.3 PORTS

5.0 VHDL TIMING

5.15.2

SIGNAL ATTRIBUTESTHE "WAIT" STATEMENT

5.2.15.2.2

Delta Timewait on sensitivity_list

474849495151545656586061616164687070737476788186

91

9192939699

103104104105106107107

115

115117117120121121123

129

129136137139

Table of Contents vii

5.2.35.2.4

wait until conditionwait for time_expression

5.35.4

SIMULATION ENGINE

MODELING WITH DELTA TIME DELAYS5.4.15.4.25.4.35.4.4

Wait for 0 ns Method

139141143146146147147148148149

Concurrent Statements MethodUse of Variables MethodVITAL Tables

5.5 INERTIAL / TRANSPORT DELAY

5.5.1 Simulation Engine Handling of Inertial Delay5.5.1.15.5.1.2

Simple ViewUpdating Projected Waveforms per LRM 8.4.1

149149

6.0 ELEMENTS OF ENTITY/ARCHITECTURE 157

6.16.2

VHDL ENTITY 157162164168

VHDL ARCHITECTURE

6.2.16.2.2

Process StatementConcurrent Signal Assignment Statements

6.2.2.16.2.2.2

Conditional Signal AssignmentSelected Signal Assignment

169170

6.2.3 Component Instantiation Statement 1716.2.3.1 Port Association Rules

6.2.3.1.16.2.3.1.2

Connection174174176Type Conversion

6.2.46.2.56.2.66.2.7

Concurrent Procedure Call 178179181183

Generate StatementConcurrent Assertion StatementBlock Statement

6.2.7.1 Guarded Signal Assignments 186

7.0 SUBPROGRAMS 193

7.17.2

SUBPROGRAM DEFINITION 193196196198

SUBPROGRAM RULES AND GUIDELINES

7.2.17.2.27.2.37.2.47.2.57.2.67.2.77.2.8

Unconstrained Arrays in SubprogramsInterface class declarationSubprogram InitializationSubprogram Implicit Signal AttributesPassing Subtypes

201202204205206208

Drivers in SubprogramsSignal Characteristics in Procedure CallsSide Effects

7.2.8.1 Separating HighLevelTasks FromLowLevel Protocols 2097.2.9 Positional and Named Notation 212

212212216218220

7.37.47.57.67.7

SUBPROGRAM OVERLOADINGFUNCTIONSRESOLUTION FUNCTION

OPERATOR OVERLOADINGCONCURRENT PROCEDURE

8.0 PACKAGES 227

227228

8.1 PACKAGE

8.1.1 Package Declaration

viii VHDL Coding Styles and Methodologies

8.1.28.1.38.1.48.1.58.1.68.1.7

Package Body 229231232235236238238243248250255256257257

Deferred ConstantThe "use" ClauseSignals in PackagesResolution Function in PackagesSubprograms in Packages

8.28.3

CONVERTING TYPED OBJECTS TO STRINGSPACKAGE TEXTIO

8.3.1 Printing Objects from VHDL8.4 DESIGN OF A LINEAR FEEDBACK SHIFT REGISTER (LFSR)

8.4.1 Random Number Generation8.5 COMPILATION ORDER

8.5.18.5.2

Compilation Rules on ChangesAutomatic Analysis of Dependencies

9.0 USER DEFINED ATTRIBUTES, SPECIFICATIONS, AND CONFIGURATIONS 261

9.19.29.3

ATTRIBUTE DECLARATIONS 261262264264269269270273277277279

USER-DEFINED ATTRIBUTES

SPECIFICATIONS9.3.1 Attribute Specifications

9.4 CONFIGURATION SPECIFICATION

9.4.1 Default Binding Indication9.4.2 Explicit Binding Indication in Configuration Specifications

9.5 CONFIGURATION DECLARATION9.5.19.5.29.5.3

Binding with configured componentsCONFIGURATION OF GENERATE STATEMENTSDeferring the Binding of an Instance of a Component

10.0 DESIGN FOR SYNTHESIS 281

282284284285288289289292294296298298304305

309

310310313

10.110.2

CONSTRUCTS FOR SYNTHESISREGISTER INFERENCE

10.2.110.2.210.2.310.2.4

Signals Assignments in Clocked ProcessVariable assignments in clocked processAsynchronous Reset or Set of RegistersSynchronous Reset or Set of Registers

10.3 COMBINATIONAL LOGIC INFERENCE10.3.110.3.2

Latch Inference and AvoidanceVariable

10.410.5

STATE MACHINERTL STATE MACHINE DESIGN STYLES

10.5.110.5.2

State Machine StylesSafe FSM with No Lock up

10.6 ARITHMETIC OPERATIONS

11.0 FUNCTIONAL MODELS AND TESTBENCHES

11.1 TESTBENCH MODELING11.1.111.1.2

Testbench OverviewTestbench Design Methodology

11.1.2.111.1.2.211.1.2.3

Validation Plan 313315316

List of errors to be detectedArchitecture block diagram

Table of Contents ix

11.1.2.4 Testbench design11.1.3 Testbench Architectures

316316

11.1.3.1 Typical Testbench Architecture 31711.1.4 FM/BFM Modeling Requirements 320

11.2 SCENARIO GENERATION SCHEMES 32111.2.1 Scenario Generation Model: VHDL Code 325

11.2.1.1 Waveform Generator 32511.2.1.2 Client/Server 327

11.2.2 Scenario Generation Model: Text Command File 33511.2.3 Scenario Generation Model: Binary Command File 346

11.2.3.1 Generation of Binary Files 347

12.0 UART PROJECT 353

12.1 UART ARCHITECTURE 35312.1.1 UART Transmitter 353

12.1.1.112.1.1.2

General UART Concepts 353UART Transmitter design 354

12.1.2 UART Receiver 357361365368370371372374380

383

384384384385386391

12.2 UART TESTBENCH

12.2.112.2.212.2.312.2.412.2.512.2.612.2.7

UART PackageTransmit ProtocolReceive Protocol ComponentTransmission Line ComponentMonitor or Verifier ComponentTestbench Entity and ArchitectureConfiguration

13.0 VITAL

13.1 VITAL13.1.1 Overview

13.213.3

VITAL FEATURESVITAL MODEL

13.3.113.3.2

Pin-to-Pin Delay Modeling StyleDistributed Delay Modeling Style

APPENDIX A

APPENDIX B

APPENDIX C

APPENDIX D

APPENDIX E

APPENDIX F

APPENDIX G

APPENDIX H

VHDL'93 AND VHDL'81 SYNTAX SUMMARY

PACKAGE STANDARD

PACKAGE TEXTIO

STD_LOGIC_TEXTIO

PACKAGE STD_LOGIC_1164

NUMERIC_STD

STD_LOGIC_UNSIGNED

STD_LOGIC_SIGNED

395

405

407

409

411

415

427

429

x VHDL Coding Styles and Methodologies

APPENDIX I

APPENDIX J

APPENDIX K

STD_LOGIC_ARITH

STD_LOGIC_MISC

VHDL PREDEFINED ATTRIBUTES

431

435

439

443INDEX

PREFACE

VHDL Coding Styles and Methodologies, Edition is a follow up book to the firstedition of same book and to VHDL Answers to Frequently Asked Questions, first andsecond editions. This book was originally written as a teaching tool for a VHDL trainingcourse. The author began writing the book because he could not find a practical and easyto read book that gave in depth coverage of both, the language and coding methodologies.This edition provides practical information on reusable software methodologies for thedesign of bus functional models for testbenches. It also provides guidelines in the use ofVHDL for synthesis. All VHDL code described in the book is on a companion CD. TheCD also includes the GNU toolsuite with EMACS language sensitive editor (with VHDL,Verilog, and other language templates), and TSHELL tools that emulate a Unix shell.Model Technology graciously included a timed evaluation version of ModelSim, arecognized industry standard VHDL/Verilog compiler and simulator that supports easyviewing of the models under analysis, along with many debug features. In addition,Synplicity included a timed version of Synplify, a very efficient, user friendly and easy touse FPGA synthesis tool. Synplify provides a user both the RTL and gate level views ofthe synthesized model, and a performance report of the design. Optimization mechanismsare provided in the tool.

This book is intended for:

1.

2.

College students. It is organized in thirteen chapters, each covering a separateaspect of the language, with complete examples. Students can compile andsimulate the examples to get a greater understanding of the language. Each chapterincludes a series of exercises to reinforce the concepts.

Engineers. It is written by an aerospace engineer who has many years ofhardware, software, computer architecture and simulation experience. It coverspractical applications of VHDL with coding styles and methodologies thatrepresent what is current in the industry. VHDL synthesizable constructs areidentified. Included are practical guidelines for the design of bus functionalmodels used in testbenches, such as waveform generation, client/server control,text and binary file command methods, and binary file generation schemes. Alsoincluded is an elaboration of a project for the design of a synthesizable UniversalAsynchronous Receiver Transmitter (UART), and a testbench to verify properoperation of the UART in a realistic environment, with CPU interfaces andtransmission line jitter. An introduction to VHDL Initiative Toward ASICLibraries (VITAL) is also provided. The book emphasizes VHDL 1987 standardbut provides guidelines for features implemented in VHDL 1993.

xii VHDL Coding Styles and Methodologies

This book differs from other VHDL books in the following respects:1.

2.

3.

4.

5.6.7.

8.

9.10.

Emphasizes VHDL core, Ada like sequential aspects and restrictions, along withthe VHDL specific, concurrent aspects of the language.Uses complete examples with good code, and code with common mistakesexperienced by users to demonstrate the language restrictions andmisunderstandings.Provides a CD that includes all the book examples in addition to GNU EMACSlanguage sensitive editor, other useful reference VHDL code material, and GNUTSHELL.Uses an easy to remember symbology notation throughout the book to emphasizelanguage rules, good and poor methodology and coding styles.Identifies obsolete VHDL constructs to be avoided.Identifies non-synthesizable structures.Covers practical design of testbenches for modeling the environment andautomatic verification of a unit under test.Provides a complete design example that uses the guidelines presented in thebook.Provides an introduction to VITAL.Provides guidelines for synthesis and identifies the VHDL constructs that aretypically synthesizable.

This book is organized in four basic VHDL aspects:1.

2.

3.

4.

SEQUENTIAL LANGUAGE. This is similar to the sequential aspects of otherprogramming languages like C or Ada. Chapter 1 provides sufficient knowledgeto compile and simulate a simple counter. Chapter 2 covers the basic languageelements including the lexical elements, the syntax, and the types. Chapter 3discusses the control structures.CONCURRENCY. This differentiates VHDL from other sequential languages.Chapter 4 discusses drivers, chapter 5 covers the timing and chapter 6emphasizes the concurrent statements.ADVANCED TOPICS. This includes subprograms in chapter 7, packages inchapter 8, and attributes, specifications and configurations in chapter 9, anddesign for synthesis in chapter 10.APPLICATIONS. This emphasizes reusable software methods to generatefunctional models, bus functional models, and testbench designs in chapter 11; aUART project with synthesizable transmitter and receiver in a testbenchenvironment in chapter 12; VITAL coding style optional methodology in chapter13.

The language rules, coding styles, and methodologies presented in this book support thestructure necessary to create digital hardware designs and models that are readable,maintainable, predictable, and efficient.

About The CD

Table 1 summarizes the contents of the enclosed CD.

NOTATION CONVENTIONS

The following symbols and syntactic description are used to facilitate the learning ofVHDL.

SYMBOLS

Methodology and guideline.

Two thumbs up. Good methodology or approach.

Two thumbs down. Poor methodology or approach.

Disagreement in community on methodology or approach.

Legal or OK code

Coding Error

Synthesizable

Non-SynthesizableEllipsis points in code: Source code not relevant to discussion.

[1] Quotations reprinted from IEEE Std 1076-1993 IEEE Standard VHDLLanguage Reference Manual (LRM). Quotations printed in "italic and in thisfont". Syntax reprinted from the LRM "in this font", but without the prefix [1].

Boldface Boldface in text: Emphasizes important points.Boldface in syntax and sample code: Emphasizes VHDL reserved words.

xvi VHDL Coding Styles and Methodologies

SYNTACTIC DESCRIPTION

::= (read as "can be replaced by")

Vertical bar separates alternative items

left_hand_side ::= right_hand sideleft_hand_side is the syntactic categoryright_hand_side is a replacement rule

Example: letter_or_digit ::= letter | digit

Square brackets [] enclose optional itemsExample: return_statement ::= return [expression]

Braces {} enclose a repeated item (zero or more times).Example: index_constraint ::= (discrete_range, {discrete_rang})

Underlined identifies that the notation is applicable for VHDL’93 ONLYExample: … end [configuration] [configuration_simple_name]

Acknowledgments

VHDL Coding Styles and Methodologies, Edition evolved from the previous editionof this book, and from VHDL Answers to Frequently Asked Questions, first and secondeditions. It also evolved from several documents and discussions with severalindividuals, along with personal experiences and frustration of students in using VHDL.

I thank Model Technology for allowing me access to ModelSim, an excellent and easy touse VHDL/Verilog compiler/simulator, and for their excellent product support. I thankSynplicity for allowing me access to Synplify, a very efficient, user friendly and easy touse FPGA synthesis tool. I also thank these two companies for providing evaluationcopies of their tools in this book.

I thank Peter Sinander from the European Space Agency for publishing on the Internet

the document VHDL Modelling Guidelines2. I thank Janick Bergeron from QualisDesign Corp for publishing on the Internet the document Guidelines for Writing VHDL

Models in a Team Environment3. Those documents contributed to many of the codingstyles presented in this book. I thank Richard Hall from Cadence Design Systems, Inc.who reviewed the original version of this book and provided many suggestions. I thankLarry Saunders, Steve Schoessow, Johan Sandstrom, and John Coffin for various VHDLdiscussions we had over the years on the use of VHDL. I thank Synopsys, Inc. for therelease of their VHDL packages.

I thank Geoff Voelker, Andrew Innes and Reto Zimmermann for their effort in providingGNU Emacs for Windows NT and Windows 95/98. I thank James Fulcomer and DrewDavidoff for their inquisitive challenges in the use of the language, in addition tocompiling the GNU software into an easy to install package.

I also thank my publisher Carl Harris for supporting in these endeavors of publishingbooks.

I acknowledge my daughter Lori Hillary, and my son Michael Lloyd for inspiring me toteach.

I especially thank my wife, Gloria Jean, for her patience and support in these projects

2 The VHDL Modelling Guidelines document is available through anonymous ftp fromftp.estec.esa.nl in the "/pub/vhdl" directory.3 The Guidelines for Writing VHDL Models in a Team Environment is available via ftp fromvhdl.org as /pub/misc/guidelines.paper.ps.

xviii VHDL Coding Style and Methodologies

About the Author

Ben Cohen has an MSEE from USC and is a Scientist engineer at Raytheon SystemsCompany. He has technical experience in digital and analog hardware design, computerarchitecture, ASIC design, synthesis, and use of hardware description languages formodeling of statistical simulations, instruction set descriptions, and hardware models. Heapplied VHDL since 1990 to model various bus functional models of computer interfaces.He authored VHDL Coding Styles and Methodologies, 1st Edition, and VHDL Answersto Frequently Asked Questions, first and second editions. He was one of the pilot teammembers of the VHDL Synthesis Interoperability Working Group of the DesignAutomation Standards Committee who authored the IEEE P 1076.6 Standard For VHDLRegister Transfer Level Synthesis. He has taught several VHDL training classes, and hasprovided VHDL consulting services on several tasks.

email: VhdlCohen@aol.comWeb page: http://members.aol.com/vhdlcohen/vhdl