Overcoming Phase Sensitivity in Real-Time Parallel DSP for Optical Coherent Communications: Optically Filtered Lasers

JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 32, NO. 3, FEBRUARY 1, 2014 411

Overcoming Phase Sensitivity in Real-Time ParallelDSP for Optical Coherent Communications:

Optically Filtered LasersWing-Chau Ng, An T. Nguyen, Simon Ayotte, Chul Soo Park, Member, IEEE, and Leslie A. Rusch, Fellow, IEEE

Abstract—Implementation of real-time giga-Baud optical coher-ent systems for single-carrier higher-level modulation format suchas 64-quadrature amplitude modulation (QAM) depends heavilyon phase tracking. For offline digital signal processing, decision-directed phase recovery is performed at symbol rate with the bestperformance and the least computational effort compared amongother best-known algorithms. However, in real-time systems, hard-ware parallelization and pipelining delay on feedback path posestringer requirement on the linewidth, or the frequency noise spec-tral level of laser sources. This leads to the paucity of experi-ments demonstrating real-time phase tracking for 64- or higherQAM. In this paper, we experimentally investigate the impact ofoptically-filtered lasers on parallel and pipelined phase tracking ina single-carrier 5 Gbaud 64-QAM back-to-back coherent system.For parallelization levels higher than 24, the optically-filtered lasershows more than 2 dB improvement in optical signal-to-noise ratiopenalty compared to that of the same laser without optical filtering.

Index Terms—Coherent detection, fiber Bragg grating, phaserecovery, 64-QAM.

I. INTRODUCTION

H IGH performance optical coherent communications hasbecome commercially viable due to the availability of

digital signal processing (DSP) [1]–[3] and high-speed analog-to-digital converter (ADC). ADCs are integrated onto a sin-gle CMOS chip with an application specific integrated circuit(ASIC) exploiting a time-interleaved structure [3]–[7]. Power-optimized ASIC designs allow efficient real-time calibration oftime skew and offset mismatch between time-interleaved chan-nels [4]–[6]. While higher order modulation formats enabled bycoherent detection are sensitive to phase noise, the emergenceof inexpensive sub-MHz-linewidth C-band semiconductor lasersources have led to spectrally efficient coherent systems. Exter-nal cavity lasers (ECLs) and integrated tunable laser assembly

Manuscript received August 8, 2013; revised October 26, 2013; acceptedNovember 29, 2013. Date of publication December 4, 2013; date of currentversion December 23, 2013. This work was supported in part the Natural Sci-ences and Engineering Research Council of Canada CREATE program for NextGeneration Optical Networks under Grant 214200).

W. C. Ng, A. T. Nguyen, C. S. Park, and L. A. Rusch are withthe Center d’optique photonique et laser, Department of Electrical andComputer Engineering, Universite Laval, Quebec, QC G1V 0A6, Canada(e-mail: [email protected]; [email protected]; [email protected]; [email protected]).

S. Ayotte is with TeraXion Inc., Quebec, QC G1P 4S8, Canada (e-mail:[email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/JLT.2013.2294135

(ITLA) have typical linewidths of 100 and 10 kHz, respectively,enabling phase tracking in digital coherent receivers for quadra-ture amplitude modulation (QAM).

To recover the transmitted QAM signal in a digital coher-ent receiver, the phase of the received signal must be tracked.The three best-known phase tracking algorithms are feedfor-ward modified Mth power algorithm (FF-MMPA) [8], [9], blindphase search (FF-BPS) [10] and decision-directed phase recov-ery (DD-PR) [11]. For 64-QAM or higher, FF-MMPA showsextra optical signal-to-noise ratio (OSNR) penalty due to am-plitude discrimination and its stringent laser linewidth require-ment, while FF-BPS requires tremendous computational effortto provide necessary phase resolution. DD-PR requires the leastcomputational effort and does not require amplitude discrimina-tion, and is typically used for 64-QAM experimental demonstra-tions with offline DSP [12]–[15]. Nevertheless, feedback delayremains an obstacle to implement DD-PR in real-time [12].

For real-time systems, serial symbol-by-symbol phase track-ing is not available, as the state-of-the-art ASIC or field pro-grammable gate array (FPGA) cannot perform DSP at Gbaudrates [2], [3], [5]–[7]. The received signal must be demulti-plexed into sub-GHz parallelized channels for DSP. The effec-tive sampling rate for each channel is multiplied by the numberof parallel channels, with a proportional increase in the effec-tive phase noise on each channel. For phase tracking algorithmswith feedback delay this effect is further aggravated [10]. In thiscase, the estimated phase lags the current received symbol by aduration proportional to product of the parallelization level andthe number of pipelining delay elements on the feedback path,again increasing phase tracking error [16], [17].

A superscalar structure was proposed in [16] to avoid thefeedback delay, in which large memory blocks temporarily storereceived symbols and phase tracking is performed in each blockserially. This results in larger power consumption and high hard-ware complexity. Parallelization remains the most power effi-cient and cost effective solutions for phase tracking algorithms.Examples for parallel phase tracking with feedback for 16-QAMor higher include decision-directed maximum likelihood esti-mation (DD-MLE) by Zhang et al. [18] and decision-directedphase locked loop (DD-PLL) by Zhou and Sun [19].

Recent experiments for real-time phase tracking address onlyquadrature-phase-shift-keying (QPSK) and 16-QAM. Fukuchiet al. [20] demonstrated polarization-multiplexed (PM)-QPSKin a 16-card parallel FPGA-based real-time DSP at 112 Gb/swith superscalar structure. Ogasahara et al. [21] demonstratedPM-QPSK with 1072-km transmission in a 32-card parallel

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412 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 32, NO. 3, FEBRUARY 1, 2014

FPGA-based real-time DSP at 112 Gb/s. Crivelli et al. [6] real-ized a 16-parallel time-interleaved DD-PR at a clock frequencyof 781.25 MHz in a 40-nm CMOS chip for 12.5 Gbaud PM-QPSK. On the other hand, Pfau et al. [22] demonstrated real-time 5 Gbaud 16-QAM with only a feed forward algorithm in32-parallel channels at 156.25 MHz. At the baud rates examinedand for the laser sources used, i.e., for the symbol-time linewidthproducts examined, neither QPSK nor 16-QAM is vulnerable tofeedback delay.

The greater vulnerability of 64-QAM to phase noise has madesuch systems difficult to demonstrate in real-time. The only real-time demonstration of 64-QAM was reported by Yoshida et al.[23]. An optical phase locked loop and additional laser tones forphase tracking were required to reduce the complexity of DSPin the real-time FPGA receiver. The paucity of experimentsindicates that parallel DSP for 64 QAM has not been fullyexplored, and suggests that implementing real-time 64-QAM(or higher density constellations) relies on laser sources withlower phase noise.

The strong white frequency noise of current low-linewidthsemiconductor lasers can be suppressed markedly by employ-ing a fiber Bragg grating (FBG) [24]. Ayotte et al. [25], showeda Q2-factor improvement of 1.7 dB using FBG-filtered 10-kHz-linewidth lasers in a homodyne 64-QAM system using onlyserial DSP. We showed BER improvement by using FBG fil-tering for 100-kHz linewidth lasers for 16-QAM using parallelDD-MLE and DD-PLL [26]. The impact of feedback of parallelDD-PR for 64-QAM was not investigated, nor were bit-error-rate (BER) measurements produced previously. Starting fromthe lowest linewidth commercial laser and adding optical sig-nal processing results in the lowest phase noise available onthe market, and allows us to probe the limits of M-ary QAMmodulation performance dominated by phase impairments.

In this paper, we experimentally compare the performanceof filtered and unfiltered laser sources. We demonstrate andquantify the BER improvement due to FBG-filtering when usingparallel DD-MLE with four pipelining delays on the feedbackpath [18] in our off-line processing emulating real-time, parallelDSP. We report single-carrier 5-Gbaud 64-QAM back-to-backheterodyne coherent system performance.

This paper is organized as follows. The noise reduction tech-nique is recalled in Section II, along with laser phase noise char-acterization. We discuss qualitatively the impact of paralleliza-tion and phase noise reduction given by FBG-filtered source onBER in Section III. Experimental 64 QAM measurements arepresented in Section IV, followed by results and discussion inSection V. We conclude in Section VI.

II. LASER SYSTEM DESCRIPTION

The laser sources used are TeraXion PS-TNLs with an ITLAand a FBG to suppress the phase noise. The optical filter pro-duces 51 narrowband transmission peaks separated by 100 GHz[24]. The interleaved spectral responses present a narrow trans-mission peak (FWHM of 49 to 77 MHz for all channels) at every115 GHz from 191.4 to 196.6 THz, so that one peak can be ther-mally tuned to any frequency within this range. Fig. 1 shows

Fig. 1. Transmission spectrum of the FBG assembly.

Fig. 2. Frequency locking schematic. TEC: thermoelectric cooler.

the optical spectrum of the FBG assembly including a polar-ization isolator and a polarizing tap isolator, measured betweenpoints A and B on Fig. 2. The ITLA has a measured linewidthof 10 kHz.

The optical filtering of the laser spectrum is achieved bycontrol of the laser carrier and the narrow transmission peakof the FBG assembly. Fig. 2 illustrates the frequency lockingmechanism. A dithering signal modulates the ITLA. The filteredsignal is detected and sent to the control electronics. Correctionsignals are generated to maintain alignment of the ITLA car-rier frequency with a selected transmission peak. Both thermaltuning of the optical filter and ITLA carrier frequency controlis applied to correct the misalignment. Eventually slow varia-tions become less detrimental to phase estimation, whereas fastfrequency fluctuation associated to the wings of the laser spec-trum falling outside of the narrowband transmission peak aresuppressed. The optical filtering scheme covers whole C-band.

For laser sources having pure Brownian phase noise (orequivalently white frequency noise), the linewidth is definedas the 3-dB width of the Lorentzian field power spectral density(PSD) [27]. To understand the interplay of phase noise reductionwith phase tracking algorithms working in a parallel architec-ture, we must turn to the frequency noise power spectral density(FN-PSD). Brownian phase noise leads to a flat FN-PSD. A car-toon of FN-PSD is given in Fig. 3. The black solid line showsthe mid-frequency band (from 10 to 100 MHz) dominated byBrownian phase noise, i.e., SΔf ,BM (f) = Δν/2π, where Δνis the double of the original laser linewidth (because of themixing in homodyne detection); it is constant over frequency.Conventionally, laser linewidth allows a quick quantification ofphase-error variance in coherent communication systems withBrownian phase noise for system performance analysis [28].

NG et al.: OVERCOMING PHASE SENSITIVITY IN REAL-TIME PARALLEL DSP FOR OPTICAL COHERENT COMMUNICATIONS 413

Fig. 3. Cartoon of frequency-noise power spectral density for a laser withactive frequency noise reduction.

Additive white Gaussian noise (AWGN) results in a flatphase-noise power spectral density (PN-PSD), or an upwardsloping line in the FN-PSD. The AWGN FN-PSD, found in theAppendix is

[SΔf ,AWNG (f)]dB =[No/

(2A2)]

dB+ 20 log10 f (1)

where No is the two-sided field PSD of white Gaussian noise(flat noise floor appeared in field PSD), and A is the amplitudeof electric field of the receiver signal in the absence of noise.As illustrated in Fig. 3 (blue dotted, upward sloping line), thef 2-FN AWGN measurement noise dominates the filtered sourceat high frequencies (starting from hundreds of MHz).

Following the FBG filtering, the phase noise is no longerBrownian (the frequency noise is colored), and therefore thesimple parameterization by the linewidth is no longer valid, i.e.,the FN-PSD is no longer flat at mid-frequencies. In particular,filtering by the ultra narrowband FBG will create a downwardslope in the FN-PSD shown in Fig. 3 (red dash).

As the ITLA laser linewidth is inappropriate to characterizethe filtered ITLA, we must turn to other parameters. One def-inition of the suppression accorded by the noise filtering is tomeasure the reduction in FN-PSD at the point where measure-ment noise obscures laser phase noise, as illustrated in Fig. 3(green, dot-dashed lines). This parameterization, however, doesnot capture the frequency dependence of FN-PSD. The objec-tive of this paper is to quantify the performance improvementfor BER in the presence of parallelization in phase tracking. Thelevel of parallelization will determine which frequency regionwill dominate. Greater parallelization level will lead to FN-PSDin the shaded region of Fig. 3 playing a greater role in overallperformance.

TeraXion PS-TNLs provides two modes of operation: 1) a na-tive mode, with the FBG at full transmission (without filtering),2) a low-noise mode, with FBG filtering starting at 10 MHz.The FN-PSD of the two operating modes of the PS-TNL areshown in Fig. 4 as measured with a self-homodyne coherent de-tection setup [29]. Note that switching to the low-noise mode ofPS-TNLs reduces laser phase noise, but the phase-noise statis-tics are changed so that the linewidth is no longer uniquelydefined [29] (the field PSD does not have a Lorentzian shape).In Fig. 4, the upper curve shows the FN-PSD of the free-runninglaser without FBG filtering, and the lower curve shows that op-tical filtering by an FBG suppresses the white FN by 4 dB at

Fig. 4. FN-PSD of native mode (without FBG) and low-noise mode (withFBG).

Fig. 5. Parallel implementation of DD-MLE [18].

frequencies above 50 MHz. The f 2-FN (upward sloping) noisedoes not come from the lasers themselves, but mainly from theelectrical noise of our coherent receiver.

III. IMPACT OF FILTERED SOURCES ON PHASE TRACKING

There are two practical problems in the implementation ofDSP for optical communication. First, power consumption ofCMOS chips increases linearly with clock frequency [30],(3.10)], and therefore increases with data rate; DSP at lowerclock speed provides power savings. Second, the currently avail-able ASICs and reconfigurable FPGA cannot process at Gbaudrates. Parallel processing and pipelining are required, whichtremendously increases the effective linewidth of lasers.

For parallel processing, the serial data is acquired in a time-interleaved manner into several parallel channels having dupli-cate processing hardware [30]. This allows processing multipledata in parallel in a clock period. With time-interleaved paral-lelization, the received symbols at Gbaud rates (symbol periodTsym ) are demultiplexed into P sub-GHz channels for DSP. Forexample, in Fig. 5, during the first round of time interleaving,P symbols, r[k], r[k-1] . . ., r[k-P+1] arrive at the input of thefirst, second, . . ., P th channel, respectively. Next, another Psymbols, r[k+P], r[k+P-1], . . ., r[k+1] follow, and the processwill repeat. Thus, the ith channel receives time-interleaved sym-bols r[k-i+1], r[k-P-i+1], r[k-2P-i+1], and so on, where i is theindex of parallelization channels, taken from 1 to P , where Pis the number of parallelization. Two adjacent symbols in eachchannel have a time separation of P×Tsym , instead of Tsym in


Fig. 6. True phase versus time illustrating delayed phase-noise compensationdue to four pipelining registers on the feedback path in parallel DD-MLE.

serial processing. As a result, each channel perceives laser phasenoise having a variance of 2π(PΔν)Tsym , i.e., time-interleavedparallelization increases the effective laser linewidth by a factorof P .

Even though ASIC design allows higher processing speedthan FPGAs by circuit optimization, multipliers and lookuptables are unavoidable sources of latency. The throughput ofan algorithm simply cannot keep up with the input data rate(sampling rate) at each parallelization channel. Pipelining mustbe introduced in order to increase the effective sampling rate[30]. For example, an algorithm usually consists of multipliers,slicers and lookup tables that cannot be implemented withinone clock cycle. Thus pipelining is required, in which delays(flip-flops [10] or so-called pipelining registers [30]) are addedbetween individual operations requiring a clock cycle or less;the immediate result of each operation is stored in registers forsubsequent manipulation.

Decision-directed phase recovery (DD-PR) is the preferredsolution for high baud rate, higher-density constellation sys-tems. The serial DD-PR intrinsically contains one symbol delayon the feedback path. To realize parallel DD-PR in ASIC orFPGA, however, the feedback delay is increased (as discussedin Section I). To illustrate the effect of feedback delay in par-allel DD-PR, we select the decision-directed maximum likeli-hood estimation (DD-MLE). This algorithm has four pipeliningregisters in the closed loop [18], instead of five in that of DD-PLL [19]; thus DD-MLE can perform better than DD-PLL [26]when parallelized. As shown in Fig. 6, the estimated phase isgenerated using (k-5P+1)th to (k-4P )th symbols. The com-pensation is applied to the (k-P+1)th to kth received symbols,introducing a lag of approximately (4 × P × Tsym ) seconds.Delayed phase noise compensation caused by pipelining regis-ters on feedback path further increases phase error variance toapproximately 2π(4PΔν)Tsym , i.e., the effective laser linewidthfurther increases in the DD-MLE case by four. Pipelining delaysare detrimental to real-time feedback-delayed phase tracking atGbaud-rate optical communications.

Intuitively, lower FN-PSD level results in a smaller parallelphase tracking error. In the following, we will first discuss inbrief the bandwidth reduction of parallel digital feedback loop,and then give a heuristic approach to see the intuitive relationship

between the FN-PSD level and the parallelization levels using afeedback loop for 64-QAM.

Assuming zero frequency offset, for Brownian phase noise,the phase-noise increment between two adjacent symbols is aGaussian process with zero mean and a variance 2π(Δν)Tsym ,where Tsym is the symbol duration, Δν is the total laserlinewidth (transmitter and receiver). As the conventional def-inition of laser linewidth no longer holds, it is more appro-priate to express the variance of phase-noise increment as2π[2πSΔf (f)]Tsym , where SΔf (f) refers to the total two-sidedFN-PSD containing both transmit and receive laser phase noiseas discussed in Section III.

For serial tracking, DD-MLE can be linearized as the follow-ing first-order discrete loop equation [31, (6)],

θk+1 = θk + U, (2)

where θ is the phase estimate, and U is the phase increment;U is a function of the parameters of the moving average filter,laser phase noise variance and SNR. For parallel tracking withfeedback delay, following the derivation from Zhang et al. [20],(2) can be modified as

θk−i+1 = θk−D−i+1 + f({

θ, θk−D−i+1 ,A,n∗1

})

θ = [θm ]k−Dm=k−D−P +1 ,A = [Am ]k−D

m=k−D−P +1

n∗1 =

[n∗

1,m

]k−D

m=k−D−P +1 (3)

where D = P × d, and d is the number of pipelining registersin the closed loop. θk , A, and n1

∗ are vectors of true phases,transmitted symbols and the AWGN, respectively, taking fromk-D-P+1 to k-D. The second term of RHS of (3) is the incre-ment of the discrete loop equation, which is a function of phasetracking error, transmitted symbols and the AWGN seen in eachrail taking from k-D-P+1 to k-D (Appendix B). For higher par-allelization levels required to process Gbaud rates in opticalcommunications, the feedback delay of D symbols results inmuch higher phase error than that of serial tracking. For d > 1,the effect of the feedback delay dominates that of the movingaverage filter, and therefore the introduction of feedback delayequivalently reduces loop bandwidth and phase margin [31].

To maintain phase tracking, the phase-recovered symbolsshould fall well inside the decision boundary. The decisionboundary for 64-QAM is defined as the threshold angle be-yond which erroneous decision will happen. This threshold an-gle is calculated as the distance between the corner symbolof 64-QAM constellation and its closest symbol: 4.73 degrees(0.0263π radian). As previously mentioned, the feedback loopof parallel DD-PR introduces a delay between the phase esti-mate and the current symbol, the phase tracking loop bandwidthfor DSP in electronics becomes Rs /(d × P).

We propose a heuristic criterion to avoid loss of lock in phasetracking at moderate or high OSNR: the phase-noise incrementbetween two adjacent symbols in each parallelization channelshould be smaller than a certain threshold which is a fractionof 64-QAM decision boundary. The phase-noise increment overthe response time of the feedback loop Tloop is proportional to


the root-mean square of its variance

0.0263π/K ≥√

4π2S

(f =

Rs

Pd

)Tloop (4)

where Tloop is approximately equal to d × P × Tsym ,K is aproportionality constant, whose value depends on the desiredBER level at high OSNR. K is usually larger than unity to makethe threshold tighter in the presence of AWGN phase noise.Note that for phase tracking, we should observe FN-PSD atoperating frequency (loop bandwidth) f = Rs /(d × P), whichis the corner frequency beyond which the feedback loop startsto lose tracking. Equation (4) becomes

SΔf

(f =

Rs

Pd

)≤ (0.0263/K)2

4PdTsym(5)

Equation (5) tells us that when the parallelization level in-creases, the loop bandwidth of parallel DD-MLE reduces, andthe FN-PSD level has to be smaller by a factor of P in orderto maintain phase tracking. For filtered sources, the FN-PSD isshaped by FBG filter with a corner frequency smaller than thephase-tracking loop bandwidth. The FN-PSD level, due to theFBG suppression, is lower than that of the original laser withinthe loop bandwidth (as shown in the red-shaped region in Fig. 3,or 10–100 MHz in Fig. 4). Therefore filtered lasers can allowhigher parallelization for a fixed number of pipelining delayelements on the feedback path.

IV. 64-QAM EXPERIMENT

In this section, we compare the BER performance of FBG-filtered lasers (low-noise mode) with that of unfiltered lasers (na-tive mode) using parallel phase tracking in a time-interleavingstructure as discussed in Section III. Fig. 7 shows the experimen-tal setup for single polarization back-to-back 5 Gbaud 64-QAM.Two separate PS-TNLs tuned at 1550 nm were used as trans-mitter and local oscillator sources. To examine the effect ofFBG filtering, two different measurements were taken: 1) bothsources in native mode; 2) both sources in low-noise mode.

A 20-GSa/s, 6-bit arbitrary waveform generator (AWG) oper-ating at 4 samples per symbol was used to generate two 5 Gbaud8-level electrical signals. Data was a repeated sequence of 98304bits (limited by AWG memory) taken from a pseudo-random bitsequence of length 231–1, driving the in-phase/quadrature (IQ)modulator. Wiener-Hopf-based [32] predistortion was appliedto compensate for RF components and the imperfect linear gainof the power amplifier in the transmitter.

A combination of variable optical attenuator and EDFA wasused to adjust the received OSNR. To maintain the integratedcoherent receiver at its optimum operating point, the receivedoptical power was fixed at −8 dBm and the local oscillatorpower was set to 13.8 dBm. The coherently detected signal wassampled by the real time oscilloscope at 80 Gsa/s with 30-GHzelectrical bandwidth. The captured samples were then retimedand resampled to one sample per symbol for the subsequentDSP.

A coarse non-data-aided fast Fourier transform-based fre-quency offset compensation (NDA-FFT-FOC) [33] was per-

Fig. 7. Top: experimental setup of back-to-back 5-Gbaud 64-QAM. Rightbottom: Recovered 64 QAM constellation without parallelization at OSNR =28 dB (BER = 6e-5). IQ mod: In-phase/Quadrature modulator, AWG: Arbitrarywaveform generator, PM fiber: Polarization maintaining fiber, VOA: variableoptical attenuator, OBPF: optical bandpass filter, PC: polarization controller.Coh. Rx.: Coherent Receiver. RTO: Real time oscilloscope. EDFA: Erbiumdoped fiber amplifier.

formed in a block-wise fashion over 30,000 symbols. We appliedtraining-sequence-based Wiener-Hopf-based decision-directedequalizer (WH-DD-EQ) with 31 taps [32]. Fine NDA-FFT-FOCwas performed to further remove the effect of frequency offsetdynamics [34]. The serial data was demultiplexed into P chan-nels, where P was varied from 8 to 30 to observe the perfor-mance of different levels of parallelization.

BPS-based pre-rotation [34] was used to obtain the initialphase of the first symbol of each channel. Subsequently, par-allel DD-MLE (see Section III) was used for phase recovery,incurring a pipelining delay of four [18]. The P channels werethen recombined into a single data stream. We again applied31-tap WH-DD-EQ [32] to further equalize with the more reli-able decisions following phase recovery. Finally, hard decisionwas performed on I and Q individually, and we counted errors.Bit error rate (BER) was estimated over 7 114 200 bits for eachOSNR value, which allows reliable estimation down to BER =5.6e−5.

V. RESULTS AND DISCUSSION

In Fig. 8 we present BER versus OSNR results for nativemode (square markers) and low-noise mode (circle markers).For serial data processing (solid curves), the two sources offersimilar performance. For parallel DD-PR with P parallelizationlevel and d pipelining registers on feedback path, the processingrate of each channel becomes Rs /P , leading to larger phaseexcursions, where Rs is the optical baud rate. The feedbackdelay due to the d pipelining registers further reduces the loopbandwidth to approximately Rs /P /d, as discussed in Section III.Hence, in Fig. 8, parallel processing leads to an increase in BER,


Fig. 8. BER versus OSNR for native and low-noise mode of PS-TNLs forserial and parallel phase tracking (d = 4) with P = 12 and P = 24.

Fig. 9. OSNR penalty versus parallelization (d = 4) for back-to-back 5 Gbaud64-QAM. Upper curve: native mode. Lower curve: low-noise mode.

but the FEC threshold is still respected. For 12 parallel rails(dashed curves) and 24 rails (dotted curves) we see a reducedBER floor for the low noise mode.

With FBG noise suppression, the phase tracking error de-creases, improving BER. We swept parallelization levels P ,determined BER and calculated the OSNR penalty at BER =10−3 for each level as shown in Fig. 9. For P = 8 and 12, corre-sponding to phase tracking loop bandwidth of 156.25 MHz and104.17 MHz, respectively, the low-noise mode (with FBG noisesuppression) cannot provide significant improvement because,as shown in Fig. 4, in this frequency region the FN-PSD is mainlydue to the f 2 frequency noise (i.e., white phase noise [29]) of thecoherent receiver starting from 70 MHz. For higher paralleliza-tion, the phase tracking effective loop bandwidth falls within afrequency region where the f 2 frequency noise level of the co-herent receiver is lower than the white frequency noise level ofthe native mode (unfiltered laser), and therefore the frequency-noise suppression of the low-noise mode can be clearly ob-served. The low-noise mode shows a 2 dB improvement overtht native mode for P > 24. When using the native mode, par-allel DD-PR even fails for P > 26 while FBG filtering allowsthe break down point to extend up to P = 30.

Fig. 10(a) and Fig. 10(b) shows the recovered constellationdiagrams of native mode and low-noise mode, respectively, forP = 26 at OSNR = 32 dB. Fig. 10(a) shows the rotation of

Fig. 10. Constellations over 30 000 symbols, P = 26, d = 4, OSNR = 32 dBfor (a) native mode (BER = 1e-3) and (b) low-noise mode (BER = 4e-4).

symbols at the outermost ring, leading to high bit error rate(BER = 1e−3). With FBG suppression, the FN-PSD is lowered,helping the reduction of rotation of symbols at the outermostring (BER = 4e−4) as shown in Fig. 10(b).

As mentioned in Section III, power consumption of CMOSchips increases linearly with clock frequency [30], we compareP = 16 for native mode with P = 20 for low-noise mode forthe same OSNR penalty in Fig. 9. The decrease of processingrate from 312.5 MHz to 250 MHz allows a 6.3% reduction inpower consumption for performing phase recovery in hardware(Appendix C).

VI. CONCLUSION

We experimentally investigate the impact of an optically-filtered laser on parallel and pipelined DD-MLE in a single-carrier 5 Gbaud 64-QAM back-to-back heterodyne coherentsystem. Using FBG further suppresses the frequency noisespectral level of contemporary narrow-linewidth semiconduc-tor lasers such as ECL or ITLA. For parallelization level higherthan 24, the optically-filtered laser shows more than 2 dB im-provement in OSNR penalty compared to that of conventionallasers. For the same OSNR penalty, the optically-filtered laserpermits greater parallelization, e.g., increase from 16 to 20, toreduce the hardware processing rate from 312.5 to 250 MHz.

APPENDIX

A. PSD of White Phase Noise Section

This section supplements Section II, giving the origin of thef 2-curve at high frequencies in the AWGN FN-PSD in (1).While observable in several references on laser characterization,a thorough analysis is infrequent. Chen et al. [35] attributed sucha f 2-curve to optical ASE noise and fiber nonlinearity. How-ever, our previous work in [29, Fig. 2] that also experimentallyshowed the f 2-curve in the absence of fiber transmission contra-dicts this explanation, and suggests that the f 2-curve orginatesfrom the electrical noise of coherent receiver. To our best knowl-edge, Leeson [36] first illustrated that the f 2-curve on FN-PSDis due to white phase noise introduced by thermal noise ofelectrical oscillators (which appeared as a flat noise floor in PN-PSD), and approximated the level of the PN-PSD noise floor


using thermal-noise parameters. The small modification for thePN-PSD noise floor can be made by referring to the exact PDFfor white phase noise given by Fu and Kam [37].

After coherent detection, the measurement appears as a com-plex phasor in baseband

rk = Aejθk + nk (A.1)

where θk is the total laser phase noise, nk is the zero-mean whiteGaussian electrical noise of coherent receiver, with a varianceof σ2 contributed by thermal noise and LO-noise beating, A isthe real amplitude of measurement phasor rk .

The field PSD of rk consists of a Lorentzian shape nearthe zero frequency caused by the Brownian phase noise, and aflat floor due to electrical noise covering elsewhere in the fieldPSD. This two-sided field PSD of white Gaussian noise can beexpressed as

No = σ2/BW2-sided (A.2)

where BW2−sided is the two-sided bandwidth of the spectrum,or the sampling rate of the ADC (real-time oscilloscope). Toobtain PN-PSD, assuming that there is no phase wrapping, wetake the angle of (A.1)

Arg(rk ) = Arg[(

ejθk + nk/A)]

= θk + εk (A.3)

where εk is the white phase noise. Applying geometric approachon complex plane for (A.1) shown in [37, Fig. 1], the exactprobability distribution function (pdf) of white phase noise εk

depends on measurement, showing a zero-mean Tikhonov dis-tribution with a variance of σ2 /(2|rk |A) [37], (18)]. For SNRlarger than 10 dB, the pdf can be approximated well by a zero-mean Gaussian distribution with a variance of σ2 /(2A2) [37],(17)], where the factor of 1

2 can be thought as the equal con-tribution of in-phase and quadrature-phase noise components.Thus, the phase-noise PSD for white phase noise is given byNo /(2A2).

In DSP, we obtain frequency noise by differencing two con-secutive phases [38, (2)], and the FN-PSD should have a sincsquared envelope [38], (4)], but its effect can only be observed athigh frequencies around the symbol rate. The frequency-noisePSD can be simply derived by multiplying f 2 of the phase-noisePSD [35], i.e.

SΔf ,AWGN (f)dB =[No

/(2A2)]

dB+ 20 log10 f (A.4)

which agrees with [36]. From (A.4), on the logarithmic FN-PSD, the slope of the f 2-curve does not change as shown inFig. 3 and Fig. 4. An increase in electrical noise only brings upthe f 2-curve.

B. Discrete Loop Equation for Parallel DD-MLE

In this section, the discrete loop equation for describing paral-lel DD-MLE is derived based on [18]. Assuming that the phasetracking is performed after perfect equalization and frequencyoffset compensation, the phasor estimate V [18, (3)] of parallel

DD-MLE in Fig. 5 is

V = |V | e−j θk −i + 1 =k−dP∑

m=k−(d+1)P +1

Cm

(A∗

m e−jθm + n∗m

)

(B.1)where |V | is the modulus of V, θk−i+1 is the phase estimateat time index k − i+1, i is the parallelization channel indextaking from 1 to P , the subscript m refers to time index, θm

is the true phase, Am is the complex transmitted QAM signal,nm is the AWGN as defined in Appendix A, Cm is the deci-sion symbol of QAM signals. Following the derivation in [18],(4)], assuming small phase tracking error, such that slicers givecorrect decisions, (B.1) becomes

|V | e−j θk −i + 1 = e−j θk −d P −i + 1

·k−dP∑

m=k−(d+1)P +1

|Am |2[e−j(θm −θm ) + n∗

1,m

](B.2)

where the noise term n∗1,m

Δ= n∗m ejθm /A∗

m is reduced by the

amplitude A∗m and rotated by the phase estimate θm . As for

each round of time interleaving, the phase estimate is commonto all P channels i.e. θk−(d+1)P +1 = · · · = θk−dP , θm can befactorized out from the summand, and we simply write it asθk−dP −i+1 . Then, we take the unwrapped argument on bothsides in (B.2) and apply the first-order Taylor-series expansiontwice, we obtain

θk−i+1 = θk−dP −i+1 +1

∑k−dPm=k−dP −P +1 |Am |2

×k−dP∑

m=k−dP −P +1

|Am |2(θm − θm

)

− 1∑k−dP

m=k−dP −P +1 |Am |2k−dP∑

m=k−dP −P +1

|Am |2 Im(n∗

1,m

)

(B.3)

for i = 1,. . ., P . Note that the above equation holds for all Pchannels during each round of time interleaving, as all channelsshare the same phase estimate. Both the second and the thirdterms of (B.3) refer to the increment of the discrete loop equationappearing in the second term of (3). The second term of (B.3)is the weighted sum of phase errors taken from k-dP-P+1 tok-dP, with the mth weight equal to the mth received symbolenergy. Similarly, the third term of (B.3) is the weighted sumof the imaginary part of n∗

1,m taken from k-dP-P+1 to k-dP(for high SNR [18]), with the mth weight equal to the mthreceived symbol energy. These two terms are scaled down bythe total symbol energy within the time duration from dP-P+1 tok-dP.

C. Reduction in Power Consumption due to Parallelization

This section reviews the reduction in power consumption ofCMOS circuits due to pipelining and parallelization [30, Ch. 3and 10], discussed in Sections III and IV. First, the power


consumption PCMOS of a CMOS circuit can be approximated by

PCMOS = CtotalV20 fclk (C.1)

where Ctotal is the total capacitance of the circuit, V0 is thesupply voltage, and fclk is the clock frequency of the circuit. It isassumed that the capacitance of multipliers, slicers and lookuptables dominates those of adders and pipelining registers.Second, the critical path (defined as the minimum time requiredfor processing the next new sample [30], Ch. 3]) is limited bythe propagation delay related to the charging and dischargingof the CMOS gate and stray capacitances. Thus, the minimumallowed clock period of the processor Tproc can be expressed as

Tproc =CchargeV0

k (V0 − Vt)2 (C.2)

where Vt is the CMOS threshold voltage, and k is a process pa-rameter depending on the material and geometry applied in theCMOS technology [39, Ch. 2], and Ccharge is the capacitance tobe charged or discharged in a single clock cycle. The intercon-nect capacitance usually dominates the CMOS gate capacitance,and appears as the major capacitances (e.g. multipliers) withina critical path. For a fair comparison of power consumption be-tween serial processing and parallel processing (with differentparallelization level P ), we assume that the parallel DD-PR ispipelined with an identical number of registers in each parallelrail as that of the serial pipelined DD-PR. Please note that fine-grain pipelining [30, p. 69] for multipliers or for lookup tablesand bit-level pipelining [30, p. 482] are not considered here.

For pipelining, the insertion of d pipelining registers reducesthe original physical distance within a critical path by d times(where d is the number of pipelining registers as defined inSection III). Thus, the charging capacitance is also reduced byd times because of the reduced coverage of interconnect on thegrounded substrate [30], Ch. 6], while the overall capacitanceof the circuit is not changed significantly by the addition ofpipelining registers. The charging-capacitance reduction allowsa faster transition (or a shorter rise-time because of a smallerRC constant), which equivalently reduces the supply voltagefrom V0 to βV0 (for β < 1) within a clock duration, and thepropagation delay Tpd,s,pip for pipelined serial processing is

Tpd,s,pip =Ccharge,pip (βV0)k (βV0 − Vt)

2 (C.3)

where Ccharge,pip is the charging capacitance after pipelining.For parallel and pipelined processing, the same serial

pipelined DD-PR is duplicated in parallel by P times, lead-ing to P -folded increase in the total capacitance in the circuit,while the charging capacitance of each parallel rail, and thusthe propagation delay Tpd,p,pip remains the same as that of theserial pipelined processing:

Tpd,p,pip = Tpd,s,pip =Ccharge,pip (βV0)k (βV0 − Vt)

2 (C.4)

since the processing rate of each parallel rail is P timesslower than the original processing rate. Using (C.2) and (C.4),

Tpd,p,pip becomes

Ccharge,pip (βV0)k (βV0 − Vt)

2 = PCchargeV0

k (V0 − Vt)2 (C.5)

By solving the quadratic equation in β in (C.5) and using(C.1), the power consumption for parallel and pipelined pro-cessing can be calculated as

PCMOS,p,pip =C ′

totalβ2

CtotalPPCMOS (C.6)

Taking V0 = 5 V, Vt = 0.6 V, d = 4, Ccharge,pip =Ccharge/d,C ′

charge = Ccharge×P , the power consumption forP = 16 and P = 20 are 2.71% and 2.54% of the original circuit,respectively, leading to a 6.3% reduction in power consump-tion for performing DD-PR when the parallelization level Pincreases from 16 to 20.

ACKNOWLEDGMENT

The authors would like to thank Q. Zhuge of McGill Univer-sity for his detailed explanation of his work [17].

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Wing-Chau Ng was born in Hong Kong, in 1984. He received the M.A.Sc.degree from the University of Toronto, Toronto, ON, Canada, working on wave-length conversion in semiconductor. He is currently working toward the Ph.D.degree at the Universite Laval, Quebec City, QC, Canada.

His current research area covers digital signal processing in coherentcommunications.

An T. Nguyen was born in 1982. He received the B.S. degree in physics, and theM.S. degree in electronics engineering from the University of Science—VietnamNational University (UoS – VNU), Ho Chi Minh City, Vietnam, in 2003 and2007, respectively. In 2011, he received the Ph.D. degree in optical telecom-munications from the Centro di Eccellenza per l’Ingegneria dell’Informazione,della Comunicazione e della Percezione, Scuola Superiore Sant’Anna, Pisa,Italy.

From 2003 to 2007, he was at VNU as a research assistant working on Wire-lessLAN and WirelessMAN physical layer, mainly on forward error coding,channel modeling, and channel estimation. His research topics involved ultra-fast (640Gbps and beyond) OTDM subsystems, multifunctional hybrid add/dropnode for OTDM and WDM integration, all-optical wavelength and modulationformat converter, ultrafast packet switching and photonic digital processing cir-cuits. Since 2011, he has been with the Centre d’Optique, Photonique et Laser,Universite Laval, Quebec, Canada. His projects focus on optical coherent de-tection systems with higher-order modulation formats, OFDM-over-fiber andfull-duplex wireless-fiber interfacing.

Simon Ayotte received the B.S. degree in physics engineering and the Ph.D.degree in electrical engineering from the Universite Laval, Quebec city, QC,Canada, in 2002 and 2007, respectively.

His graduate work focused on the optical sources interference noise in opticalcode division multiple access fiber optics telecommunication systems. In 2006and 2007, he spent nine months at Intel Corporation (Santa Clara, CA, USA)working in the Silicon Photonics group where he worked on a multi-channeloptical transmitter and also invented a new silicon dispersion compensator forfiber optics transmission. He joined TeraXion, Quebec city, QC, Canada, in2008, where he has been the Technical Leader on several projects involvingsimulation, design, and manufacturing of advanced laser systems.


Chul Soo Park (S’97–M’06) received the B.S. degree from Kwangwoon Uni-versity, Seoul, Korea, in 1997, and the M.S. and Ph.D. degree from the GwangjuInstitute of Science and Technology, Gwangju, Korea, in 1999, and 2006,respectively.

In 2005, he was a Part-time Research Staff in the Korea Photonics Tech-nology Institute, where he developed the visible light communication link andits related transceiver circuits using LEDs. From 2006 to 2012, he was a Re-search Staff Member at Institute for Infocomm Research, A∗STAR, Singapore,where he worked on microwave photonics system and hybrid optical access net-work. He is currently with the Center d’optique photonique et laser, UniversiteLaval, Quebec city, QC, Canada, as a Senior Researcher/Laboratory Manager.His current research interests include optical coherent detection system, siliconphotonics (device and system application), and microwave photonics encom-passing application of fiber-optic nonlinearity for photonic phased array antennasystem, reconfigurable radio-over-fiber, integrated network of wired and wire-less system for broadband service.

Dr. Park is a member of the IEEE Photonics Society. He served as an execu-tive committee member for IEEE Singapore Section during 2010 and 2011 andpublication chair for the international topical meeting on microwave photonics2011.

Leslie A. Rusch (S’91–M’94–SM’00–F’10) received the B.S.E.E. degree(Hons.) from the California Institute of Technology, Pasadena, CA, USA, in1980, and the M.A. and Ph.D. degrees in electrical engineering from PrincetonUniversity, Princeton, NJ, USA, in 1992 and 1994, respectively.

She has experience in defense, industrial, and academic communicationsresearch. She was a Communications Project Engineer for the Department ofDefense from 1980–1990. While on leave from Universite Laval, she spenttwo years (2001–2002) at Intel Corporation creating and managing a group re-searching new wireless technologies. She is currently a Professor in the Depart-ment of Electrical and Computer Engineering, Universite Laval, QC, Canada,performing research on wireless and optical communications. Her researchinterests include advanced optical networks exploiting all optical wavelengthconversion, analysis of phase noise in optical systems using coherent detection,semiconductor and erbium-doped optical amplifiers and their dynamics; andin wireless communications, optimization of the optical/wireless interface inemerging cloud based computing networks, optical pulse shaping for high-bitrate ultrawide-band systems, and implantable medical sensors with high bit rateUWB telemetry. She has published more than 90 journal articles in interna-tional journals (90% IEEE/IEE) with wide readership, and contributed to over100 conferences. Her journal articles have been cited over 1000 times per theScience Citation Index.

Dr. Rusch is currently an Associate Editor for the OSA/IEEE Journal ofOptical Communications and Networking. She has served as Associate Edi-tor for IEEE Communications Letters and on several IEEE technical programcommittees.

Documents

Overcoming Phase Sensitivity in Real-Time Parallel DSP for Optical Coherent Communications: Optically Filtered Lasers