On the Characterization and Efficient Computation of Hard-to-Detect Bridging Faults

1640 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 12, DECEMBER 2004

On the Characterization and Efficient Computation ofHard-to-Detect Bridging Faults

Irith Pomeranz, Fellow, IEEE, Sudhakar M. Reddy, Fellow, IEEE, and Sandip Kundu

Abstract—We investigate a characterization of hard-to-detectbridging faults. For circuits with large numbers of lines (or nodes),this characterization can be used to select target faults for test gen-eration efficiently, when it is impractical to target all the bridgingfaults (or all the realistic bridging faults). We demonstrate that thefaults selected based on the proposed characterization are indeedhard-to-detect by performing the following experiments. 1) Weshow that the fault coverage of a given test set, with respect tothe selected subset of bridging faults, is lower and more sensitiveto the test set than the fault coverage obtained with respect to arandom subset of bridging faults of the same size, with respectto the complete set of bridging faults, and when possible, withrespect to a subset of realistic bridging faults of the same size.2) We demonstrate that a test set generated for the selected subsetof bridging faults detects other bridging faults more effectivelythan when a test set is derived for a randomly selected subsetof bridging faults of the same size. We also describe an efficientprocedure for selecting hard-to-detect bridging faults accordingto the proposed characterization. This procedure avoids enumera-tion of all the faults in order to select the hard-to-detect ones. Thisis important for large circuits where even enumeration of all thebridging faults may not be feasible.

Index Terms—Bridging faults, fault selection, fault simulation,hard-to-detect faults, test generation.

I. INTRODUCTION

THE NUMBER of bridging faults in a circuit with lines(or nodes) is on the order of . Consequently, for large

circuits, only a subset of the bridging faults can be consideredin practice during test generation. In order to limit the numberof bridging faults targeted for test generation, a set of bridgingfaults called realistic bridging faults is selected in [1]–[3] basedon layout information. This selection procedure identifies faultsthat are most likely to occur taking into account that physicaldefects are more likely to bridge two lines if the lines are closer

Manuscript received May 10, 2003; revised November 20, 2003. The workof I. Pomeranz was supported in part by the National Science Foundation underGrant CCR-0098091 and in part by the Semiconductor Research Corporationunder Grant 2001-TJ-950. The work of S. M. Reddy was supported in part bythe National Science Foundation under Grant CCR-0097905 and in part by theSemiconductor Research Corporation under Grant 2001-TJ-949. This paper isbased on “On the Characterization of Hard-to-Detect Bridging Faults,” whichappeared in the Proceedings of the Design, Automation, and Test in Europe Con-ference, Mar. 2003, pp. 1012–1017. This paper was recommended by AssociateEditor S. Hellebrand.

I. Pomeranz is with the School of Electrical and Computer Engi-neering, Purdue University, West Lafayette, IN 47907 USA (e-mail:[email protected]).

S. M. Reddy is with the Electrical and Computer Engineering Department,University of Iowa, Iowa City, IA 52242 USA.

S. Kundu is with the Intel Corporation, Austin, TX 78746 USA.Digital Object Identifier 10.1109/TCAD.2004.837725

to each other. In large industrial designs, such methods typi-cally generate bridging fault lists that are an order of magnitude(or more) larger than the number of nodes in the circuit. Forthis reason, typically only a portion of these faults that have thehighest probability of occurrence are actually targeted for testgeneration. However, it has been observed that very high per-centages of these highest-probability faults are also easy-to-de-tect. Consequently, the effectiveness of the tests generated forthese targeted faults is low as they leave many untargeted faultsundetected.

A fundamentally different approach to the selection of asubset of bridging faults is to focus on hard-to-detect faults.As with other fault models, hard-to-detect faults are faultswith relatively few tests, which are not likely to be detected bytests for other faults. Moreover, tests for hard-to-detect faultsare more likely to detect a large number of other faults thantests for easy-to-detect faults. In this work, we consider a wayto characterize hard-to-detect bridging faults. The proposedcharacterization provides a ranking of the faults according totheir difficulty of detection. Based on this ranking, it is possibleto select a subset of faults of the desired size as targets for testgeneration. When layout information is available, the proposedranking can be used for selecting a subset of the realisticbridging faults that are the hardest-to-detect. When layoutinformation is not available and it is impractical to consider allthe bridging faults in the circuit, the proposed ranking providesa way to select a set of target faults whose tests detect otherfaults, which are not included in the selected subset.

The proposed characterization is done based on informationavailable from structural analysis of the circuit and from logicsimulation of a (small) subset of vectors. Thus, the computa-tional effort required for applying the proposed characterizationto a given set of bridging faults is low. We describe the charac-terization of bridging faults according to their difficulty of de-tection in Section II. We then report the results of three experi-ments to demonstrate the effectiveness of this characterization.

In Section III, we perform bridging fault simulation ofdifferent test sets to obtain fault coverages with respect to thefollowing subsets of faults: 1) the complete set of bridgingfaults; 2) a subset of bridging faults that are the hardest-to-de-tect according to the proposed characterization; 3) a randomlyselected subset of faults of the same size as that selected usingthe proposed characterization; and 4) a subset of realisticbridging faults of the same size when they are available. Thecomparison shows that the fault coverage with respect to the“hard-to-detect” faults is significantly lower than the other faultcoverages and more sensitive to the test set. Thus, the selectedfaults are indeed hard-to-detect.

0278-0070/04$20.00 © 2004 IEEE

POMERANZ et al.: CHARACTERIZATION AND EFFICIENT COMPUTATION OF HARD-TO-DETECT BRIDGING FAULTS 1641

In Sections IV and V, we compare the results of test gener-ation targeting subsets of hard-to-detect faults as measured bythe proposed characterization, and random fault subsets of thesame size. We compare test sets derived for fault subsets of thesame size by considering the fault coverage obtained with re-spect to the complete set of bridging faults. The results of theseexperiments show that complete coverage of all the detectablebridging faults is obtained for smaller subset sizes when sub-sets of hard-to-detect faults are used. This indicates that testsfor hard-to-detect faults based on the proposed characterizationare more effective at detecting other, untargeted faults.

In Section VI, we demonstrate that the computation ofhard-to-detect bridging faults can be done efficiently by per-forming the following experiment. We compute the difficultyof detection for all the bridging faults, select a subset ofhard-to-detect-faults, and perform test generation only forthe selected subset of hard-to-detect faults. We show that theoverall runtime for this process is significantly smaller than theruntime for test generation without fault selection, where all thebridging faults are targeted. We show this for the case where thesame bridging fault coverage is achieved in both experiments.

The computational effort required for applying the proposedcharacterization to a given set of bridging faults is low. The maincomputational bottleneck in applying the proposed characteri-zation results from the fact that in a large circuit the numberof bridging faults may be too large to enumerate the faults andcompute the difficulty of detection for each bridging fault in-dividually. To address this issue, we describe in Section VII aprocedure for selecting hard-to-detect bridging faults withoutenumerating all the bridging faults in the circuit.

We consider AND-type and OR-type bridging faults [4] as wellas four-way bridging faults [5], [6]. The four-way bridging faultmodel addresses at the gate-level the fact that the effects of abridging fault depend on the relative strengths of the drivingnodes and on the threshold voltages of the driven nodes [7].We experiment with AND-type and OR-type bridging faults inSections III, IV, and VII, and with four-way bridging faults inSections V and VI.

We use multilevel implementations of Berkeley PLAs [8] forexperiments with circuits that have small numbers of inputs,and the combinational logic of ISCAS’89 [9] and ITC’99 [10]benchmark circuits for experiments with circuits that have largernumbers of inputs.

The set of hard-to-detect bridging faults selected by the pro-posed method is influenced by the set of vectors used for faultcharacterization. We use different types and sizes of vector setsto perform the characterization. The vector set can be deter-mined by the user based on the availability of deterministic testvectors for stuck-at faults, runtime constraints, and the desiredaccuracy.

II. HARD-TO-DETECT BRIDGING FAULTS

In this section, we first describe the proposed characteriza-tion of hard-to-detect faults for AND-type and OR-type bridgingfaults. We then apply it to four-way bridging faults.

Fig. 1. Combinational logic of s27.

A. AND- and OR-Type Bridging Faults

An AND-type bridging fault between lines and is rep-resented as AND . An OR-type bridging fault betweenlines and is represented as OR .

The proposed characterization is based on two sets of valuesassociated with (single) lines in the circuit. The first set of valuesis obtained by logic simulation of a small set of input vectors,denoted by . The size of is denoted by . Duringthe logic simulation process of , we collect informationabout the values assigned to every line in the circuit. We denoteby the value of line under vector . These valuesare used as follows. For a test to detect a bridging fault asso-ciated with a pair of lines , it is necessary for to assign

and , or and . Using the valuescollected during logic simulation of , we can associate

with the pair the number of vectors such thatand , or and . The

lower this number, the more difficult it is to set and to dif-ferent values, and the faults associated with are likely tobe harder-to-detect.

To make the characterization more accurate, we compute forevery line a set of necessary assignments . A necessaryassignment of is a value that must be assigned to a line in thecircuit in order to propagate a change in the value of toward theprimary outputs. The set is similar to the set of necessaryassignments for a stuck-at fault on line , except that we donot associate a faulty value with line . To define the necessaryassignments for , we use structural analysis of the circuit. Weconsider the path from to the closest primary output or fanoutstem (whichever comes first). Every off-path input along thispath must have the noncontrolling value for a change in the valueof to propagate.

For illustration, we show in Fig. 1 the combinational logicof ISCAS’89 benchmark circuit . To propagate a changein the value of line 4, line 16 must be set to 0, line 18 mustbe set to 1, and line 5 must be set to 0. We obtain

, where in every pairis a line and is the value that must be assigned to in order topropagate a change in the value of .

We collect a set of necessary assignments for every linebefore we simulate the set of vectors . During the logic

simulation process of , we update a variable ac-cording to whether or not satisfies the necessary as-signments . We set if the necessary assign-ments of are satisfied by , and we set otherwise.The variables are used as follows. For a test to detect


a bridging fault associated with , it is necessary for toassign and , or and . At the sametime, must satisfy the necessary assignments for propagatinga change in the value either of or of .

Using and , we define a numberAND for an AND-type bridging fault and a numberOR for an OR-type bridging fault to capture the difficulty of de-tecting the fault, as follows.

The number AND is equal to the number of vectorssuch that 1) , and

(with these values, an AND-type bridging fault will change thevalue of from 1 to 0, and the necessary assignmentsrequired to ensure that the change in the value of propagatesare satisfied) or 2) , and(with these values, an AND-type bridging fault will change thevalue of from 1 to 0, and the necessary assignmentsrequired to ensure that the change in the value of propagatesare satisfied).

The number OR is equal to the number of vectors, such that: 1) , and

or 2) , and .The lower the value of AND or OR ,

the harder-to-detect the fault is expected to be. Thus, we canrank the faults according to their difficulty of detection using

AND , and OR . To select hard-to-detectfaults, we select the faults with the lowest values of .

B. Four-Way Bridging Faults

Under the four-way bridging fault model [5], [6], a pair oflines is associated with four faults corresponding to twopossible combinations of values (0, 1 and 1, 0) on , and twopossibilities for a line whose value may change in the presenceof a fault. The first fault is activated when , andit causes the value of to change from 0 to 1 (this fault is alsoreferred to as in [6]). The second fault is activatedwhen , and it causes the value of to changefrom 1 to 0 . The third fault is activated when

, and it causes the value of to change from 1 to 0. The fourth fault is activated when ,

and it causes the value of to change from 0 to 1 .To use the characterization of hard-to-detect faults based onfor four-way bridging faults, we extend the definition of as

follows. We denote by a bridging fault betweenlines and , which is activated on when and

. The number is equal to the numberof vectors such that and

. Again, allows a ranking of the faults accordingto their difficulty of detection. A lower value ofindicates that the fault is harder-to-detect.

III. VALIDATION THROUGH FAULT SIMULATION

In this section, we report the results of an experiment wherewe fault simulate various test sets using different subsetsof AND- and OR-type bridging faults, one of them includinghardest-to-detect faults according to the characterization de-fined in the previous section. The results indicate that thesefaults are indeed hard-to-detect.

TABLE IPARAMETERS OF SIMULATED FAULTS AND TESTS (COMPACT TEST SETS)

We simulate the following subsets of faults:

1) the set of all the nonfeedback AND- and OR-typebridging faults between every pair of lines that are notfanout branches or inputs of the same gate.

2) a subset consisting of approximately 1% of thefaults in that have the lowest values of AND

and OR . The subset is defined as follows.Initially, . For , we addto every fault AND withAND and every fault OR with

OR . The value of is determined suchthat it is the first value of for which the size ofreaches or exceeds 1% of the number of faults in .

3) a subset of the same size as , where the faultsare selected randomly out of .

4) a subset of the same size as that includesthe faults identified as most likely to occur by a realisticbridging fault extraction tool [1]. We consider only non-feedback bridging faults provided by the extraction toolin order to be consistent with the selection of and

. We consider only several of the circuits, for whichsets are available to us.

We simulate the following two types of test sets:

1) compact deterministic test sets for single stuck-at faultsfrom [11].

2) random test sets of the same size as the compact deter-ministic test sets.

We also simulated noncompact deterministic test sets forsingle stuck-at faults in order to verify that similar results areobtained with larger test sets that detect more bridging faults.We omit the results due to their similarity to the results usingcompact test sets.

We use random vectors for the set tocompute the detection difficulty measures AND and

OR . The results for compact deterministic test sets andrandom test sets of the same size are shown in Tables I and II,as follows.

In Table I, after the circuit name, we show the total numberof faults in and the number of faults in the selected subsets

and . We then show the average value ofcomputed over all the faults in , over the faults in ,


TABLE IIFAULT COVERAGES (COMPACT TEST SETS)

over the faults in , and over the faults in . The averagevalue of for a subset of faults is computed as

In the last column of Table I, we show the number of testssimulated.

In Table II, after the circuit name, we show the fault cover-ages obtained by simulating the deterministic single stuck-attest sets from [11] under the sets of faults ,and . We then show the fault coverages obtained by sim-ulating random test sets of the same size under the sets of faults

, and .From Table I, it can be seen that the average value of for

faults in is significantly lower than the average value offor faults in or . From Table II, it can be seen

that the fault coverages computed with respect to the subset ofhard-to-detect faults are significantly lower than the faultcoverages computed with respect to , or . In ad-dition, the fault coverage computed over the faults in ismore sensitive to the test set being simulated. With random testsets, the fault coverage over is significantly lower than thefault coverage obtained by deterministic test sets. The differencein fault coverage between the two test sets is significantly lowerwhen considering the randomly selected set , the realisticset or the set of all the faults .

It is important to note that if fault sampling is done for thepurpose of fault simulation, provides a better approxima-tion of the actual fault coverage; however, when the goal is toselect a subset of target faults for test generation, the faults in

are more difficult to detect and thus should be targetedexplicitly.

Information not provided by this experiment is the extent towhich the subset of hard-to-detect faults includes undetectablefaults. We address this issue in the following section.

IV. VALIDATION THROUGH TEST SELECTION USING

HARD-TO-DETECT FAULTS

In this section, we describe the results of an experiment wherewe derive compact test sets for subsets of hard-to-detect faultsof increasing sizes. For comparison, we also obtain compact test

sets for randomly selected subsets of faults of the same sizes.We compare the fault coverage achieved by the two types of testsets with respect to the complete set of faults. This experimentprovides an indication of the relative ability of tests for hard-to-detect faults to detect other faults.

To remove as much as possible the effects of test generationheuristics on the comparison, we consider in this section circuitswith small numbers of inputs. For a given subset of faults , wederive a compact test set by using a greedy covering procedurethat selects tests out of the set of all possible input vectors ofthe circuit. The greedy heuristic first selects a yet-undetectedfault in that has the smallest number of tests. Out of the testsfor the selected fault, it selects the test that detects the largestnumber of yet-undetected faults in .

The subsets of hard-to-detect faults are determined as fol-lows. For if there is at least one fault withAND or OR , we define a subset of faults

that consists of every fault with AND orOR . We denote the resulting subsets of faults

.We also define subsets of the same sizes consisting of

randomly selected faults. We denote the random subsets by, respectively. We have for

.We are interested in the first subset (or ) for which

the compact test set detects all the detectable bridging faults inthe circuit (i.e., the test set achieves 100% fault efficiency withrespect to the set of all the bridging faults). However, weobserved that, especially with random selection of target faults,the fault coverage with respect to may decrease when thesize of the fault subset is increased. To remove this effect, wecaptured the first subset size after which 100% fault efficiencywas obtained for all the larger subsets considered. We denotethis subset by % for the proposed selection criterion, andby % for randomly selected faults. We userandom vectors for the characterization of hard-to-detect faults.

The results of this experiment are shown in Table III. InTable III, after the circuit name, we show the total number offaults and the number of undetectable faults. We then show theproportion of faults included in %, and in %. Undercolumn tests we show the number of tests included in the testset selected for %, and in the test set selected for %.

From Table III, it can be seen that by using the proposedcharacterization, all the selected as well as unselected detectablefaults are detected, on the average, after only 0.585 of the faultsare targeted. For random selection of faults, this happens after0.981 of the faults are targeted. We refer to faults as hard-to-de-tect when they need to be targeted in order to be detected, whilefaults that can be detected by tests for other faults are easy-to-de-tect. With this terminology, the proposed method is able to iden-tify hard-to-detect faults more accurately than a random selec-tion and it detects many of the easy-to-detect faults without tar-geting them. The test set sizes are approximately the same when100% fault efficiency is reached for both fault subsets.

For the circuits considered in Table III, information about un-detectable faults and the values of associated with them isgiven in Table IV. After the circuit name, we show the totalnumber of faults and the number of undetectable faults. We then


TABLE IIIACHIEVING 100% FAULT EFFICIENCY

TABLE IVUNDETECTABLE FAULTS

consider the first three values of . For every value of, we show the total number of faults with AND or

, and the number of undetectable faults withthis value of . Table IV shows that many (but not all) of the un-detectable faults have . In addition, not all the faults with

are undetectable. Thus, it is important to include faultswith in the set of faults targeted for test generation.

V. VALIDATION THROUGH DYNAMIC TEST COMPACTION

In the experiment reported next, we use a dynamic test-com-paction procedure (i.e., a test-generation procedure withdynamic compaction heuristics) for bridging faults to furtherdemonstrate the effectiveness of targeting hard-to-detect faults.

The dynamic test-compaction procedure we use considersthe four-way bridging fault model from [5] and [6]. A subsetof bridging faults was originally selected as part of this com-paction procedure such that for every pair of lines used fordefining four faults, the difference between the indicesdoes not exceed a preselected constant. We denote the subset ofbridging faults selected in this way by (since it is based online indices). We set the maximum value of such that ap-proximately 10% of the circuit faults are included in .

Using the proposed characterization of hard-to-detect faults,we then replace the subset with a subset of faultsof the same size. We compare the results of the dynamic com-paction procedure when applied to and when applied to

TABLE VRESULTS OF DYNAMIC TEST COMPACTION

by considering two parameters: 1) the average value offor the selected faults and 2) the percentage of faults detectedout of the set of all the four-way bridging faults when thetest set is generated for and for . Additional detailsof this experiment are given next.

The dynamic test compaction procedure starts from a givendeterministic test set for single stuck-at faults, and it adds a min-imal number of tests to this test set in order to detect bridgingfaults. We use the stuck-at test set as the set for identifyinghard-to-detect faults.

For the set , we consider nonfeedback four-way bridgingfaults between every pair of lines that are outputs of multi-inputgates and are not inputs of the same gate. For the larger circuits( and larger), considering the set of all the bridging faults

is not practical because of its size. We, therefore, restrict theset to include bridging faults involving lines such that

for that results in close to one million bridgingfaults. Both and are contained in .

The results of this experiment are shown in Tables V and VI,as follows.

In Table V, after the circuit name, we show the total numberof four-way bridging faults (the number of faults in ) and thenumber of faults targeted by the dynamic compaction procedure(the number of faults in and ). Under column ind, weshow the average value of for the faults in , and the faultcoverage with respect to . Under column hard we show thesame information when dynamic test compaction is performedfor the set of faults . The values of that result in fewerthan one million bridging faults in the larger circuits are givenbelow Table V.

In Table VI, we show the fault coverage, with respect to ,of the test sets obtained when and when are targetedby the dynamic test compaction procedure.

Table VI shows that when the set of all the four-waybridging faults is simulated, the tests generated for detectlarger percentages of the faults than tests generated for .Since many of the faults in are easy-to-detect, the differ-ences in fault coverage are not large, but the fault coverages areconsistently higher when using the proposed subset of hard-to-detect faults.


TABLE VIFAULT COVERAGES FOR DYNAMIC TEST COMPACTION

VI. EFFECT ON TEST GENERATION TIME

In this section, we consider the effect of identifying hard-to-detect bridging faults on the test-generation time.

We use the dynamic test compaction procedure used inSection V in three experiments. In the first experiment, werun the procedure to generate tests for the set of all thefour-way bridging faults without applying any fault selection.We obtain a fault coverage denoted by . In the secondexperiment, we select a subset of hard-to-detect faultssuch that a test set for achieves the fault coverage .We include in increasing percentages of the hard-to-de-tect faults of until the fault coverage target is achieved. Inthis way, we can compare the test generation time when thesame fault coverage is reached. In practice, a limited numberof hard-to-detect faults may be selected to further reduce thetest generation time. In the third experiment, we perform testgeneration for a set of hard-to-detect faults whose sizeis approximately half the size of . The results for severalcircuits are shown in Table VII as follows.

Under column all we show the results of test generation for allthe four-way bridging faults. The results include the number offaults, the number of tests generated, the fault coverage ,and the runtime in seconds on a Sun B2000 workstation.

Under column hard1, we show the results of test generationfor the set of hard-to-detect faults hard1. The results for thiscase include the number of selected faults, the number of testsgenerated, and the runtime on a Sun B2000 workstation. Thenumber of selected faults is such that the fault coverage is equalto . The runtime includes the time to select hard-to-detectbridging faults and the runtime for test generation.

Under column hard2, we show the results of test generationfor the set of hard-to-detect faults . The results for thiscase include the number of selected faults, the number of testsgenerated, the fault coverage with respect to , and the run-time on a Sun B2000 workstation.

From Table VII, it can be seen that for the same fault cov-erage, the selection of hard-to-detect faults reduces the overalltest-generation time by a factor of two or more. By further re-stricting the number of selected hard-to-detect faults, it is pos-sible to reduce the test generation time even further. In practice,the number of selected hard-to-detect bridging faults can be de-termined based on the test generation time that can be expended.

The set of selected faults can also be increased dynamically untila limit on runtime is reached or no additional bridging faults aredetected.

VII. EFFICIENT COMPUTATION OF HARD-TO-DETECT FAULTS

In this section, we describe a procedure for computing a set ofhard-to-detect bridging faults without explicitly computing forevery fault , where AND, OR . We first describethe basic approach and demonstrate it through an example. Wethen discuss sources of inaccuracy in the resulting procedureand how they can be overcome. Finally, we present experimentalresults.

A. Basic Approach

The basic idea behind the proposed procedure is to partitionthe circuit lines into subsets based on which we can findfaults that have for AND,OR .This will allow us to find many of the hardest-to-detect faults(the faults with the lowest values of ). We satisfy the condition

by defining a subset in one of two ways.

1) All the lines in assume the same values under all thevectors in . With for ,the contribution of to is zero. Therefore, forevery for AND,OR . Itis interesting to note that this condition was used earlier todetermine bridging faults that are not detected by a giventest set under IDDQ testing [12].

2) For every line , the necessary assignments arenever satisfied by any vector in . With

, the contribution of to iszero. Therefore, for every ,for AND,OR .

It is important to note that the conditions above are sufficient(but not necessary) for obtaining . It is alsopossible to obtain when (or

) for every vector such that.

Suppose that we obtain subsets of lines suchthat each subset satisfies one of the conditions above. Wedefine a set of candidate hard-to-detect bridging faults asfollows. AND OR

.When do not provide the desired number

of candidate bridging faults in , weinto two or more subsets , and we com-pute subsets with respect to every subset

. We then define as above for every ,and . The motivation for the parti-tioning of is as follows. For , we obtain larger sets

than for . Therefore, contains morecandidate faults than . In order not to lose information byconsidering , instead of , we find candidate faultsbased on such that . Weexpect to find hard-to-detect faults with respect to by usingthe hard-to-detect faults with respect to for .For the faults in we compute the accurate values of , andselect the required number of hardest-to-detect faults.


TABLE VIIEFFECT ON TEST-GENERATION TIME

TABLE VIIIV FOR s27

B. Example

We demonstrate the computation of hard-to-detect faults byconsidering the combinational logic of ISCAS’89 benchmarkcircuit shown in Fig. 1 under a set that consists offive random vectors. In Table VIII, we show for every vector

the set of lines that assume the value 0 under ,the set of lines that assume the value 1 under , and the setof lines whose necessary assignments are not satisfied under

. We omit fanout branches since we do not define bridgingfaults involving fanout branches [4].

We use the subsets and to compute subsets of linesthat assume equal values under all the vectors in as fol-lows. Initially, we define . We then con-sider each vector . When is considered, we havesubsets of lines computed based on .We compute and for , andkeep only the subsets that contain at least two lines. For , weobtain , and . In ad-dition, we use the sets to compute a set of lines whosenecessary assignments are not satisfied by any vector in .We obtain .

We use , andto define bridging faults that are guaranteed to have

. However, all the bridging faults we can define based on, and are feedback bridging faults. In addition, since

contains a single line, no bridging faults are defined basedon . Consequently, no bridging faults are defined in this case.

To increase the number of candidate hard-to-detect bridgingfaults, we partition into two (or more) subsets ofapproximately equal size. We consider again, thistime after partitioning into and

. For , we obtain the followingsubsets of lines that assume the same values under and :

,

and . From , and , weobtain a total of 26 candidate bridging faults ( does notcontribute any candidate faults). In addition, we obtain from

the set of lineswhose necessary assignments are not satisfied by any vector in

. After adding bridging faults involving these lines, wehave 34 candidate faults.

After performing the same analysis based on we have40 candidate bridging faults. To select a subset of these faults,we compute for every candidate fault and select the faults withthe lowest values of . We point out that has 126 bridgingfaults, and that 40 hard-to-detect faults were identified withoutenumerating all 126 faults. In addition, it is important to notethat we select bridging faults for which with respect to atleast one subset of vectors . Considering the complete set

, the value of for a candidate bridging fault may be largerthan zero. For with , the values of for the candidatefaults are zero or one.

In general, we partition into subsets untilthe number of candidate bridging faults obtained for a partitioninto subsets is large enough to allow us to select the desirednumber of hard-to-detect bridging faults. To partition into

subsets, we include either or con-secutive vectors of in every subset so as to obtain subsetsof approximately equal sizes.

C. Accuracy

In the proposed selection process, we include in faultsthat are guaranteed to have with respect to at least onesubset of vectors . Thus, the faults are hard-to-detect withrespect to a subset of , and they are likely to be hard-to-detect with respect to .

A selected fault may have with respect to[an example is the fault (15, 20, OR) of ]. Our expectation isthat faults in would have small values of , and would thusbe hard-to-detect with respect to . If they are not hard-to-detect with respect to , they would not be selected when theaccurate values of are computed for the faults in . Thus,there is no loss of accuracy by including such faults in .

A loss of accuracy may occur when a fault hasa small value of , yet and are not included inthe same subset of lines for any and . This can happenwhen is obtained for at least one vector under


every ; and or for at leastone vector under every ; however, all or most of thevectors that set also have [or

]. In this case, the fault will not beincluded in and will not be selected even though it isharder-to-detect than selected faults [an example is the fault (1,4, AND) of ]. In the following section, we will verify thatthis inaccuracy does not significantly affect our ability to selecthard-to-detect faults.

The accuracy of the selection procedure can be improved byconsidering additional (possibly overlapping) subsets of .By increasing the number of subsets we increase the number ofhard-to-detect faults for which and are likelyto be included in the same subset for some and . This in-creases the likelihood that the fault would be included inand selected as a hard-to-detect fault. We do not consider thisoption here.

It is important to consider the case where the unpartitionedprovides a sufficient number of candidate hard-to-detect

faults. In this case, the candidate hard-to-detect faults selectedby the proposed procedure are guaranteed to have withrespect to . Thus, they are the hardest-to-detect faults withrespect to . The inaccuracy in this case occurs only becausewe may not select all the hardest-to-detect faults. However, thecircuits for which does not need to be partitioned typicallyalso have large numbers of faults with . The proposed pro-cedure naturally selects a subset of the hardest-to-detect faultsin this case.

D. Validation Through Fault Simulation

We report the results of two fault-simulation experiments inthis section. In the first experiment, we verify the accuracy ofthe efficient selection process by comparing its results to theresults of the selection process used in Section III, where iscomputed for every bridging fault. For this purpose, we repeatthe experiment reported in Tables I and II using faults selectedby the efficient selection process. In the second experiment, weapply only the efficient selection process (without enumeratingall the bridging faults as required in Section III) and compare itto random selection of faults. This is applicable to circuits withlarge numbers of faults where enumeration of all the faults isnot practical.

The results of the first experiment are reported in Tables IXand X. The tables are arranged similar to Tables I and II, withthe following additions.

In Table IX, under column candidates, we show the numberof subsets into which is partitioned by the proposed pro-cedure in order to select hard-to-detect faults, and the numberof candidate faults obtained. Under columns marked e.hard inTables IX and X we show the results obtained when hard-to-de-tect faults are selected using the efficient procedure.

From Table IX, it can be seen that the number of candidatebridging faults considered by the efficient procedure is an orderof magnitude smaller than the number of all the bridging faults.The number of candidate hard-to-detect faults is only slightlyhigher than the number of faults actually selected.

TABLE IXPARAMETERS FOR EXPERIMENT 1

TABLE XFAULT COVERAGES FOR EXPERIMENT 1

The average value of for the hard-to-detect faults computedby the efficient procedure is higher than that computed by ex-plicitly considering all the bridging faults. This is due to the factthat we may miss some of the hard-to-detect faults. However,both values are significantly smaller than the average value ofobtained by selecting a random set of faults of the same size, orby considering all the bridging faults.

A similar conclusion applies when comparing the fault cov-erage with respect to the various subsets of faults in Table X. Al-though the fault coverage with respect to the subset of hard-to-detect faults computed by the efficient procedure is higher thanwhen all the bridging faults are considered explicitly (indicatingthat some easier-to-detect faults are selected), both fault cover-ages are lower than the fault coverages obtained for a randomlyselected subset of faults, or with respect to all the bridging faults.

For the second experiment, we apply only the efficientfault-selection procedure (without enumerating all the faults).We partition into subsets to ensure that containsat least of the circuit faults, for values of definedbelow. We then enumerate only the faults in , and selectapproximately of these faults. In the selection process, weselect all the enumerated faults with until thefirst value of for which at least of the circuit faults areselected. For comparison, we also select the same number offaults randomly.


TABLE XIPARAMETERS FOR EXPERIMENT 2

The values of are determined as follows. For the experi-ment reported in Tables IX and X, we considered approximately1% of the circuit faults in order to be consistent with the resultsof Tables I and II. Since the circuits considered for these ex-periments had relatively small numbers of faults to select from,selecting 1% of the faults yielded reasonable numbers of targetfaults. For circuits with very large numbers of faults (e.g.,has 8.75 M faults, and has 33.35 M faults), a set con-taining 1% of the faults may be too large to target. Thus, for thesecond experiment, we use , where is the number oflines in the circuit. We always select all the faults with the samevalue of . Thus, we may sometimes select more than faults.

We also made the following change compared to the exper-iments reported in Tables I, II, IX, and X. In the earlier exper-iments, consisted of 100 random vectors. For the largercircuits we consider in the second experiment, 100 random vec-tors are typically too few to see large variations in the value offor the various faults. It is possible to use a larger random set, ora deterministic stuck-at test set. We use the second alternativeand replace by a deterministic stuck-at test set. This is rea-sonable since test generation for bridging faults can be speededup by starting the process from a stuck-at test set, which canalso be used for selecting target hard-to-detect bridging faultswithout simulating the complete set of bridging faults under thetest set.

For our fault-simulation experiments, we prefer to ensure thatthe test set we simulate is different from the test set based onwhich faults are selected. Therefore, we use uncompacted singlestuck-at test sets for the selection of hard-to-detect faults inISCAS’89 benchmark circuits, and compacted single stuck-attest sets for bridging fault simulation.

We also consider ITC’99 benchmark circuits. For these cir-cuits, stuck-at test sets are selected out of a large set of random

TABLE XIIFAULT COVERAGES FOR EXPERIMENT 2

vectors and compacted by reverse order fault simulation. We usetwo different selections of random vectors to create two stuck-attest sets, one used for the selection of hard-to-detect faults, andone used for performing fault simulation of the selected bridgingfaults. The results are reported in Tables XI and XII.

In Table XI, after the circuit name, we show the total numberof bridging faults and the number of faults in the selected sub-sets. Under column candidates, we show the number of vectorsin , the number of subsets into which is partitioned inorder to select hard-to-detect faults, and the number of candidatefaults obtained. We then show the average value of computedover all the faults selected by the proposed procedure, and theaverage value of computed over the randomly selected faults.

In Table XII we show the fault coverage obtained by simu-lating a stuck-at test set under the hard-to-detect faults selectedby the proposed procedure, and under the randomly selectedfaults.

The results of Tables XI and XII support the conclusionthat the proposed selection procedure can select hard-to-detectfaults in circuits with very large numbers of faults. In addition,it can be seen that for some of the largest circuits considered( , and ), no partitioning ofis required and the selected faults all have . This indicatesthat they are the hardest-to-detect, and no harder-to-detect faultremains unselected.

VIII. CONCLUDING REMARKS

We proposed an efficient characterization of hard-to-detectbridging faults based on the results of logic simulation of a smallset of vectors, and on necessary assignments for propagation ofchanges of single line values in the circuit. For a fault charac-terized as hard-to-detect, only a small number of vectors assign


different values to the fault sites and satisfy the necessary as-signments for propagating a change from the fault site whosevalue will change in the presence of the fault. For circuits withlarge numbers of lines, this characterization can be used to selecttarget faults for test generation when it is impractical to targetall the faults (or all the realistic faults).

We demonstrated that the faults selected by the proposedcharacterization are indeed hard-to-detect by showing that thefault coverage with respect to this subset is lower than the faultcoverage obtained with respect to a random subset of the samesize, and with respect to the complete set of faults. We con-sidered realistic bridging faults when possible. We simulateddeterministic single stuck-at test sets as well as random test setsin order to demonstrate this point.

We also demonstrated that a test set for the selected faultsdetects other, unselected faults more effectively than when a testset is derived for a randomly selected subset of faults of the samesize. The selection of hard-to-detect faults was shown to reducethe overall test generation time significantly compared to thecase where all the bridging faults are targeted.

For circuits with large numbers of lines, where enumerationof all the bridging faults is not feasible, we described a pro-cedure for enumerating hard-to-detect bridging faults withoutenumerating all the bridging faults in the circuit. This procedurehas two steps. In the first step, a set of candidate hard-to-detectbridging faults is enumerated. In the second step, the measureof difficulty of detection is computed for the enumerated faults,and a subset consisting of the hardest-to-detect enumeratedfaults is selected. We presented experimental results to demon-strate the effectiveness of the efficient selection procedure.

ACKNOWLEDGMENT

The authors thank the reviewers for their detailed commentsand constructive suggestions.

REFERENCES

[1] F. J. Ferguson and J. P. Shen, “A CMOS fault extractor for inductive faultanalysis,” IEEE Trans. Computer-Aided Design, vol. 7, pp. 1181–1194,Nov. 1988.

[2] S. T. Zachariah and S. Chakravarty, “A scalable and efficient method-ology to extract two node bridges from large industrial circuits,” in Proc.Int. Test Conf., Oct. 2000, pp. 750–759.

[3] Z. Stanojevic and D. M. H. Walker, “FedEx—A fast bridging fault ex-tractor,” in Proc. Int. Test Conf., Oct. 2001, pp. 696–703.

[4] M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital SystemsTesting Testable Design. Rockville, MD: Computer Science, 1990.

[5] S. Sengupta et al., “Defect-based tests: A key enabler for successful mi-gration to structural test,” Intel Technol. J., vol. Q.1, 1999.

[6] V. Krishnaswamy, A. B. Ma, and P. Vishakantaiah, “A study of bridgingdefect probabilities on a pentium (TM) 4 CPU,” in Proc. Int. Test Conf.,2001, pp. 688–695.

[7] P. C. Maxwell and R. C. Aitken, “Biased voting: A method for simulatingCMOS bridging faults in the presence of variable gate logic thresholds,”in Proc. Int. Test Conf., Oct. 1993, pp. 63–72.

[8] R. K. Brayton, G. D. Hachtel, C. T. McMullen, and A. L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis. Nor-well, MA: Kluwer, 1984.

[9] F. Brglez, D. Bryan, and K. Kozminski, “Combinational profiles of se-quential benchmark circuits,” in Proc. Int. Symp. Circuits Syst., May1989, pp. 1929–1934.

[10] ITC99 Benchmark Home Page, http://www.cerc.utexas.edu/itc99-benchmarks/bench.html.

[11] S. Kajihara, I. Pomeranz, K. Kinoshita, and S. M. Reddy, “Cost-effectivegeneration of minimal test sets for stuck-at faults in combinational logiccircuits,” IEEE Trans. Computer-Aided Design, vol. 14, pp. 1496–1504,Dec. 1995.

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Irith Pomeranz (M’89–SM’96–F’99) received theB.Sc. degree (summa cum laude) in computer engi-neering and the D.Sc. degree in electrical engineeringfrom the Technion—Israel Institute of Technology,Haifa, Israel, in 1985 and 1989, respectively.

From 1989 to 1990, she was a Lecturer in the De-partment of Computer Science, Technion. From 1990to 2000, she was a faculty member in the Departmentof Electrical and Computer Engineering, Universityof Iowa. In 2000, she joined the School of Electricaland Computer Engineering, Purdue University, West

Lafayette, IN, where she is currently a Professor. Her research interests includetesting of VLSI circuits, design for testability, synthesis, and design verification.

Prof. Pomeranz was a recipient of the National Science Foundation YoungInvestigator Award in 1993, and of the University of Iowa Faculty ScholarAward in 1997. She serves as an Associate Editor of the ACM Transactionson Design Automation and as an Associate Editor of the IEEE TRANSACTIONS

ON COMPUTERS. She served as Guest Editor of the IEEE TRANSACTIONS

ON COMPUTERS, January 1998 special issue on Dependability of ComputingSystems, and as Program Co-chair of the 1999 Fault-Tolerant ComputingSymposium. She served as Program Chair of the 2004 VLSI Test Symposium.

Sudhakar M. Reddy (S’68–M’68–SM’84–F’87)received the undergraduate degree in electricaland communication engineering from OsmaniaUniversity, Hyderabad, India, the M.S. degree fromthe Indian Institute of Science, Bangalore, India, andthe Ph.D. degree in electrical engineering from theUniversity of Iowa, Iowa City.

Since 1968, he has been a member of the facultyof the Department of Electrical and Computer Engi-neering, University of Iowa, where he is currently aProfessor. He has been active in the areas of testable

designs and test generation for logic circuits since 1972.Prof. Reddy is a Member of Tau Beta Pi, Eta Kappa Nu, and Sigma Xi. He has

been an Associate Editor and twice a Guest Editor of the IEEE TRANSACTIONS

ON COMPUTERS. He is an Associate Editor of the IEEE TRANSACTIONS ON

COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. In 1990,he was made a University of Iowa Foundation Distinguished Professor.

Sandip Kundu received the B.Tech (Hons) degreein electronics and electrical communication engi-neering from the Indian Institute of Technology(IIT), Kharagpur, India, in 1984, and the Ph.D.degree from the University of Iowa, Iowa City, in1988.

He is a Principal Engineer and Manager of theCircuit Marginality Test Group, Intel Corporation,Austin, TX. He has published more than 50 papers indiverse areas, including very large scale integrationdesign, testing, computer-aided design (CAD), and

coding and information theory. He holds several patents and has delivered tentutorials at conferences.

Dr. Kundu has served on the program committees of all major CAD con-ferences, including the Design Automation Conference, the International Con-ference on Computer-Aided Design, and the Design, Automation, and Test inEurope Conference. He was the Technical Program Chair of the InternationalConference on Computer Design in 2000 and was its General Chair in 2001.He is the General Chair for the 2005 Very Large Scale Integration Conferenceto be held in India. He currently serves as an Associate Editor of the IEEETRANSACTIONS ON COMPUTERS.

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On the Characterization and Efficient Computation of Hard-to-Detect Bridging Faults