On Multiple Path Propagating Tests for Path Delay Faults

On Multiple Path Propagating Tests for Path Delay Faults *

Ankan K . Pramanick Data Systems Division

IBM Corporation Kingston, NY - 1240 1

ABSTRACT The path delay fault model is arguably the strongest

model for real delay defects in circuits. The recent availability of fully path delay f u l t testable designs has made it feasible to consider the problem of making test application for path delay faults more efficient by reducing the sizes of the potentially large test-sets required to obtain satisfactory coverages. This paper presents, for the first time, a heuristic-driven test generation procedure for obtaining maximal multiple-path-propagating robust tests, which detect the largest possible number of path faults simultaneously. Extensive experimental results are presented to demonstrate the efficacy of this approach, which is seen to significantly reduce test-set lengths for path delay faults by generating highly efficient robust tests.

I. Introduction Ascertaining correct operation of digital logic cir-

cuits requires verification of functional behavior as well as correct operation at desired clock rates. Failures causing logic circuits to malfunction at desired clock rates, or not meet timing specifications, are currently receiving much attention. Such failures are modeled by what are called delay faults. The objective of delay testing is to guarantee that the circuit operates without any malfunction at the specified clock rate. Two types of delay fault models are in use [l - 13, 16 - 251. The Gate Delay Fault model [l. 3 - 6, 21 - 261 assumes that a delay fault is “lumped” at a fuulty gate. This model thus inherently considers only single, isolated failures. Path Delay Faults [2, 6 - 13, 16 - 201, on the other hand, model distributed failures caused by statistical process variations, imprecise modeling, etc., as well as isolated failures.

Both models have certain advantages, and also suffer from certain inadequacies. Though the path dt9lay fault model is stronger in the sense that it models both isolated and distributed failures, and hence supports the consideration of multiple delay faults, as well as effectively models defects in designs created with the increasingly popular statistical design philosophy [2, 71, its biggest single drawback is that the paths in practical circuits may be

* Research reported was supported in part by SDIO/IST Contract No. N00014-90-J-1793, managed by the US Office of Naval Research.

7 Work done while the author was with the Dept. of Electrical & Computer Engg. at The University of Iowa.

Sudhakar M . Reddy Dept. of Electrical & Computer Engg.

The University of Iowa Iowa City, IA -. 52242

too numerous for explicit consideration of all of them. Traditionally, advocates of this strong model have proposed testing for a “carefully chosen” subset of all possible paths in the circuits, as for example, the set of the most critical (longest delay) paths in the circuit [2, 6, 7, 9, 101, for the occurrence of path delay faults. However, even if all such paths pass the tests, there is no guarantee that delay failures along some of the untested paths will never cause a circuit malfunction.

Since the number of leads in practical circuits are often not as inordinately large as the number of paths in such circuits, testing for all possible gate delay faults is more reasonably accomplished. However, this is a weaker model in the sense that it supports only single delay faults, and does not take care of distributed failures. Moreover, it is not only sufficient to find a test T for a gate delay fault: one has to also accurately specify the size of the fault detected by T [21 - 261, which is essential to finally being able to say whether the tested circuit will actually work without malfunctions in practice. As has been reported in [25, 261, such computations of detected fault sizes either have certain deficiencies [21, 23, 241, or are quite conipli- cated [25], or often, in order to ultimately provide complete fault coverages, would require alternate test application strategies and very sophisticated test hardware in practice [26].

As is evident from the above discussion, path delay faults model real delay defects (in today’s statistical design-based high performance digital circuits) arguably better than gate delay faults do, but have the disadvantage of requiring a potentially very large test set length to achieve complete fault coverage. However, a very important class of tests, Robust Tests [6, 91, are capable of detecting delay defects in multiple paths at the same time. The most attractive property of robust tests is that they cannot be invalidated in the presence of arbitrary delays, and test paths independent of delays in the rest of the circuit. This, coupled with the faci that robust tests are capable of testing several paths at once, shows that general robust tests [Is] are prime candidates for potentially efficient test sets for path delay faults, which can tackle the problem of having to test for very large numbers of paths.

Until recently, it had been seen [lo - 121 that robust tests unfortunately often did not exist for large numbers of paths in practical circuits. However, since these reports, a significant amount of research has focussed on design for testability for path delay faults E13, 16 - 201. Most of these methods were geared to the design or synthesis of circuits that are fully testable for path delay faults by robust tests.

INTERNATOONAL TEST CONFERENCE 1991 CH3O32-0/91 /OOOO-00393$01 .OO@ 1991 IEEE

Paper 15.1 393

Recent circuit synthesis methodologies, such as the ALPS-Normal form synthesis developed and employed by Xerox-PARC [ 141, and multi-level circuit synthesis by algebraic [20, 301 and extended [18] factorizations of testable two-level expressions, are increasingly making available practical circuits with inherently high, even full, levels of robust path delay fault testability. However, no significant results of investigations into methods to generate “highly efficient” robust tests - robust tests that aimed at maximizing the number of paths detected per test - have yet been reported.

Given the availability of such fully robust testable designs, this paper reports, for the first time, the results of an investigation into more efficient ways of reducing the test set lengths for path delay faults. Results of extensive experimentation show that for such available fully-testable designs, both two-level and multi-level, it is possible to generate very efficient robust tests that do sensitize a high number of paths simultaneously, thereby significantly reducing test-sequence lengths for path delay faults.

The organization of this paper is as follows. Section I1 gives a brief overview of the classes of robust tests and their important properties. Section 111 describes some of the several heuristics that aim to maximize the number of paths tested per robust test, and their integration into an Autotnatic Test Putlern Generation (ATPG) System for deterministic generation of such efficient general robust tests. These heuristics are geared towards achieving maximum efliciency in fully testable two-level circuits. A novel method for test generation in multi-level circuits, that enables us to make use of slightly modified versions of the snrne heuristics in corijunction with the path information from fully testable multi-level circuits, is described in Section IV. Section V contains details and results of the experiments performed on a set of fully-testable Berkeley-benchmark PLAs [29], and on the corresponding multi-level circuits, algebraically optimized by nzisll [28] to preserve full robust testability. Finally, Section VI gives conclusions.

11. Path Delay Faults niid Robust Tests In this section, we review some important charac-

teristics of different classes of robust tests and discuss the issues involved in multiple path fault detecting robust tests. For the sake of simplicity, we assume that the combinational circuits considered are designed with AND, OR, NAhD, NOR and NOT gates. In such circuits, for a given physical path, say P , from an input to an output, testing for path delay faults requires propagating a rising (0 to 1) and a falling (1 to 0) transilion from the root (input) of the path to the output along the signal wires in path P. Thus, for every such physical paih P in such a circuit, we have two logicul paths, one each for the two possible transitions ini- tiated at the root of the path (or finally arriving at the output of the path). Such a logical transition path has a path delay fault if the propagation delay of the path for that transition is larger than the circuit clock period. Because of the need to propagate a signal transition, tests for delay faults are in general two-pattern tests (exceptions being dynamic logic circuits, in which the pre-charge phase plays the role of the first pattern of a two-pattern test).

A two-pattern test T = < V I , V2> is said to be a robust delay test for a path P (for a rising or falling transition at the output of the path), if and only if, when P is faulty and test T is applied, the circuit output is different from the expected state at sampling time, independent of the delays along gate input leads not on P [9]. Necessary and sufficient conditions on a test pair <VI , V2> to be a robust test were given in [9]. Simply stated, these conditions require that the output of a gate along the tested path changes iff the desired transition along the path propagates to the gate’s output [9].

In [18], a classification of robust tests for path delay faults was presented. Here we briefly review the ones directly relevant to the issues of this paper. In general, a single robust test may be a test for several paths to some output in the circuit. Thus, a robust test may actually propagate transitions to an output through more than one path to that output in the circuit; these are termed Multiple- Path Propagating (MPP) robust tests [18]. On the other hand, a robust test that propagates the fault effect through only a single path to an output in the circuit is called a Single-Path Propagating (SPP) robust test for that output. For example, consider the circuit shown in Figures 1 and 2.

Figure 1 The test ~1011, 0001> for a falling transition at the

output y shown in Figure 1 is a MPP-RT, which sensitizes and propagates fault effects robustly along both the paths a-g-y and c-g-y to the output y . However, the test <0011, 0001> for a falling transition at the output y as shown in Figure 2 is a SPP-RT, which sensitizes and propagates the fault effect robustly only along the single path c -g -y.

Figure 2 A robust test is said to be a Hazard-Free Robust

Test (HFRT) if no dynamic hazards can occur on the

Paper 15.7 394

tested path during the application of the test, regardless of the gate delay values [71. (Dynamic hazards have been defined earlier only for single input changes [27]. Here we use this terminology even when more than one input is changing.) For example, the test < l o l l , 0001> ofFigure 1 is a MPP-HFRT for the paths a -g -y and c -g --y for a falling transition at the output y, while the test <001 l, 000b of Figure 2 is a SPP-HFRT for the path c -g -y for a falling transition at its output. The particular case of the SPP-HFRT was first studied in [7], where the restricted delay test pair [7] ensured single path propagation of the fault effect. Such a SPP-HFRT <VI , V2> thus has to provide steady, glitchless, sensitizing values at all the ofl-path sensitizing inputs along P (i.e., those inputs of a gate along P that are not on P themselves), when the primary inputs changed from VI to V2, as seen in the example of Figure 2. The important properties of all these different classes of robust tests have been discussed in detail in [6, 7, 9, 181.

In general, MPP-RTs (or MPP-HFRTs) are more “efkient” tests than SPP-HFRTs from the point of view of the number of tests necessary to achieve desjred fault coverage. This is because SPP-HFRTs can only detect a fault in a single path to an output of a circuit, while MPP- tests (robust or HFR) can detect path delay faults for several different paths to a particular output. However, all the design for testability approaches reported in [13, Ill, 16 - 201 have aimed at producing circuits that are highly [16] or fully [13, 17 - 191 testable by SPP-HFRTs. These include optimized multi-level circuits derived from testable two-level realizations by algebraic and extended factorizations [18, 201, and the ALPS-Normal form circuits developed by Xerox-PARC [14, 151. The key observation is that having been designed for complete SPP-I-IFR testalbility, all paths in such designs are also obviously testable by general RTs, which are potentially multiple path propagating. (A general robust test refers to any robust test, which might be SPP or MPP, hazard-free or otherwise [18].) In the next two sections, we describe the heuriistic-driven test generation procedure aimed at deriving inaximal MPP-RTs, i.e., RTs that detect path faults along as many paths as possible simultaneously.

111. Heuristic Generation of M(ixirnti1 MPP-RTs Several specialized heuristics have been devised eo

facilitate the generation of maximal MPP-RTs in two-level circuits, and some of them are described in this section. They are flexible in the sense that they can be readily integrated into any basic deterministic robust delay test generator, such as the ones reported in [lo - 121. For our purposes, we used a simplified version of the test generator iepoited in [12]. First, a review of some preliminary concepts is presented. 3.1. Preliminaries 19, 181

As mentioned in Section 11, a delay test is in general a two-pattern test T = <VI , V2>, where V I is termed the initidizing vector and V2 the test vector. The initial (final) value of a signal on a lead of the circuit under test (CUT) is the binary logic value on the line after the vector VI ( V 2 ) has been applied at the circuit inputs, and the circuit has stabilized under this input.

In order to facilitate the generation of robust tests, several logic systems have been proposed [6, 9, 12, 221. We shall use the following logic values [9, 221 in our discussion: SO (Sl): corresponds to a signal on a lead with both its

initial and final values as 0 (I), such that the signal is free of any static hazards in the entire time interval from the application of the test-vector (at time instant t l ) to the sampling of the circuit outputs (at time instant t 2 ) ;

U0 (Ul): corresponds to a signal on a lead with a final value of 0 (l), but whose initial value could either be a 0 or a I, and there could also be hazards in the time interval ( t l , t z ) .

TO (Tl): corresponds to a signal on a lead with an initial value of 1 (0) and a final value of 0 (I), and there could also be hazards in the time interval

XX: corresponds to a signal on a lead whose initial and final values are both unspecified.

The implications for circuit signals with the above values (for ANDINAND, OR/NOR and NOT gates) have been tabulated in [9l, and are not repeated here.

The basic step in the deterministic robust test generation procedure for a particular logical target path P is to choose primary input (or headline [ 121) assignments that

(a) initiate the transition of choice at the root of P, (b) propagate it along P to the output of the path, and (c) satisfy the robust sensitization criteria [9] for all ofS-path sensitizing inputs (cf. Section 11) as given in Table 1:

( t l , t2);

Table 1: Off-Path Sensitizing Input Signals

so I q i ti nn II U1

Given these above conditions, we now present some of the heuristics aimed at generating maximal MPP-RTs in IWO- level (AND-OR) circuits. 3.2. Heuristics for Two-level Circuits

Since the two-level AND-OR circuits are fully testable by SPP-HFRTs, they have the following important properties [19, 201: i) They are single-lead-irredundant circuits, i.e., all

single stuck-at faults in the circuits can be tested; ii) They represent realizations of irredundant sums of

prime implicants for each output (of a multi-level circuit). The above properties indicate that there is a one-to-

one correspondence between the inputs to a product (AND) gate and the pafhs in the circuit through that product gate and its corresponding output ~ u i n (OR) gate. We shall thus often use these terms interchangeably in the dis-

Paper 15.1 395

cussion to follow. Note also that since the circuit is irredundant, each primary input can only fan-out to a particular product gate once, either directly or through an inverter. For the sake of convenience, an input I L i i ’ to a product (AND) gate refers to its immediate input, while ‘‘iPI’’ denotes the circuit primary input (PI) corresponding to that particular input i of the product gate. We shall also distinguish between the two logical paths (of the same physical path) in terms of the transition that arrives at the output of the path. For an AND-OR circuit, these outputs are the OR gates. This leads to two cases for consideration:

Paths with rising transitions at the output, which we shall refer to as rising transition paths (RTPs); and

0 Paths withfalling transitions at the output, which we shall refer to as fulling transition paths (FTPs).

In the following sections, we present the details of the individual heuristics for RTPs, as well as the relevant other steps performed to aid the test generation process. The heuristics for FTPs are discussed in general regarding their objectives and the constraints of the environment. How- ever, FTP heuristics are considerably more complex, numerous and detailed than the RTP heuristics, and due to lack of space, are not included here. The relevant details can be found in [31]. 3.2.1. RTP Heuristics

which depicts a portion of a two-level circuit. The ideal desired situation is shown in Figure 3,

U

Figure 3 Given a single chosen target path, since the required conditions for ofS-palh sensitizing inputs (OPSIs) of the output OR gate are all SO signals (cf. Table l) , only one input of the OR gate (the one that is on the chosen target path) can carry a transition, However, since the only requirement on the OPSIs of a product (AND) gate is that they have signals with a final value of 1, this situation can be exploited by allowing as many of the inputs to the product gate (that is on the chosen target path) to carry rising transitions as possible, instead of only having the transition propagated through the single chosen target path. This would thus allow, in the two-level case, as many paths to be robustly sensitized as the number of inputs to a product gate that carried rising transitions. Towards this end, we have the following heuristics that try to choose the best such set of inputs to place transitions on, instead of selecting a single

target path: Heuristic 1: Choosing the path output and product gate:

Choose the primary output OR gate y that has the largest number of total paths through it as yet untested for a rising transition at y; then choose the product gate p at the input to y that has the largest number of paths through it as yet untested for a rising transition at y.

After the choices of y and p have been made, the following circuit signal initializations are performed (given that we started with all leads in the circuit at the value XX):

o Set the outputs of y and p to T1; 0 Set all the OPSIs of y to SO;

Hence, at this point, our problem is essentially to justify all the SO signals at the OPSIs of y (which implies that at least one input of every OPSI gate should be at SO), while allowing as many of the (untested) inputs of p to carry rising transitions as possible. The procedure for achieving this, proc-rtp, is as follows: proc-rtp : begin {

execute Heuristic 2; execute Heuristic 3 ; execute Heuristic 4; while (not all OPSI gates are justified) {

execute heuristic 5; execute heuristic 6;

1 set remaining XX-valued inputs of B to T1; carry out implications; find all newly tested paths for a rising transition at y;

1 end; We shall now describe the heuristics used in proc-rtp above. Heuristic 2: Consider the set AT1 of already tested inputs

i of p (i.e., paths that have already been tested prior to this stage of the test generation process). If AT1 # 0, set all i E ATZ to S1, and carry out all implications. Also, mark the remaining inputs of p (i.e., all i d ATI) as ppt (‘ ‘potential-path-testable’ ’).

The motivation behind the above heuristic is that while such an assignment would not cost the loss of an untested path to y through p, there is a chance that it might produce the required SO values at some inputs to the OPSI product gates of y. (A more sophisticated version, at the cost of considerable added processing, would be to set to S I only those i E AT1 that were determined to produce SO signals at the inputs to unjustified OPSI gates. However, this simpler and less costly version has been found to be equally effective when used in conjunction with the subsequent heuristics described below.) The next heuristic is djnarnic in the sense that it is subsequently repeatedly used by Heuristics 4 and 5 to re-compute the parameters it calculates under changing circuit conditions.

Paper 15.1 396

Heuristic 3: For all XX-valued PIS in the input cones of Heuristic 5:

STEP 2:Pick an XX-valued PI ipI to 6 such that

the opsl product gates that are STEP I:Pick an unjustified OPSI gate 6. unjustified, calculate 0 epnrify: the number of even parity paths (paths

without any inversions along them) from this PI to as yet unjustified OPSI gates; the number of odd parity paths (paths with only single inversions along them) from this PI to as yet unjustified OPSI gates;

0 ipI does not have any fan-outs marked ppt; and 0 an assignment of SOS1 at ipI provides the maximum number of unjustified OPSI gates with an SO signal at an input. (The above can be determined through the parity information provided by Heuristic 3.)

0 oparity:

For example, consider the fragment of a circuit shown in Figure 4, in which all the AND gates are OI>SIs for some OR gate. For the PI A, eparity = 1, and oparity = 2.

... SO (unjustified)

... SO (unjustified)

. SO (unjustified)

... SO tiustifiedl

Figure 4 Note here thdt the above parity numbers are also the numbers of unjustified OPSI product gates that can be reached (directly or through an inverter) from that primary input. Heuristic 4: STEP 1:Compute the set EQPI = {ipl} of all XX-va:lued

PIS such that a i is not markedppt, i.e., ipI does not fanout to p, and hence can be set to either SO or S1; 0 either ipI(eparity) = 0 or ipl(oparity) = 0, i.e., ipI only has identical parity paths (either all dxect or all through inverters) to as yet unjustified OPSI gates.

max{ipl(eparity), ipl(oparity)} = max {maxlipl(eparity), j ~ ~ ( o p a r i t y ) l I jpI E EQPII.

STEP2:Choose ipI E EQPI such that

STEAD 3:Set ipI to S1/SO (accordingly as ipl(oparity) or ipI(eparity) was greater), and carry out the implications of this assignment. Re-execute Heuristic 3.

STEP 4:Repeat above steps until Step 1 gives EQPI =: IZJ, or all OPSI gates have been justified.

An important point to be noted here is that the inputs chosen and set by Heuristic 4 need not be placed on the decision tree, since it would be fruitless (from the point of view of justifying SO signals at the outputs of OPSI gates) to set these inputs to the opposite steady value than that set here. This is because the input assignments made in Heuristic 4 always provide only SO signals at the inputs of all the OPSI gates they fan-out to, so that the opposite steady value assignments at these inputs would only present SI signals at those inputs of the OPSI gates. In thls sense, Heuristic 4 only makes mandatory assignments.

STEP 3:Assign SOIS1 to ipI (as determined above) and place i p ~ on the decision tree. Carry out all implications, noting that backtracks (with the opposite steady value, Sl/SO) might be necessary if implications with the assigned value results in a conflict or a violation of the robust sensitizing conditions, until no more such conflicts or violations occur. Re-execute Heuristic 3.

STEP 4:Repeat above steps until all OPSI gates have been justified, or until Step 2 fails to choose any input at all.

Note here that the above heuristic basically allows a choice of XX-valued PIS that do not fan-out to 0. After such inputs have been exhaus,ted, if there still remains some unjustified OPSI gates, we have to start sacrificing XX-valued PIS that do fan-out to p: Heuristic 6: STEP I:Choose, if possible, from among the XX-valued

PIS to j3, an input ipI such that an assignment of S1 at 1; would provide SO signals at inputs to the muximum number of as yet unjustified OPSI gates. Otherwise, choose any remaining XX-valued PI ipl in the input cone of y.

STEP 2:Assign the proper value SO61 to the chosen input ipI. (Since every input chosen here fans-out to p, only one value from SOfS1, the one that assigns S1 to E’, is admissible.) Carry out the implications of the assignment, and if a conflict occurs or a robust sensitization condition is violated, reset ipI to XX, and backtrack (from the last point in the decision tree), until implications do not cause any conflicts or violations of robust sensitization conditions.

Note that the above heuristic is executed only once, i.e., for only a single choice of i p I , for every execution of the “while” loop (cf. proc rtp) that contains it. How- ever, Heuristic 5 repeats asyong as non-ppt XX-valued inputs remain. This fact, together with the structure of the “while” loop and the fact that every path in the circuit has a SPP-HFR test, can be used to show that after all OPSI gates have been justified, there still remains at least one ppt-marked input of p that is XX-valued, so that the last few steps of proc-rpt can be meaningfully executed. 3.2.2. FTP Heuristics

The objectives in this case are more complex than in the case of RTPs, and are described through the aid of Fig- ure 5. As shown in Figure 5, after a choice of “appropriate” output and product gates y and p have been made, the objective is to maximize the number of product gates CC, 6, CF . . . in the input cone of y subject to the following constraints:

Paper 15.1 397

(a)

(b)

only one input of p can be at TO while all other (OPSI) inputs of p have to be at S1; only one input each of a, 6, C T . . . can be at TO while all other (OPSI) inputs of a, 6, CT . . . have to be at S1; all inputs of y should have signals with a j n a l value of 0. (This includes a, p, 6, ci. . . , all of which should be at TO.)

(c)

(ii)

so I... r - - - l

I - L s1- ; a 1 M s1-

.....

.....

.....

Figure 5 For the sake of brevity, the complete descriptions of

the numerous FTP heuristics used towards this goal, and the relevant details of their application, are not given here. These can be found in [311. 3.2.3. Overall Heuristics

So far, we have concentrated on heuristics that attempt to generate MPP-RTs, for either RTPs or FTPs, for a particular chosen output. In order to also have paths to other outputs robustly sensitized simultaneously, we currently use the following simple final heuristic, once the execution of all RTP or FTP heuristics is over: Heuristic 7: Set every remaining (if any) XX-valued PI

After the implications for the above assignment are carried out, all the newly detected path faults (for both falling and rising transitions at outputs) are then deterrmned, and the faults database is updated before choosing the next output and fault type to test for.

More sophisticated heuristics for making “better” or “more logical” choices than random choices for the unspecified inputs, as in Heuristic 7, have been devised and can be implemented, with an added computational expense. However, even the simple-minded Heuristic 7 has been seen to perform adequately in most cases. The reasons for this are the following: (i) In most of the test examples studied, the input cones

for different outputs had a large number of primary inputs in common. Fixing some of the PIS to appropriate values through the use of RTP or FTP heuristics for a particular, chosen output either already succeeded in testing numbers of paths for outlier outputs that could not be subsequently much improved on, or precluded the testing of numbers of

randomly to either TO or T1.

paths because conditions for robust testing for those other output paths had already been violated. In some cases, the majority (or even all) of the primary inputs of the circuit had already been specified before any overall heuristic could be applied. This left very little margin for improvement (or even none at all) by any overall heuristic applied at this stage.

IV. MPP-RTs for Multi-Level Circuits In this section, we describe a novel method that

allows us to present the path information of fully robust- testable multi-level circuits to virtually the same heuristics as in Section 111, and derive MPP-RTs for the multi-level circuits using essentially the same overall test generation process as described in the last section. When such multi- level circuits have actually been synthesized by algebraic and extended factorization [B, 201 of fully-testable two- level circuits, this method allows the usage of almost exactly the same heuristics as in Section 111 to derive MPP-RTs for the multi-level circuit, with slight modifications that will be shown later. Since all of our test cases were in fact so synthesized, we shall concentrate on such a methodology. However, this method is general enough to deal with all multi-level circuits that are fully testable. More comprehensive modifications to the RTP and FTP heuristics are then necessary, as dictated by the different general robust testability conditions given by Theorems 1 and 2 in [18]. These modifications, rhough quite straightforward, are rather long and omitted here for the sake of brevity.

Figure 6 The basis of this method is a circuit transient information representation technique [27]. In order to analyze the transients in combinational logic circuits, algebraic expressions that represent the relationship between inputs and outputs not only when the inputs have steady values, but also when the inputs are changing, were developed in [27]. These expressions, using subscripted variables, are called Transient Output Functions (TOFs), where thiz path information of a circuit is associated with the set of subscripts on the literals in the TOF. The delays in a nl-twork are taken into account by numbering all the leads in the network and associating a corresponding delay with each lead. Each variable in the TOF is a primary input variable of the circuit, and each subscripted literal ~ * ~ , ~ , k , . , , , , in the TOF indicates that there exists a path i - j - k - ...- n from the primary input variable a to the output being considered for the TOF. We shall also refer to such subscripted literals, as path lirerals. The procedure to obtain the TOF for an output y of a circuit is described in [27], and is noit given here for the sake of brevity. However, the circuit of Figure

Paper 15.1 398

6 is used an an example to show the derivation of TOFs. In this circuit, T°Fb)= ‘9,lI + j l O , l l =f6,9,11c3,9,11 + h8,10,11g7,10,11 = c3,9,11~u1,6,9,11 +b2,6,9,11)

- u1,6,9,11c3,9,11 b2,6,9,11C3,9,11 C3,8,10,11d4,7,10,11 + ~3,8,10,11(d4,7,10,11 -t e5,7,10,11) - -

‘-3,8,10,1 le5,7,10,1 1 = apCM + b CM + FNdR + FNes w h e r e M , i f P , Q , R andsarethepaths 3-9-11, 3-8-10-11, 1-6-91-11, 2-6-9-11,4-7-10-11 and 5-7-10-11 respectively.

An important point to be noted about the TOF is that the output lead of a circuit will have a signal value corresponding to a “1” when and only when the TOF of the network is equal to one [27]. As shpwn above, sime a set of (ordered) subscripts on a literal a (where a can be a or G) of a product term of the TOF represents a path, say P, in the circuit from the primary input variable a to the output, we shall replace such a set of subscripts by the name of the path, P, for brevity. As is clear from the way the TOF for an output y is constructed, every path in the circuLt that terminates at y appears as a subscript an a literal in a product term of TOF (y).

The TOF of an output of a multi-level circuit is lhus a two-level sum ofproducts (SOP) representation that contains all the path information of the original circuit. The direct two-level AND-OR realization of such a TOF, with the path literals as the PIS and the product terms of the TOF the AND gates, which we shall call a Pseudo-Two- Level TOP (PTL-TOF) circuit, is thus a natural “circuit” representation containing all the logical and topological information required by the heuristics of Section 111: to generate MPP-RTs. Such a PTL-TOF circuit for the example of Figure 6 is given in Figure 7.

so , CM

F I

FN eS * Figure 7

Any robust test for a path literal (or a set of path literals, in case of MPP-RTs) in the TOF expression is actually a robust test for the path(s) in the multnlevel circuit represented by that path literal (or set of path literals) in the TOF [18]. This leads to the following technique for deriving MPP-RTs for multi-level circuits: 0 Construct the PTL-TOF circuit for the given multi-

level circuit; e Apply the methods of Section I11 (with the slight

modifications as discussed later) to derive MPP-RTs for the paths in this PTL-TOF circuit. These are also

the set of MPP-RTs for ihe original multi-level circuit. The key observation here is that a path*A in the

PTL-TOF circuit, that starts at a path literal a B , passes through a product gate, and encis at the output OR-gate, is actually equivalent to the path B in the* multi-level circuit that is represented by the path literal a at the root of A. Thus, any robust test for A in the PTL-TOF circuit is also a robust test for B in the original circuit. For example, the MPP-RT shown in Figure 7, which tests both the path- literals b and CM (and the corresponding paths in the PTL-TOBcircuit), is exactly the same robust test for the paths 2-6-9-1 1 (Q) and 3-9-1 1 ( M ) in Figure 6 .

However, there is one major point to be noted here that makes minor modifications to the relevant procedures of Section I11 necessary: several paths in the PTL-TOF circuit might actually begin at the same path literal. For example, consider the circuit shown in Figure 7. As can be seen, there are two different paths in the circuit from the path literal cM, one passing through the top AND gate and the other through the next one. Robust tests for both these paths would therefore be valid robust tests for the same path 3-9-1 1 in the circuit of Figure 6. Hence, the required modification is that whenever a particular path A in the PTL-TOF has been determined to have been robust tested (or being considered) by a particular test, all other paths in the PTL-TOF that begin at the same path literal as A should also be considered as having been tested by the same test to prevent wasted effort in the future, and keep an accurate track of the actual paths in the original circuit that have been tested. This holds also for any of the heuristics that attempt to estimate the number of distinct paths that might be tested by certain assignments.

In essence, these minor modifications are aimed at removing the effects of path multiplicities that may be present in the PTL-TOF circuit. For example, consider the test shown in Figure 7 which does not actually test the path from cM through the top AND gate. However, since it does test the path from cM through the second AND gate, we already have a test for the actual path 3-9-11 in the circuit of Figure 6, and update the faults database to reflect this by considering the first path from cM to also be tested. The more extensive modificatiions required for general multi-level circuits, as mentioned at the beginning of this section, are along similar lines in so far as they have to deal with spurious path effects (of other types) that are present in the PTL-TOF circuit but have no physical coun- terparts in the original multi-level circuit [ 181.

One potential drawback of this multi-level circuit transformation method is that it would be inefficient for very large circuits (chiefly because of the expense involved in computing the very large TOFs for such circuits), which is why currently research into stand-alone heuristics (that do not depend on special circuit transfor- mations) for multi-level circuits is underway. However, a lot of care has been taken to make this procedure as efficient as possible, and for our test examples, some of which were quite large, it has performed efficiently.

Paper 15.1 399

V. Experiments and Results All the procedures discussed in the previous sections

were implemented as a C-language program to provide general MPP-RT generators for two-level and multi-level circuits. The performance of these ATPGs was evaluated through experimentation on a set of Berkeley PLA- benchmark circuits from [29]. The members of this set were determined in the following manner. Each PLA from [29] was optimized using espresso [29] to derive circuits that realized irredundant sums of prime implicants for every single output, which is one of the necessary conditions for robust testability [18, 19, 201. (The options “- Dso” and “41” were used with espresso to achieve this.) In order to further optimize these circuits, all identical product terms (that fed different outputs) in the multi-output functions were merged together. An efficient SPP-HFRT generator [31] was then used to determine which such circuits were fully testable by SPP-HFR Tests. Only these circuits, which numbered 18, were included in the test set. These same 18 circuits were optimized using algebraic factorizations through misII [28] to provide the corresponding test set for multi-level circuits.

Tables 2 and 3 give the performance results for the two-level and multi-level circuits respectively. Column 2 in both tables gives the total number of (logical) path faults in each circuit. Column 3 shows the number of MPP-RTs that our test generation methods provide to achieve full coverage of all the path faults. Column 4 gives the average number of paths tested per MPP-RT, which is a meas- ure of the efficiency of the MPP-RTs, while Column 5 gives the maximum number of paths tested by any MPP- RT generated for that particular circuit.

Table 2

Circuit

add6 adr4 alul alu2 alu3 col4 dk17 dk27 dk4 8 mish radd rckl rd53

xldn x9dn

24 I Z9sym

vg2

Results No. of Path

Faults 4392 680

82 558 568 392 358 134 574 328 680

2286 280

1608 1928 2276 504

1008

r Two-I vel AKD-I No. of Delay Tests 1297 282 37

162 164 224 128 49

192 138 274 228 160 314 337 339 219 672

Average paths

per test 3.39 2.41 2.22 3.44 3.46 1.75 2.80 2.73 2.99 2.38 2.48

10.03 1.75 5.12 5.72 6.71 2.30 1 .50

R circuits Pvl aximum

paths per test

48 12 10 22 22 13 28 33

110 27 12 32 3

43

As can be seen, the proposed methods always produce an improvement in the test set length over that required in the worst case by SPP-HFRTs (where a separate SPP-HFRT would be required for each logical path). The amount of improvement is seen to be quite circuit specific, ranging

from over a 10-fold improvement (rckl) to a 1.5 times improvement (Z9sym) with an average of over a 3.5-fold improvement for the two-level case, and ranging from over a 4-fold improvement (x9dn) to a 1.3 times improvement (Z9sym) with an average of over a 2.5-fold improvement for the multi-level case.

Tal

Circuit

add6 adr4 alu 1 alu2 alu3 col4 dk17 dk27 dk48 mish radd rckl rd53

xldn x9dn

24 Z9svm

vg2

? 3: Res No. of Path

Faults 498 210 76

260 282 144 340 128 572 280 170 476 154 492 440 612 190 644

ts for M No. of Delay Tests

23 1 112 40 83 89

100 125 50

194 126 89

135 95

124 122 140 100 490

Iti-Level E Average

paths per test

2.16 1.88 1.90 3.13 3.17 1.44 2.72 2.56 2.95 2.22 1.91 3.53 1.62 3.97 3.61 4.37 1.90 1.31

wits Maximum

paths per test

13 8 9

14 14 13 18 36

110 29 7

32 4

43 40 58

6 3

100 x9dn: Two-Level

8oi /- Coverage 4o 6ol /

Figure 8 20 -

-0 I I I I 7 -0 20 40 60 80 100

% of tests, Best -+ Worst

60 Coverage 4o 7~ Fault

Figure 9

-0

-0 20 40 60 80 100 % of tests, Best -+ Worst

Paper 15.1 400

An interesting parameter of these MPP-RTs is the

6 path

ETE

11.3 6.1 6.8 9.6

10.1 6.3 8.1

22.3 28.7 7.8 6.2

19.4 2.8

12.8 13.6 18.7 4.6 3.0

100 dk48: Two-Level /

fault CO

h/ No. of

faults 249 105 38

130 141 72

170 64

286 140 85

238 77

246 220 306 95

322

% Fault Coverage

adr4 alul ah2 ah3 col4 dk17 dk27 dk48 mish radd rckl rd53 vg2

xldn x9dn

24 Z9sym

W

340 41

279 284 196 179 67

287 164 340

1143 140 804 964

1138 252 504

4 0 4 d Figure 10

-0

-0 20 40 60 80 100 % of tests, Best 4 Worst

Figure 11

Coverage

-0 - -0 20 40 60 80 100

% of tests, Best 4 Worst

‘I

-0 20 40 60 80 1.00

% of tests, Best 4 Worst

-0 20 40 60 80 1.00

% of tests, Best 4 TVorst

maximum number of path faults, that the best such test was able to detect, which is quite high for most circuits, being as much as 110 in the case of dk48. In fact, in most cases, a few “high grossing” MPP-RTs were able to test a rela- tively very large number of paths, but in doing so, reduced the chances subsequent tests had of testing large numbers of paths. This significant observation is shown in Figures 8 - 13, which show the distributions of fault coverages for tests, graded from the “best” to the “worst”, for a total of six example circuits, three two-level, and three multi-level. In each category, the three circuits chosen were one each with high, medium and low levels of overall improvement figures. These graphs are fairly representative of almost the whole test set, in that most other circuits exhibited similar behavior to the ones depicted in these figures. The bar charts in Figures 8 - 13 give the individual fault coverages achieved by particular slots of tests, while the con- tinuous line is a plot of the cumulative fault coverages attained by the graded tests. As seen from Figure 10, for example, for the two-level version of dk48, about 5% of the total number of tests already provided more than 50% fault coverage. Given that this 5% of the tests is about 10 in number, and that they detect 287 path faults, the effective testing efficiency for this fraction of the MPP-RTs is as high as 29 paths per test (though its overall testing efficiency is about 3 paths per test)! Similar other high effective testing efficiencies are achieved by small sets of high grossing MPP-RTs for most of the cases. This is reported in Table 4, which shows the effective testing efficiencies (in terms of the number of paths tested per test) of the best MPP-RTs for a path fault coverage 50%.

Table 4: Effective ’I MPP-R‘

Circuit lh’ faults &

for 51 * No. of RTs 195 56 6

29 28 31 22 3

10 21 55 59 50 63 71 61 55

168

-

-

-

sting Efficiency (ETE) of rage - ti-Lv No. of

46 22 10 15 15 27 15 3 9

15 16 20 28 18 20 24 25

162

RTs -

-

ETE

5.4 4.8 3.8 8.7 9.4 2.7

11.3 21.3 31.8 9.3 5.3

11.9 2.8

13.7 11.0 12.8 3.8 2.0

- -

-

of

VI. Conclusions The recent availability of fully path delay fault

robust testable designs has made it feasible to consider the problem of making test application for path delay faults

Paper 15.1 40 1

more efficient by reducing the sizes of test-sets required to obtain a certain desired coverage. This is an important consideration for the path delay fault model, specially because of the potentially huge test-set lengths required to obtain ful l coverage under this model (by testing all the numerous paths in the CUT), which has so far been the single drawback of the otherwise exceptionally strong path delay fault model. In this paper, we proposed, for the first time, an integrated, heuristic-dnven test generation procedure for robust tests for path delay faults that is geared to generating maximal multiple-path-propagating robust tests, i.e., robust tests that detect the maximum possible number of path faults simultaneously.

The experimental results on a large set of fully testable benchmark circuits show that in both two-level and multi-level cases, it is possible to generate very efficient robust tests that do sensitize a large number of paths simultaneously, thereby significantly reducing test- set lengths for path delay faults. The methods proposed are general enough to apply to all fully testable multi-level circuits, and not only the ones synthesized from fully testable two-level realizations, though the experimental set of circuits considered here have been of the latter kind.

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Paper 15.1 402

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