Thin Solid Films 519 (2011) 5456–5463

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Influence of thermal oxidation on the interfacial properties of ultrathin strainedsilicon layers

V. Ioannou-Sougleridis a,⁎, N. Kelaidis a, D. Skarlatos b, C. Tsamis a, S.N. Georga b, C.A. Krontiras b,Ph. Komninou c, Th. Speliotis d, P. Dimitrakis a, B. Kellerman e, M. Seacrist e

a Institute of Microelectronics, NCSR “Demokritos” 153 10 Athens, Greeceb Department of Physics, University of Partas, 265 04 Partas, Greecec Department of Physics, Aristotle University of Thessaloniki, 541 24 Thessaloniki, Greeced Institute of Material Science NCSR “Demokritos” 153 10 Athens, Greecee MEMC Electronics Materials, Inc., 501 Pearl Drive (City of O'Fallon) St. Peters Missouri 63376, USA

⁎ Corresponding author. Tel.: +30 210 6503 240; faxE-mail address: v.ioannou@imel.demokritos.gr (V. Io

0040-6090/$ – see front matter © 2011 Elsevier B.V. Adoi:10.1016/j.tsf.2011.02.085

a b s t r a c t

a r t i c l e i n f o

Article history:Received 28 May 2010Received in revised form 23 February 2011Accepted 23 February 2011Available online 2 March 2011

Keywords:Strained siliconThermal oxidationSilicon–germaniumOxide semiconductor interface

In this work we examine the influence of thermal oxidation on the electrical characteristics of ultra-thinstrained silicon layers grown on relaxed Si0.78Ge0.22 substrates under moderate to high thermal budgetconditions in N2O ambient at 800 °C. The results reveal the presence of a large density of interfacial trapswhich depends on the oxidation process. As long as the strained silicon layer remains between the growingoxide and the underlying Si0.78Ge0.22 layer, the density of interface traps increases with increasing oxidationtime. When the oxidation process consumes the s-Si layer the interface state density undergoes a significantreduction of the order of 40%. This experimental evidence signifies that the strained silicon–Si0.78Ge0.22interface is a major source of the measured interfacial defects. This situation can be detected only when thefront SiO2-strained silicon interface and the rear strained silicon–Si0.78Ge0.22 interface are in close proximity,i.e. within a distance of 5 nm or less. Finally, the influence of the material quality deterioration—as a result ofthe thermal treatment—to the interfacial properties of the structure is discussed.

: +30 210 6511 723.annou-Sougleridis).

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© 2011 Elsevier B.V. All rights reserved.

1. Introduction

The presence of strain within the channel region of ametal–oxide–silicon field effect transistor (MOSFET) increases the mobility of bothelectrons and holes charge carriers [1]. This effect has been utilizedfrom the 90 nm technology node as an additional factor to obtain thenecessary high drive currents of scaled MOSFET devices at reducedsupply voltages [2]. Silicon under strain can be generated eitherlocally, using specific processing steps (the so-called stressors andtensors), or across the entire wafer [3]. Although, local strain schemeshave been employed in high performance MOSFETs, strained-Si (s-Si)layers epitaxially grown on relaxed SixGe1−x substrates still remainan alternative technological option for high performance improve-ments of scaled MOSFET devices [4]. In addition to the mobilityenhancement issue, high stress levels may improve the gate leakagedue to the higher electron affinity of the tensile stressed Si layer [5].Moreover, electron paramagnetic resonance studies of oxidized s-Silayers on SixGe1−x virtual substrates showed a 50% reduction of thedensity of interface traps (Pb0 and Pb1 centers) and of near interfacetraps (Eγ′ centers), as compared to the standard Si/SiO2 interface [6].

It should also be mentioned that strain-free SixGe1− x virtualsubstrates are very important buffer layers in heteroepitaxial growthstudies synthesizing top semiconductor layers with or without strainby adjusting the composition of the SixGe1−x [7].

An important viability issue of these substrates is their thermalstability during the high temperature processing steps, which mayresult to Ge out-diffusion or to strain relaxation via dislocationgeneration [8–12]. If the s-Si thickness is above a certain criticalthickness strain relaxation of the s-Si layer takes place via misfitdislocations generation. Alternatively, if the SiGe layer is not fullyrelaxed thermal treatments may initiate further relaxation of the SiGelayer via threading dislocations propagation through the SiGe layer upto the s-Si/SiGe interface [12], or by generation of misfit dislocations atthe s-Si/SiGe interface [13]. In the case of ultra-thin s-Si layers a hightemperature oxidation step results in an s-Si/SiO2 interface of lowelectrical quality with a high density of interfacial defects [13]. This lastissue is usually associated with Ge out-diffusion from the SiGe layertowards the s-Si layer and segregation at the s-Si/SiO2 interface,generating interface traps and degrading the gate oxide integrity [13].These considerations define the useful range of s-Si thickness whichdepends on the Ge content of the SiGe layer and the processing thermalbudget [14].

In a recent work [15] we had questioned the origin of the interfacetraps which are created during the oxidation of the ultra-thin s-Si

Table 1List of samples and main processing parameters used in this study. The SiO2 thicknessand the remaining s-Si overlayer thickness are also reported.

Sample RCAcycles

Oxidation Annealing Oxidethickness

s-Sithickness

S2R No – – – 13 nmS2N Double – – – –

S2A Single 800 °C, 20 min 800 °C, 30 min 3.5 nm 3.5 nmS2B Single 800 °C, 30 min 800 °C, 30 min 4.3 nm 3.1 nmS2C Single 800 °C, 60 min 800 °C, 30 min 5.2 nm 2.7 nmS2D Single 800 °C, 120 min 800 °C, 30 min 5.9 nm –

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layers on relaxed SixGe1−x substrates. The main outcome of ourprevious study concluded that, a significant part of the apparentinterface traps must reside at the back s-Si/Si0.9Ge0.1 interface. In thepresent work we continue this investigation using higher Ge contentSi0.78Ge0.22 buffer layers and a study is presented regarding theinterfacial properties of ultrathin strained silicon layers oxidizedunder moderate to high thermal budget conditions in N2O ambient.The results support our previous findings and indicate clearly thatdefect formation takes place initially at the SiO2/s-Si and the s-Si/SiGeinterfaces. By increasing the thermal budget, we observe an increaseof the interfacial defects that upon consumption of the s-Si layer bythe oxidation process are reduced substantially. This indicates that thes-Si/SiGe interface is a major source of interfacial defects. Moreover,with the increase of the thermal budget the bulk defects are formedwithin the SiGe substrate. Both interfacial and bulk defects producesignificant generation currents at the inversion–depletion biasregimes, which distort the extracted interface trap density profilesfrom the C–V characteristics.

2. Experimental details

The strained-Si/relaxed SixGe1−x heterostructure substrate used isschematically shown in Fig. 1. Epitaxial p-type silicon layer, withresistivity 1 Ω cm and thickness 2.75 μm, was grown on top of a5 mΩ cm p++ boron doped wafer, followed by a graded SixGe1−x

layer in which the Ge content increases linearly from 0 to 22%. On topof the graded SixGe1−x a constant composition Si0.78Ge0.22 layer and as-Si layer 13 nm thick, were grown successively. The SixGe1−x and thes-Si layers were not intentionally doped with boron. However, aresidual doping in the low range of 1014 cm−3 is expected due to thedeposited systemauto-doping effects. The sampleswere subjected to aRadio Corporation of America (RCA) cleaning process. This step servesalso as an effective etching process of the s-Si overlayer. Transmissionelectron microscopy (TEM) studies (not shown here) indicated thatfollowing the RCA process the s-Si overlayer has been reduced down to4–5 nm. Thermal oxynitridation in 100% N2O ambient was performedat 800 °C for 20, 30, 60 and 120 min in a conventional atmosphericpressure furnace, followed by a post-oxidation annealing at theoxynitridation temperature for 30 min. The Si oxidation rate in aN2O ambient is slower as compared to pure oxygen widening theprocessing timewindow, especially for ultra-thin s-Si layers like in ourcase. The fabricated samples were designated as S2A to S2D as can beseen in Table 1. Reference samples were also studied in the as-grownstatewith (S2R) andwithout (S2N) the s-Si layerwhichwas etched offby two RCA cleaning cycles. The SiO2 thickness and the estimatedremaining s-Si overlayer thickness after oxynitridation are also shownin the Table 1. The former was extracted from the Maserjiancapacitance method [16] and the latter was estimated by subtracting

Fig. 1. Schematic diagram indicating the ordering of the several layers of the strainedsilicon structure.

from the initial s-Si thickness (before the oxidation step), the standardsilicon consumption during oxidation (0.44tox where tox is the oxidethickness). These thickness values must be considered as grossestimations, due uncertainties of the initial s-Si layer thickness andalso due to oxide thickness determination errors.

The motivation to study the influence of oxidation of ultra-thinstrained silicon samples (beyond their practical thickness) on theinterfacial properties was driven by the intention to have the SiO2/s-Siinterface in close proximity to the s-Si/Si0.78Ge0.22 interface. It isanticipated that the high thermal budget process which the samplesunderwent combined with the ultra-thin s-Si overlayer will resultin a significant Ge out-diffusion from the Si0.78Ge0.22 layer towards thes-Si/SiO2 interface, increasing thus the density of interface states andthe fixed charges [17]. In addition, such configuration should allow forthe collective response of both interfaces to electrical measurements[15]. Generic type aluminum capacitors were formed using photoli-thography and wet etching, in order to study the electrical character-istics of the structures. The capacitors were subjected to a forming gaspost metallization annealing at 400 °C for 20 min. The samples weretested by x-ray diffraction (XRD) at room temperature using a SiemensD-500 x-ray diffractometer. The x-ray radiation was provided by aCuKα source (1.54 Å) operated at 40 kV. The variation of the diffrac-tion angle 2Θ was from 1 to 90°, with an angular resolution of 0.03°.TEM image studies were performed in cross-section geometry in bothconventional and high resolution techniques utilizing a JEOL 2011electron microscope operating at 200 keV. The electrical measure-mentswere recorded in the dark at roomor higher temperatures usinga Signatone probe station with a hot chuck system using an HP 4284ALCR meter and an HP 4041B picoammeter.

3. Results

3.1. X-ray diffraction and transmission electron microscopy results

Fig. 2 shows XRD patterns recorded from four selected sampleseither with different s-Si layer thickness or without the s-Si layer (asindicated in Table 1), in the region of the (004)main diffraction peaks.The patterns are dominated by the strong diffraction peaks arisingfrom SiGe layer and from the Si substrate. Differences between thepatterns are observed at 2Θ angles larger than 69.5°. According to Ref.[18], this is the region where the diffraction signal from the s-Si isexpected. Therefore, these differences are attributed to the s-Si layer.The stronger signal arises from the as-grown sample which has thethicker s-Si layer, while the weaker from the samples S2N and S2D.These results suggest that the s-Si layer of sample S2D was consumedduring the oxidation, since sample S2N has no s-Si layer.

Fig. 3a shows a bright field cross-section HRTEM image from theas-grown sample along the [110] axis. The image indicates the goodquality of the epitaxial s-Si layer of 13 nm thickness. Fig. 3b shows thecorresponding HRTEM image of sample S2D, which clearly reveals thatthe s-Si overlayer was totally consumed by the oxidation process. Thisin turn suggests the partial oxidation of the underlying SiGe layer, aprocess which leads to a strong Ge pile-up effect at the SiO2/SiGeinterface [15,17]. The oxide thickness was estimated by TEM at 6.5 nm,

Fig. 2. XRD patterns of two control and two oxidized samples. Eachmain layer gives twopeaks due to the diffraction of the CuKa1 and CuKa2 x-ray components. Thisrepresentation was preferred since the usual extraction procedure of the CuKa2peaks reduces substantially the signal at angles higher than 69.5° and any comparisonbetween the samples within this range is meaningless.

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while the interface between the SiO2 and the SiGe is rather rough(~1 nm roughness) either due the Ge pile-up effect or to pre-existingSiGe layer undulation. Therefore, TEM results confirmed the XRDresults regarding the consumption of the s-Si layer after the prolongedoxidation. It has been reported that the influence of thermal treatment

Fig. 3. (a) Cross-sectional HRTEM image showing the as-grown S2R sample along the[110] zone axis. The 13 nm thick s-Si layer is visible while the s-Si/SiGe interface isindicated by the white line. (b) HRTEM of sample S2D, which illustrates the absence ofthe s-Si due to the prolong oxidation treatment.

in SiGe material either under stress or in a relaxed state, may occur viaSi–Ge intermixing [19], dislocation generation [10] or further relaxationof the SiGe substrate, if the latter was not fully relaxed [12]. However,the invariance of the XRD patterns in the region of the SiGe peaksindicates that no significant structural transformation occurred in theSi0.8Ge0.2 layer during the long temperature treatment. In addition,Raman studies (which are not presented here) do not indicate arelaxation of the SiGe substrate.

3.2. Capacitance–voltage characteristics

The high frequency (1 MHz) capacitance–voltage (C–V) character-istics from all samples are shown in Fig. 4. Themost prominent featureof these characteristics is the presence of a hump or plateau aboveflat-bands. This plateau signifies a gate voltage regime where thesemiconductor surface potential is either constant or slowly varying.In most cases a plateau defines either a charge trapping mechanismthat takes places at interface traps, or a charge confinement effect atsemiconductor heterojunctions [20,21]. These two cases can bedistinguished from their frequency response. In the case of interfacetraps the plateau shows strong dispersion upon the ac signalfrequency variation of the capacitance measurements, while chargeconfinement plateaus involving confinement of carriers at hetero-junctions are frequency independent [22]. Fig. 5a and b show theroom temperature C–V characteristics of samples S2A and S2Drecorded within the frequency range of 1 MHz to 1.6 kHz. For sampleS2D the quasi-static (QS) C–V characteristic is also presented (SampleS2A has a very thin oxide and the QS–C–V measurement could not beobtained). Although both samples exhibit strong frequency depen-dence the plateau region is frequency independent. This also holds forthe two other samples. This indicates that the plateau is not related tointerface traps but rather to the confinement of holes at the s-Si/SiGeheterojunction. In the case of sample S2A (shorter oxidation) a veryprominent plateau is evident, being almost horizontal with an extentof 100 mV. For the case of sample S2D, which had no s-Si overlayer,the plateau becomes less prominent. The presence of a plateau in thelast case should be attributed to the strong Ge pile-up effect whichmay result in band discontinuities at the SiO2 interface.

Fig. 6 shows the apparent carrier concentration NappHF as afunction of the depletion layer depth XdHF from the SiO2 interface,calculated according to the following equations [23]:

NappHF VGð Þ = qεSi2

d�1 C2

HF

. �dVG

24

35−1

ð1Þ

Fig. 4. 1 MHz C–V characteristics of all oxidized samples. The most prominent feature ofthe characteristics is the plateau region.

Fig. 5. Capacitance–voltage characteristics within the frequency range of 1 MHz to1.6 kHz of samples S2A (a) and S2D (b). The quasi-static C–V is also shown for the caseof S2D sample. In both cases the plateau region is independent of frequency. Note thatthe plateau in the case of sample S2A is well defined and almost flat, while for sampleS2D appears as a change of C–V slope.

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XdHF = εSi1

CHF VGð Þ−1Cox

� �ð2Þ

where εSi is the dielectric constant of Si, q is the electronic charge, Coxthe oxide capacitance and CHF the high frequency (1 MHz )

Fig. 6. Apparent doping vs. depth profile of all studied samples, extracted from the1 MHz high frequency characteristics. The local maxima correspond to unrealisticvalues for the s-Si thickness due to the presence of interface traps. The importantphysical meaning is the deterioration of the s-Si/SiGe hole confinement ability with theoxidation time. This trend is interpreted as defect formation at the s-Si/SiGe interface.

capacitance. This plot has been extensively utilized for the estimationof the s-Si layer thickness, since the C–V plateau results in a localmaximum of the apparent carrier concentration vs. depletion layerdepth. As can be seen in Fig. 6 the estimated depths from this graphdeviate significantly from the nominal values of the s-Si layerthicknesses shown in Table 1. This is attributed to the large densityof interface traps and their capacitance heavily distorts the measuredcapacitance values [22]. The peak arises from the C–V plateau andreflects the strength of the hole confinement effect at the s-Si/SiGeinterface. In this sense, Fig. 6 reveals an interesting qualitative trend.The increase of the oxidation time results in a gradual fade-out of thepeak characteristics, attributed to the deterioration of the s-Si/Si0.78Ge0.22 heterojunction. It is concluded thus that high thermalbudgets lead to a gradual relaxation of the hole confinement ability.

Fig. 7 shows the resulting interface trap density estimated from thehigh–low C–V method. The three samples exhibit an identicalbehavior, having an almost constant density of interface traps aroundmidgap of the order of 2–3×1012 eV−1 cm−2. There is also anapparent increase in the interface trap density near the conductionband (inversion regime) and a sharp drop of the interface trap densityfrom Ev+0.35 eV towards the valence band.

3.3. Conductance characteristics

The density of interface traps was further examined by conduc-tance measurements. All samples exhibited the same behavior, whichis presented in Fig. 8a and b showing the room temperatureconductance characteristics of samples S2A and S2D for several gatevoltages. At weak inversion, a narrow conductance peak dominatesthe Gp/ω–f spectrum having a maximum at relatively low frequencies.As the gate voltage biases the capacitor progressively into depletionthe single peak evolves into a double peak response and thecharacteristic is shifted to higher frequencies. This behavior indicatesa typical response of interfacial traps and it is further evident that asthe structure is biased into depletion the low-frequency contributionis reduced and finally vanishes while the high frequency oneincreases. These two loss mechanisms were resolved by monitoringthe evolution of the Gp/ω–f characteristics at higher temperatures.

3.4. High temperature characteristics

C–V, G–V, QS andGp/ω–f measurements were performedwithin thetemperature range 295–355 Kwith a step of 10 K, in theweak inversionand depletion regimes in order to exploit the behavior of theconductance characteristics and to determine the activation energy ofthe loss mechanisms. The Gp/ω vs. f characteristics in both bias regimes

Fig. 7. Density of interface traps across the energy gap extracted from the high–low C–Vmethod for the samples S2B, S2C and S2D.

Fig. 8. Conductance characteristics vs. frequency recorded for several gate voltageswithin the weak inversion and depletion regimes of samples S2A (a) and S2D (b). Bothgraphs have been plotted under the same y-axis scale. Note that the loss peak at weakinversion is higher for the sample S2D. At depletion the loss characteristics are higherfor sample S2A.

Fig. 9. Evolution of the conductance vs. frequency characteristics with temperature atthe depletion region of samples S2A (a) and S2D (b). The characteristics were assumedto arise from two different loss mechanisms, and they were deconvoluted into twoGaussian contributions. The graph also indicates temperature evolutions of the low(peak A) and the high (peak B) frequency contributions.

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shift towards higher frequencies with temperature, due to the timeconstant increase of the interface traps. This is illustrated in Fig. 9a andb which show the temperature dependence of the conductancecharacteristics of samples S2A and S2D in the depletion region, forgate voltages −0.12 V and −0.14 V respectively. The complexconductance characteristics in the depletion regimewere deconvolutedinto two separate Gaussian contributions designated hereafter as peakA and peak B. The deconvolution process could be applied withconfidence only to these cases where the two peaks were well defined.Fig. 9a and b show also a temperature evolution of the twocontributions of the conductance characteristics. The activationenergies of the loss mechanisms were extracted from the ln(fmax/T2)vs. 1/T Arrhenius plots (where fmax is the frequency of the conductancemaximum and T the temperature of the measurement) and arepresented in Fig. 10a and b for samples S2A and S2D respectively. Inparticular, the activation energies for all samples in the weak inversionregion were found to have values within the range 0.53–0.58 eV.Therefore, the loss mechanism in the weak inversion is due togeneration effects via midgap states, a case frequently encountered inMOS structures with high density of interfacial defects. In the depletionregion the activation energies of peak A were found to have valueswithin the range 0.45–0.51 eV resulting thus to an Arrhenius plotalmost parallel to that of the weak inversion case. Taking into accountthe inherent uncertainty of the deconvolution procedure, we attributepeak A also to generation effects via midgap states. The activationenergy of peak B has values 0.37 to 0.43 eV and is attributed tointerfacial defects.

The density of interface traps corresponding to peak B wascalculated from the peak maximum according to the relation [22]:

Dit≅2:5qA

Gp

ω

� �max

ð3Þ

where A is the area of the capacitor, q is the electronic charge, and(Gp/ω)max is the conductance value at the peak. Fig. 11 shows theresulting density of the interface traps extracted from Eq. (3) as afunction of the oxidation time at Ev+0.4 eV. It is evident that theinterface traps density increase from 8.2×1011 to 1.2×1012 eV−1 cm−2

with the increase of the oxidation time from 20 to 60 min indicating anincrease of 30%. At the longest oxidation of 120 min the Dit valuedecreases to 7.2×1011 eV−1 cm−2 which corresponds to a reduction of40% relatively to the S2C sample. It is important to notice that sampleS2D (i.e. without the s-Si layer) exhibits the lowest Dit value despite thefact that it must have the highest Ge concentration segregated at theSiO2 interface due to the consumption of the s-Si layer and the partialoxidation of the SiGe.

An overall picture of the interfacial properties of the samplesunder investigation is provided in Fig. 12a and b where the Dit values,estimated from the high–low method and from the conductancecharacteristics. The small difference in the Dit extracted from theconductance and the high–low method is typical.

The generation–recombination effects originate from levels closeto midgap and can be either interfacial or bulk traps. These twodifferent types of traps can be distinguished by the examination of the

Fig. 10. ln(fmax/T2) vs. 1/T Arrhenius plots of the conductance loss peaks of samples S2A(a) and S2D (b). (a) The Arrhenius plots correspond to three gate voltages, Vg=0 V atweak inversion, and at −0.1 V and −0.2 V at depletion. At weak inversion only one lossmechanism appears with activation energy of 0.58 eV attributed to generation effects. Atdepletion two lossmechanisms are present having activation energies 0.49–0.45 eV (peakA) and 0.37–0.4 eV (peak B). (b) For sample S2D the weak inversion loss mechanism(Vg=0 V) has the activation energy 0.53 eV, while at depletion (Vg=−0.14 V) themechanisms have activation energies 0.51 eV (peak A) and 0. 37 eV (peak B).

Fig. 12. Compiled results of the interface trap density extracted from the high–low C–Vmethod and the conductance analysis of peak B at room temperature (295 K) andat 333 K. The Arrhenius plot activation energy is also provided. (a) Sample S2B and(b) sample S2D.

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equivalent parallel conductance–voltage characteristics at the inver-sion regime [24]. When generation through interface traps dominatesthe loss, the conductance goes through a maximum as a function of

Fig. 11. Dependence of the interface trap density extracted from the analysis of the peakB as a function of the oxidation time at energy of Ev+0.4 eV. As long as the s-Sithickness remains the increase of the oxidation time results in an increase of theinterface trap density. As the s-Si layer is consumed the Dit reduces substantially.

bias in weak inversion and drops to a very low value at stronginversion. When bulk traps dominate the loss the conductance atweak and strong inversion is bias independent.

Fig. 13a and b show the Gp/ω–V characteristics of all samplesunder study at 1.6 kHz at room temperature (295 K) and at 344 Krespectively. At room temperature the G/ω–V characteristics exhibit astrong peak at theweak inversion region. This peak is attributed to themixed contribution of the generation and the interface trap responses.It indicates that interfacial traps are mainly responsible for thegeneration–recombination effects. Moreover, it suggests that theHill's method which is usually employed for the extraction of the Dit

cannot be applied with confidence in our case [13,25]. At stronginversion a constant component is evident which becomes strongerby increasing the oxidation time. The above picture changes as themeasurement temperature increases. At 344 K the constant compo-nent of the equivalent parallel conductance at strong inversionincreases steadily with the oxidation time. Therefore, the interfacetraps generation–recombination mechanism is dominant only for thecases of the shorter oxidation treatments (S2A, S2B). In addition, thepeak of sample S2B is higher than that of S2A. For sample S2C the twomechanisms have actually the same strength, and for the longestoxidation case the generation–recombination from bulk traps maskscompletely the interfacial generation mechanism. The significance ofthe conductance results is the qualitative manifestation of theconstant degradation of the material quality via the generation ofinterfacial and bulk defects with the increase of the thermal oxidationtreatment.

Fig. 13. Conductance–voltage characteristics of all oxidized samples recorded at(a) 295 K and (b) 344 K. The measurement frequency was 1.6 kHz in all cases. Thegraph shows the influence of the thermal oxidation extent to the carrier generationcharacteristics and thus to material quality. It is evident that the increase of theoxidation time creates significant amounts of bulk traps which dominate the G–V at thehighest temperatures.

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4. Discussion and conclusions

The presented experimental results of the oxidation of ultra-thins-Si layers on relaxed SiGe virtual substrates, under moderate to highthermal budget conditions indicate the following main outcomes:

a) The interface trap density increases with the oxidation time, as longas the s-Si layer remains between the growing thermal oxide andthe underlying SiGe substrate. Nevertheless, Dit undergoes asignificant decrease which approaches 40% between S2C and S2Dsamples. This indicates that the back s-Si/SiGe interface constitutes asignificant source of themeasured interfacial trapswhich contributein parallel with the defects located at the SiO2/s-Si interface. Theinfluence of the s-Si/SiGe interfacial defects to the C–V character-istics of oxidized ultra-thin s-Si layer MOS capacitors has beendemonstrated by simulation studies, which showed that locatingthe interface traps at the SiO2/s-Si or at the s-Si/SiGe interface couldreproduce the experimental C–V characteristics [26]. It is wellknown that the s-Si/SiGe interface is the main location of defectcreation upon strain relief of the silicon overlayer [27–29]. Duringhigh temperature annealing of s-Si/SiGe structures Ge out diffusesfrom the SiGe layer towards the s-Si, which results in an effectivereduction of the s-Si, while the s-Si/SiGe interface abruptnesssmears out substantially [9,30]. This process induces defects, sinceannealing experiments at 800 °C showed the formation of a deep-level center very close to the s-Si/SiGe interface, attributed to partial

relaxation of the s-Si layer [31]. High temperature thermal oxidationof ultra thin s-Si/SiGe intensifies the above processes due to the factthat the growing oxide gradually consumes the s-Si layer, whichbrings into close proximity the two interfaces. The out-diffused Geaccumulates at the SiO2 interface because it cannot be incorporatedwithin the growing oxide, leading to the generation of interfacialdefects [32–37]. In addition, the oxidation process injects largeamounts of Si interstitial atoms which may induce defects at thes-Si/SiGe interface or interact with pre-existing defects at the SiGeboundary. Our results indicate also a deterioration of the s-Si/SiGeinterface with the increase of the oxidation extent, as manifested bythe relaxation of the hole confinement ability. If the defects locatedat the s-Si/SiGe interface form a continuum of states, they willrespond as interfacial traps, since the bulk Fermi level will interceptthe defect band at a different energy position. The aboveconsiderations indicate that the concept of a defected s-Si/SiGeinterface could explain the Dit reduction when the s-Si layer isconsumed.

b) The density of interface traps across the bandgap, as extractedfrom the high–low C–V method, indicates a rather featureless andconstant Dit profile within the energy range Ev+0.35 to Ev+0.6 eV. Below Ev+0.35 eV the Dit show a rapid decrease, while theincrease above Ev+0.6 eV is attributed to generation effects.Similar results with a rather flat interface trap density within therange of Ev+0.3 to Ev+0.6 eV was also reported by C–V and byDLTS studies [30,31,34]. Furthermore, the interface traps havedifferent origin than those of the standard thermal oxidation of Si,since they could not be passivated by the forming gas annealingtreatment. Our previous results on oxidized ultra-thin s-Si layerson Si0.9Ge0.1 substrates showed that a 1% Ge accumulation at theSiO2/s-Si interface corresponds to a Dit of 1×1012 cm−2 eV−1,while 44% Ge accumulation at the SiO2/SiGe interface provides alower Dit value of 5.9×1011 cm−2 eV−1 [15]. In addition, thereduction of the Dit upon consumption of the s-Si layer is notaccompanied by a significant variation of the Dit profile, whichimplies that the s-Si/SiGe interface contribution to the measuredDit must have a relatively homogenous density within the energyrange of Ev+0.3 to Ev+0.6 eV. Moreover, the activation energythat was estimated from the temperature evolution of theconductance peak indicated that the signal arises from deepinterfacial traps located approximately at Ev+0.4 eV and arerather independent from the Ge content of the SiGe layer [15]. Theabove observation indicates that the defect characteristics of theexamined structures must have a common origin. Usually theformation of interfacial defects in oxidized ultra-thin s-Si/SiGestructures is attributed to the segregation of Ge atoms at the SiO2

interface where a part contributes to the generation of interfacialtraps. However, several DLTS studies either in s-Si/SiGe or in SiGestructures revealed broad spectra due to the presence of multiplepeaks arising from dislocations or dislocation related defects, inboth n and p type structures which constitute the most abundantdefect in the s-Si/SiGe materials system [10,38–40]. In the case ofp-type s-Si/SiGe the activation energy of the energy levels is foundwithin the range of Ev+0.25 to Ev+0.5 eV [9]. It has also beenreported that extended defects may form band like states [40].Considering these experimental results we do not exclude thepossibility of the contribution of the extended defects at the SiGeinterface to the measured interfacial defect density.

c) The analysis of the Gp/ω–f characteristics as a function oftemperature indicates that the energy location of the interfacialtraps lies within the energy range of Ev+0.37 to Ev+0.4 eV. Forthe case of lower Ge content virtual substrates i.e. Si0.9Ge0.1 theresults showed that the interfacial traps are located within thesame actual range of Ev+0.4 to Ev+0.44 eV [15]. This outcomesuggests that the interfacial defect formation does not dependstrongly on the Ge content of the virtual substrate.

5463V. Ioannou-Sougleridis et al. / Thin Solid Films 519 (2011) 5456–5463

d) The conductance analysis revealed very clearly that generationeffects dominate the capacitor behavior at the weak inversion anddepletion regions which in turn impose restrictions to theextraction of a correct interface density profile. These phenomenaarise from the relaxed Si0.78Ge0.22 layer with a correspondingenergy gap of 1.0 eV, yielding an intrinsic carrier concentration ni

at 300 K of 9.9×1010 cm−3, about 4 times higher than the siliconvalue [41]. The above justifies the presence of strong currents dueto carrier generation since the generation rate within the spacecharge region is proportional to ni. The increase of the oxidationtime enhances the generation–recombination phenomena of thecapacitors. The strong bulk generation phenomena which wereobserved at the temperature of 344 K for the case of the longestoxidation times indicates the strong influence of the prolongedhigh temperature treatment to the SiGe buffer layer which resultsin defect generation via the formation of bulk defects.

In conclusion, oxidation of ultra-thin s-Si films on SiGe virtualsubstrates, under moderate thermal budget conditions, leads to theformation of defect states not only at the at SiO2/s-Si interface but also atthe s-Si/SiGe interface. The close proximity of these interfacial defectsresults in a combined response from both interfaces upon externalelectrical excitation. Under prolonged thermal oxidation the s-Si layer istotally consumed and the interfacial trapdensity undergoes a significantreduction of 40%.

References

[1] M.T. Currie, C.W. Leitz, T.A. Langdo, G. Taraschi, E.A. Fitzgerald, D.A. Antoniadis, J.Vac. Sci. Technol. B 19 (2001) 2268.

[2] S.E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buechler, R. Chau, S. Cea, T.Ghani, G. Glass, T. Hoffman, C.-H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B.Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguygen, S.Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, Y. El-Mansy, IEEETrans. Electron Devices 51 (2004) 1790.

[3] M.L. Lee, E.A. Fitzgerald, M.T. Bulsara, M.T. Currie, A. Lochtefeld, J. Appl. Phys. 97(2005) 011101.

[4] S.H. Olsen, L. Yan, R. Agaiby, E. Escobedo-Cousin, A.G. O'Neil, P.E. Hellström, M.Ostling, K. Lyutovich, E. Kasper, C. Claeys, E.H.C. Parker, Microelectron. Eng. 86(2009) 218.

[5] L. Yan, S.H. Olsen, M. Kanoun, R. Agaiby, A.G. O'Neil, J. Appl. Phys. 100 (2006)104507.

[6] P. Somers, A. Stesmans, V.V. Afanas'ev, C. Clayes, E. Simoen, J. Appl. Phys. 103(2008) 033703.

[7] A. Nylandsted Larsen, Mater. Sci. Semicond. Process. 9 (2006) 454.[8] N. Sugii, J. Appl. Phys. 89 (2001) 6459.[9] L.H. Wong, C.C. Wong, K.K. Ong, J.P. Liu, L. Chan, R. Rao, K.L. Pey, L. Liu, Z.X. Shen,

Thin Solid Films 462–463 (2004) 76.[10] S.H. Olsen, A.G. O'Neil, P. Dodrosz, S.J. Bull, L.S. Driscoll, S. Chattopadhyay, K.S.K.

Kwa, J. Appl. Phys. 97 (2005) 114504.[11] D. Buca, B. Hollander, H. Trinkaus, S. Mantl, R. Carius, R. Loo, M. Caymax, H.

Schaefer, Appl. Phys. Lett. 85 (2004) 2499.[12] R. Loo, R. Delhougne, M. Caymax, M. Ries, Appl. Phys. Lett. 87 (2005) 182108.

[13] G.K. Dalapati, S. Chattopadhyay, K.S.K. Kwa, S.H. Olsen, Y.L. Tsang, R. Agaiby, A.G.O'Neil, P. Dobrosz, S.J. Bull, IEEE Trans. Electron Devices 53 (2006) 1142.

[14] H.C.-H. Wang, Y.-P. Wang, S.-J. Chen, C.-H. Ge, S.M. Ting, J.-Y. Kung, R.-L. Hwang,H.-K. Chiu, L.C. Sheu, P.-Y. Tsai, L.-G. Yao, S.-C. Chen, H.-J. Tao, Y.-C. Yeo, W.-C. Lee,C. Hu, IEEE 2003 Int. Electron Device Meet., Washington D.C., USA, December 8 10,2003, IEEE Tech. Dig., 2003, p. 61.

[15] V. Ioannou-Sougleridis, N. Kelaidis, C. Tsamis, D. Skarlatos, C.A. Krontiras, S.N.Georga, P. Komninou, B. Kellerman, M. Seacrist, J. Appl. Phys. 105 (2009) 114503.

[16] J. Maserjian, J. Vac. Sci. Technol. 11 (1974) 996.[17] C.G. Ahn, H.S. Kang, Y.K. Kwon, B. Kang, Jpn. J. Appl. Phys. I 37 (1998) 1316.[18] P.M. Mooney, S.J. Koester, H.J. Hovel, J.O. Chu, K.K. Chan, J.L. Jordan-Sweet, J.A. Ott,

N. Klymco, D.M. Mocuta, in: D.G. Seiler, A.C. Diebold, Th.J. Shaffner, R. McDonald, S.Zollner, R.P. Khosla, E.M. Secula (Eds.), 2003 International Conference onCharacterization and Metrology for ULSI Technology, Austin, U.S.A., March 2428, 2003, AIP Conf. Proc., 683, 2003, p. 213.

[19] K. Cai, C. Li, Y. Zang, J. Xu, H. Lai, S. Chen, Appl. Surf. Sci. 254 (2008) 5363.[20] S.P. Voinigescu, K. Iniewski, R. Lisak, C.A.T. Salama, J.P. Noel, D.C. Houghton, Solid

State Electron. 37 (1994) 1491.[21] A. Sareen, Y.Wang, U. Sodervall, P. Lundgren, S. Bengtsson, J. Appl. Phys. 93 (2003)

3545.[22] S. Chattopadhyay, K.S.K. Kwa, S.H. Olsen, L.S. Driscoll, A.G. O'Neil, Semicond. Sci.

Technol. 18 (2003) 738.[23] D.K. Schroder, Semiconductor Material and Device Characterization, 2nd ed.

Wiley, New York, 19988 p. 373.[24] E.H. Nicollian, J.R. Brews, MOS (Metal Oxide Semiconductor) Physics and

Technology, Wiley, New York, 19828 p. 218.[25] R. Mahapatra, S. Maikap, G.S. Kar, S.K. Ray, Solid State Electron. 49 (2005) 449.[26] N. Kelaidis, D. Skarlatos, C. Tsamis, Phys. Status Solidi C 5 (2008) 3647.[27] Y. Kimura, N. Sugii, S. Kimura, K. Inui, W. Hirasawa, Appl. Phys. Lett. 88 (2006)

031912.[28] X.L. Yuan, T. Sekigushi, S.G. Ri, S. Ito, Appl. Phys. Lett. 84 (2004) 3316.[29] X. Lu, R. Zhang, G. Rozgonyi, E. Yakimov, N. Yarykin, M. Seacrist, in: H. Huff, L.

Fabry, D. Gilles, U. Goesele, T. Hattori, W. Huber, S. Ikeda, H. Iwai, P. Packan, H.Richter, M. Rodder, E.Weber, R. Wise (Eds.), 209 Electrochemical Society Meeting,Denver, U.S.A. May 7–12, 2006, Electrochemical Society Trans., 22, 2006, p. 569.

[30] S.J. Koester, K. Rim, J.O. Chu, P.M. Mooney, J.A. Ott, M.A. Hargrove, Appl. Phys. Lett.79 (2001) 2148.

[31] R. Zhang, G.A. Rozgonyi, E. Yakimov, N. Yarykin, M. Seacrist, J. Appl. Phys. 103(2008) 103506.

[32] Y.J. Song, J.W. Lim, S.H. Kim, H.C. Bae, J.Y. Kang, K.W. Park, K.H. Shim, Solid StateElectron. 46 (2002) 1983.

[33] L.K. Bera, S. Mathew, N. Balasubramanian, G. Braithwaite, M.T. Currie, F.Singaporewala, J. Yap, R. Hammond, A. Lochtefeld, M.T. Bulsara, E.A. Fitzgerald,Appl. Surf. Sci. 224 (2004) 278.

[34] S. Chattopadhyay, L.D. Driscoll, K.S.K. Kwa, S.H. Olsen, A.G. O'Neil, Solid StateElectron. 48 (2004) 1407.

[35] D. Wang, M. Ninomiya, M. Nakamae, H. Nakashima, Appl. Phys. Lett. 86 (2005)122111.

[36] P.N. Grillot, S.A. Ringel, E.A. Fitzgerald, G.P. Watson, Y.H. Xie, J. Appl. Phys. 77(1995) 3248.

[37] P.N. Grillot, S.A. Ringel, E.A. Fitzgerald, G.P. Watson, Y.H. Xie, J. Appl. Phys. 77(1995) 676.

[38] V. Ligatchev, T.K.S. Wong, S.F. Yoon, J. Appl. Phys. 95 (2004) 7681.[39] J. Lu, Y. Park, G.A. Rozgonyi, J. Appl. Phys. 103 (2008) 073716.[40] W. Schroter, J. Kronewitz, U. Gnauert, F. Riedel, M. Seibt, Phys. Rev. B 52 (1995)

13726.[41] G. Eneman, E. Simoen, R. Delhougne, E. Gaubas, V. Simons, P. Roussel, P. Verheyen,

A. Lauwers, R. Loo,W. Vandervorst, K. DeMeyer, C. Claeys, J. Phys. Condens. Mater.17 (2005) S2197.