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Abstract— We study the design of different 6T and DICE SRAM blocks based on a commercial 65 nm CMOS technology and discuss the experimental results for X-ray, proton and heavy ion irradiation campaigns. The results obtained show that the number of affected bits depends not only on LET value, but also on the location of a strike. MCU patterns are discussed. The sensitive area is estimated as the whole SRAM cell area after deduction of the region between N+ and P+ guard rings. The results for normally incident particles clearly showed the advantages and trade-offs of different circuit and layout techniques.
Index Terms—SEU, SBU, MCU, DICE, critical charge,
SRAM, RHBD, heavy ions, protons, TID, CMOS, guard rings.
I. INTRODUCTION
IGH-DENSITY memory is very desirable for space applications. In modern deep-submicron technology the
total ionizing dose (TID) hardness is inherently high, and Single-Event Effects (SEE), e.g. Single-Event Latchup (SEL) and the Single-Event Upset (SEU), are the major problems for space CMOS microelectronic components [1], [2]. High radiation and fault tolerance can be achieved by process or by design [3]. The former approach is very effective but also very expensive. The latter is implementable on a standard high effective and low cost commercial technology.
One of the well-known and wide-spread design solutions improving SEU tolerance is dual interlocked cell (DICE) [4]. Unfortunately, they are vulnerable to SEU in sub-100 nm technologies due to small distance between two neighboring sensitive volumes. Nevertheless, 2-μm nodal spacing of all sensitive pairs helps to improve the SEU tolerance of such cells [5].
Manuscript received April 08, 2013. This work was supported in part by the Ministry of Education and Science
of Russian Federation under Contract No. 16.426.11.0040. M. S. Gorbunov, P. S. Dolotov, A. A. Antonov are with Scientific
Research Institute of System Analysis, Russian Academy of Sciences, 117218, Nakhimovsky prosp. 36/1, Moscow, Russia. (e-mail: [email protected], [email protected], [email protected]).
G. I. Zebrev and M. S. Gorbunov are with the Department of Micro- and Nanoelectronics of Moscow Engineering Physics Institute (National Research Nuclear University), Moscow, Russia (e-mail: [email protected]).
V. V. Emeliyanov is with the Research Institute of Scientific Instruments, Lytkarino, Moscow, Russia (e-mail: [email protected]).
A. B. Boruzdina, A. G. Petrov and A. V. Ulanova are with Specialized Electronic Systems (SPELS) and National Research Nuclear University (NRNU) “MEPHI”, Moscow, Russia (e-mail: [email protected]).
There are many solutions to increase the SEL immunity. The triple well (TW) or deep N-well (DNW) and guard rings [6] are implementable on a standard commercial technology and allow to reach SEL threshold linear energy transfer (LET) level ~ 60 MeV×cm2/mg and more. The main disadvantage of TW or DNW is possible increasing of SEU cross section due to multiple upsets in neighboring cells [7]. Multiple upsets in the same logical word (multiple-bit upsets, or MBUs) are uncorrectable by a simple error correction code (ECC) scheme and therefore it is important to decrease the number of such errors.
A number of publications show the increasing role of MBU or multiple-cell upsets (MCUs) in modern sub-100 nm technologies [8]-[11]. Particularly, the work [11] shows the comparison of SEE sensitivity of commercial SRAM based on different technology processes. It was recently reported in [12] about the development of a radiation-hardened 90 nm static random access memory (SRAM). Both radiation-hardening by process (RHBP) and by design (RHBD) techniques were used to improve the hardness of this memory.
In this work we present the experimental results for the test chip “TS5_RH65” with 4 different 2Kx64 SRAM blocks. The chip was irradiated by X-rays, 1 GeV protons and heavy ions at different electrical and temperature regimes. The main objective of the provided study is to compare performance and SEE characteristics of different design solutions applied to SRAM blocks fabricated with the same commercial process using standard technology options. Also, the cross-section values for high LET were compared to the cell’s layout. The sensitive area was estimated taking into account N+ and P+ guard rings. The layout dependence of MCU is discussed.
This paper is organized as follows: Section II describes the hardening methods applied to the designed SRAM blocks. The hardness assurance campaign plan is described in Section III. The experimental results are presented in Section IV and are discussed in Section V.
II. HARDENING METHODS APPLIED TO SRAM BLOCKS
The test chip was designed by the Scientific Research Institute of System Analysis (SRISA), Russian Academy of Sciences, and was fabricated by TSMC 65 nm bulk CMOS process. Chip area is 12 mm2. Nominal supply voltages (Vdd) are 1.0 V and 3.3 V for the core blocks and input/output (I/O), respectively. Conventional wire-bonding package was
Design of 65 nm CMOS SRAM for Space Applications: a Comparative Study
Maxim S. Gorbunov, Member, IEEE, Pavel S. Dolotov, Student Member, IEEE, Andrey A. Antonov, Gennady I. Zebrev, Vladimir V. Emeliyanov, Member, IEEE, Anna B. Boruzdina, Andrey G. Petrov,
Anastasia V. Ulanova
H
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provided and hence the silicon thinning was not needed for the cyclotron heavy ion testing.
SRAM blocks and different test structures were placed on the chip. Particularly, ring oscillators were used for the study of total dose effects. The ring oscillator is based on I/O circuits and consists of 7 stages. The first stage contains the input circuit and NAND gate providing “Enable” signal; another input of the NAND gate is used for the feedback. Other stages have the output and input circuits and the inverters. Thereby, the ring oscillator has both low-Vdd and high-Vdd transistors. Frequency divider based on D-flip-flops is placed at the output of the ring oscillator.
Tables I summarizes the main characteristics of the designed SRAM blocks. The “6T” is standard high density block with 6-transistor (6T) cell without any solutions for SEL prevention. The “6T_GR” is based on 6T cell with N+ and P+ guard rings. The “DICE_GR” block has solid guard rings and the “DICE” block has intermittent rings. The critical charge was estimated by SPICE modeling using well-known double exponential current source [13] with rise and fall time constants of 7 ps and 200 ps, respectively [14].
One can see from Table I that an alpha-particle can cause an upset in the designed 6T cells. As DICE-like cells are immune to ion strike to a single sensitive volume, the critical charge strongly depends on distance between neighboring sensitive volumes and other layout details. Thus, critical charge value was not calculated for such cells. Although one can not achieve a high precision simulation using the double exponential current source for advanced deep-submicron technologies, we use it for comparison and estimation.
TABLE I CHARACTERISTICS OF THE DESIGNED SRAM BLOCKS
Block name
Area, μm2 Guard rings
Estimated critical
charge, fC
Supply Current
Idd, mA
Access time, ns
6T 0.5 - 4 1.3 0.80 6T_GR
4 N+ and
P+ 10 2.5 3.3
DICE 8 - N/A 5.5 6.1 DICE_GR
8 N+ and
P+ N/A 5.5 6.1
Table I also shows the simulated access time for “typical-typical” corner (Vdd=1.0 V, T=25°C) and the measured supply current.
P-channel access transistors are used in all SRAM blocks, except “6T”, to eliminate the possibility of failure due to radiation-induced leakage current. Additionally, some design solutions are applied to protect the control circuits of all blocks, except “6T”, from Single-Event Transients (SET). The address decoders are duplicated and their outputs are connected to C-elements [15] to avoid undesirable SET. Reading control circuits are also duplicated and spatially separated. All latches, flip-flops and registers are based on DICE-cells. As such cells contain 2 copies of data, DICE-cells in flip-flops act as C-element. Sense amplifiers are based on clocked comparators and are not protected from SEU by design, but they are duplicated. If SET occurs in one of two
sense amplifiers, read error signal arises, which means that the read operation must be repeated.
Fig. 1 shows the fragments of memory arrays. Bit interleaving is used in all SRAM blocks, whereby successive bits in the same logical word are physically separated by interposing bits which are mapped to other logical words.
7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
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Bit # i+1 of the word # 0
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“6T”
“DICE”, “DICE_GR”
“6T_GR”
a)
b)
c) Fig. 1. Fragments of SRAM arrays showing the cell interleaving: a) “6T”, b) “DICE” and “DICE_GR”, c) “6T_GR”.
Successive bits in the same logical word are separated by 7 bits from other words in “6T” block (see Fig. 1a). “DICE” and “DICE_GR” have the same architecture and use the additional interleaving of the adjacent cells, i.e. the portion of one memory cell (e.g. a bit of the word number 4 shown in Fig. 1b) is physically laid out between and adjacent to portions of another memory cell (e.g. a bit of the word number 5 shown in Fig. 1b). Fig. 2 illustrates this interleaving concept.
Fig. 2. DICE cells with interleaving: layout and schematics. Information copies are highlighted by the dotted rectangles.
DICE cell contains information in 2 copies: “A” and “B”. There are also inverted values “AN” and “BN”. An error occurs when a charged particle affects both copies “A” and “B” (“AN” and “BN”) and when it strikes to PMOS from a copy and NMOS from its inverted counterpart. Interleaving leads to spatial separation of different information copies of a cell as shown in Fig. 1b. The nodal spacing of critical sensitive pairs in the particular layout is about 1.5-2 μm. These values are achieved using standard design rules and we were not forced to noticeably increase this distance. The nearest critical sensitive volumes correspond to the transistors separated by the guard rings (see Fig. 2).
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It is known that memory cells are sensitive to SEU during the reading cycle [16]. 8-transistor cells with combined row and column selection can be used to eliminate this effect [17]. In this case the half-selected cells do not enter the reading mode and their fault-tolerance is thus improved. The disadvantage of this method is the increase of total leakage current and bit-line capacitance. The DICE-cells are modified in the same manner in our work. Access and inverter’s PMOS transistors are also shown in Fig. 2; inverter’s NMOS transistors are not shown.
The design of “6T_GR” block is based on the design of the “DICE” block. The adjacent 6T cells are based on the DICE configuration, i.e. are interleaved. Let us consider the words number 4 and 5. One can see from Fig. 1c that there are 2 interposing transistors (2T) from the word number 5 between 2 pairs of transistors from the word number 4. The main drawback of this solution is higher probability of MCU, because a single charged particles striking to one of 2 pairs of transistors leads to charge sharing with transistors from the adjacent cell.
All logic gates, IO circuits and flip-flops were designed with 2 pairs of N+ and P+ guard rings. This solution drastically increases the area, but practically eliminates SEL in the core and the periphery even at very high LET and elevated temperature.
III. HARDNESS ASSURANCE CAMPAIGN
A. Test Equipment
Fig. 3 shows the special test equipment designed for the experiments. The test board includes device under test (DUT), FPGA, USB and JTAG interfaces.
Fig. 3. The test board with FPGA and DUT.
The area under DUT contains metalized holes for better heat transfer from the heater while testing at elevated temperature. The central hole is needed for the detectors in the vacuum chamber.
Each SRAM block, IO circuits and the core logic have separated power supply domains for current measurement. Therefore, it is possible to detect in which block SEL occurs. The on-board clock generator frequency is 10 MHz.
Fig. 4. The test board for the proton tests.
Fig. 4 shows the special test equipment designed for the proton experiments. The test board includes only device under test (DUT). The test equipment was located a few meters away from the beam to avoid failures in the equipment due to stray protons.
B. Test Plan
The data was written to the whole 64-bit logic word. The reading operation is organized byte by byte. One of four available types of patterns was set by FPGA: 0x5555_5555, 0xAAAA_AAAA, 0x0000_0000 or 0x1111_1111. Since the successive bits’ separation was used, there was no physical difference between the pairs of patterns: 0x5555_5555 and 0xAAAA_AAAA; 0x0000_0000 and 0x1111_1111. Therefore, the change of pattern during the irradiation session was not needed. The physical checkerboard pattern taking into account bits’ separation is not useful for “DICE”, “DICE_GR” and “6T_GR” blocks since the cells are relatively large and sensitive volumes are spatially separated. The results for the physical checkerboard could differ in “6T” block, but this case is not the worst, as one can see from the Section V-C.
Pattern 0x5555_5555 was written to all SRAM blocks during the SEU investigations. Due to separation of successive bits, all memory was thus divided to large regions with “1” and “0”. The width of these regions is from 8 (in “6T”, “DICE” and “DICE_GR” blocks) to 16 cells (in “6T_GR” block), as can be seen from Fig. 1. The tests of SRAM blocks consisted of sequential reading of the data and information verification by comparing 32 data bits to the reference 32-bit pattern located in external memory. When an error occurred, the address and data with timestamp of the erroneous logic word were written to the log-file. The time of data transfer from the test board to operator’s personal computer (PC) is relatively high: about few milliseconds per one erroneous logic word. As possible errors can be located in both 32-bit parts of a logic word, the data in memory was not overwritten after detection and the loss of information for upsets was avoided. At the same time it leads to enhanced time of data transfer to log-file. A possibility of striking several times to the same logic word during the experiment session is taken into account by means of comparing the data from the same address at 2 successive
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reading cycles. All SEU tests were provided at standard power supply (1.0 V for core voltage and 3.3 V for input/output (IO) circuits).
Pattern 0x0000_0000 was written to all SRAM blocks during the SEL investigations. No reading procedures were provided in this case to avoid influence of local voltage drop to SEL cross-section. All latchup tests were provided at higher power supply (1.1 V for core voltage and 3.6 V for IO circuits) at normal and elevated temperature. The same conditions were provided during X-ray irradiation.
Additional functional control was provided after X-ray irradiation at lower power supply (1.0 V for core voltage and 3.0 V for IO circuits). Static current measurements were provided at higher power supply.
The programmable power sources were used to protect the DUT from damage caused by possible catastrophic failures. These sources disconnect the block with enhanced supply current from the power domain and automatically reconnect power supply after normalization of a current.
Proton SEE tests were performed in a manner similar to heavy ion exposures. Pattern 0xAAAA_AAAA was written to all SRAM blocks during the SEU investigations. All SEU tests were provided at standard power supply and all SEL tests were provided at higher power supply.
C. Radiation Testing Equipment
The heavy-ion irradiations were provided by the Russian Federal Space Agency (Roscosmos) heavy ion’s facility IS 01-A based on the isochronous cyclotron U-400M of Flerov Nuclear Reaction Laboratory of Joint Institute for Nuclear Research (JINR), Dubna, Moscow region, Russia. It was operated by Specialized Electronic Systems company (SPELS), Moscow, Russia. A complete listing of the heavy ion beams used is shown in Table II. Heavy ions were used at normal incidence only. The fluence was varied from 8.5∙105 cm-2 to 1.6∙107 cm-2 depending on session (flux ~ 1000 cm-2∙s-1). Data are plotted using effective Linear Energy Transfer (LET) calculated using SRIM [18] taking into account metal layers. SEU and SEL effects were studied at room temperature. SEL was also investigated at elevated temperature (more than 85° C).
TABLE II HEAVY ION BEAMS PROPERTIES
Ion Energy, MeV Effective LET, MeV×cm2/mg
22Ne 81 7 40Ar 146 18 84Kr 269 41
136Xe 435 60
The TID irradiation was performed at the Specialized Electronic Systems (SPELS) and National Research Nuclear University “MEPhI” using “REIM-2” X-ray source with 10 keV mean photon energy and 50 keV maximum energy. The dose rate was 14 rad/s.
1 GeV proton SEE tests were performed at the Petersburg Nuclear Physics Institute (Gatchina, Leningradskaya region, Russian Federation). We provided 3 irradiation sessions: The
beam properties are shown in Table III. TABLE III
PROTON IRRADIATION SESSIONS PROPERTIES
Session Irradiation Flux,
×108 cm-2×s-1 1 backside 2.0 2 backside 1.1 3 frontside 1.3
Irradiation during the sessions 1 and 2 was provided from the backside. The third session was provided from the front side to estimate the role of metallization layers. Fluence for each session was about 1011 cm-2.
IV. EXPERIMENTAL RESULTS
6 chips were involved to the provided experiments: two were irradiated by heavy ions, another two were tested at protons accelerator and the rest two were irradiated by X-rays. All parts were decapsulated prior to tests.
A. SEU results
Fig. 5 shows SEU cross-section LET dependence for the SRAM blocks. Note that error cross-sections, not event cross-sections, are shown here. One can see from Fig. 5 that high-LET cross-section values for “DICE” and “DICE_GR” are about 3 orders of magnitude lower than cross-sections for “6T” and “6T_GR”. Despite the 2-μm nodal spacing of sensitive pairs, there are few upsets in DICE cells even at low LET values, but there are no MCU in such cells. There is negligible difference in cross-sections for cells with solid and intermittent guard-rings. High-LET cross-sections for “6T” and “6T_GR” are almost equal and are similar to obtained in [11]. Nevertheless, the characteristics of MCU in blocks with 6T cells deserve special attention.
Fig. 5. SEU cross-section LET dependence for SRAM blocks.
Fig. 6 shows the examples of upset maps for “6T” SRAM block for Xe. The cell “conglomeration” represents one event, or heavy ion strike. One can see that there are different kinds of SBU and MCU for single heavy ion: from 1-bit to 10-bit upsets. It is important to note that the largest area of cell “conglomeration” with upsets is about 2 μm × 2.5 μm. Let us estimate the charge collection length. It has two parts: the ion track radius (~ 50-100 nm [19]) and the diffusion length. The charge As it was shown in [5], 2 μm nodal spacing effectively improves SEU robustness of DICE cells. The generated
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electron-hole pairs are initially located within the ion’s track region and then, after the separation by the electric field, the charge spreads in all directions. Therefore, we can estimate that the diffusion length is about 1 μm. Now we can see that the side of obtained cell conglomeration is about twice as large as diffusion length plus the ion track diameter (~ 100-200 nm [19]). The vertical “elongation” of upset area is caused by rectangular 1 μm × 0.5 μm shape of 6T cell. This fact shows the significance of diffusion process in mechanism of MCU. We provide an additional discussion of the effective size of charge collection region in Section V-B. Fig. 7 shows the contribution of SBU and MCU in total event cross section for “6T” during heavy ion and the Session 1 proton test (see Table III).
Fig. 6. Examples of upset maps for “6T” SRAM block for Xe.
One can see that for low LET the “largest” MCU is 5-bit upset, and for the highest LET it is 10-bit upset. It is important to note that 9- or 10-bit upsets occur already at 40 MeV×cm2/mg. The percentage of 4-bit MCU practically does not change from 18 MeV×cm2/mg to 60 MeV×cm2/mg. Similarly, the percentage of 8- and 6-bit MCU does not change from 40 MeV×cm2/mg to 60 MeV×cm2/mg. This fact shows the importance of layout considerations and heavy ion strike location. Further discussion of the observed effect is provided in Section V.
Fig. 7. Contribution of SBU and MCU in total event cross section for “6T”.
Fig. 8 shows the contribution of SBU and MCU in total event cross section for “6T_GR” with the example of upset map for 2-cell upset. It also shows the results of proton irradiation during the Session 1. Unlike “6T”, only SBU and 2-bit MCU are found even at 60 MeV×cm2/mg.
It should be noted, that 2-bit upsets are found only in horizontally adjacent cells, which is caused mainly by 2-cell interleaving mentioned above. The rejection of such interleaving might lead to further decrease of the number of
MCU in 6T-based cells with guard rings.
Fig. 8. Contribution of SBU and MCU in total event cross section for “6T_GR” with example of upset map for 2-cell upset.
We did not find the SEU sensitivity dependence on the initial state (“0” or “1”) of a cell. Only SBU are detected in blocks based on DICE cells. Event cross-section is about 80% and 20% of the maximum error cross-section for “6T_GR” and “6T” SRAM blocks correspondingly. Due to successive bits separation, no MBU are detected in all blocks. Therefore, simple ECC scheme can be used to improve fault-tolerance of systems based on the considered SRAM blocks.
B. SEL results
No SEL is found at room temperature in all SRAM blocks at fluence not less than 1.4×.106 cm-2. SEL occurs in “6T” block only (at fluence not less than 2.2×.105 cm-2) at elevated temperature. Estimated cross-section for 60 MeV×cm2/mg is 4.6.10-4 cm2 for “6T”. It is interesting to mention that not only solid guard rings help to significantly enlarge the threshold LET for the latch-up effect (as can be predicted [6]), but also there is no SEL in the block with intermittent guard rings, too.
C. TID results
No functional failure in the considered blocks was observed until 1.2 Mrad (Si). After that the dose gaining was stopped. In “6T” block, the leakage current was increased by a factor of 5 due to the radiation-induced inter-transistor leakage in high density SRAM. Only 10% increase of leakage was detected in other blocks. The output frequency of test ring oscillator did not change.
D. 1 GeV Protons Results
No SEL is found at room temperature in all SRAM blocks at fluence ~ 1011 cm-2. All 3 sessions demonstrated qualitatively the same results with some quantitative differences.
The character of SEU and MBU distribution and upset maps is similar to heavy ion exposures. Only one 2-bit upset occurred in “DICE_GR” block during the Session 2. Other upsets detected in DICE cells were SBU. The number of upsets in DICE cells is about 2 orders of magnitude lower than in other types of cells. Only SBU and 2-bit MCU are found in “6T_GR” block for all sessions. The contribution of MCU in total event cross section is about 35% in “6T” block and about
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3% in “6T_GR” block. The largest MCU in “6T” block was 10-bit upset during the Session 1. There were no any events with more than 7-bit upsets in other two sessions. The occurrence of 10-bit MCU in “6T” and 2-bit upset in “DICE_GR” is most probably due to the secondary particles arising from recoil silicon ions passing the sensitive volume at large angles. The secondary particles arising from copper metallization layers or tungsten can be another reason. This is the subject for further investigations.
V. DISCUSSION
Different characteristics of observed MCUs need for some discussion. Technology-computer aided-design (TCAD) simulations would give the explanation of these effects, but the information about technology features (e.g., well depth, doping concentrations, etc.) are needed for simulations with high enough precision. Unfortunately, a designer using a commercial process design kit (PDK) usually does not have such information. Nevertheless, some general ideas based on known earlier presented data are provided below in order to explain the obtained results.
A. Layout versus Cross-section Consideration
The saturation cross-section in older technologies was correlated with the sensitive area of SRAM cells (usually, drain and gate area) [20], [21]. However, there is no saturation in sub-100 nm technologies due to MCU at LET ~ 60 MeV×cm2/mg and more. In this case it is practically impossible to determine such correlation.
The results obtained for “6T_GR” block has an “intermediate” position: its error cross-section versus LET curve does not have a saturation region due to 2-bit upsets, but it is relatively easy to estimate the maximum value of the event cross-section, which is close to the sensitive area value. The sensitive area is estimated as the whole SRAM cell area after deduction of the region between N+ and P+ guard rings. Thus, not only drains, but also sources and gates are the sensitive regions. The possible explanation of the observed effect is following. There are 2 well-known SEU mechanisms in modern CMOS technologies: diffusion process [10] and parasitic bipolar amplification [22]. Due to low value of critical charge, even the collected charge located near the source pn-junction and the junction between N-well and P-substrate is large enough to cause upsets. The bipolar amplification worsens the situation. The charge induced between the guard rings does not participate in SEU mechanism and flows to the ground and power supply bus.
B. SBU versus MCU
One can see from Fig. 7-8 that the amount of SBU constantly decreases while LET values increase. Fraction of the multiple upsets can be characterized geometrically by mean number of cells (sensitive volumes) covered by effective ion’s track cross section square [23]. Then, assuming statistical approach a fraction of multiple upsets (regardless of multiplicity) PMCU can be approximated as Poisson probability
201 expMCU collP N R , (1)
where N0 is density of the sensitive volumes per unit area, Rcoll is the effective size of charge collection region induced by ion’s track. Table IV shows the effective collection radius Rcoll as function of ion LETs calculated from data in Figs.7-8 for two blocks with different area 0.5 µm2 (“6T”) and 4 µm2 (“6T_GR”). Note that these calculations were made assuming that the whole cell is the sensitive volume.
TABLE IV EFFECTIVE COLLECTION RADIUS
Rcoll, μm Ion Effective LET, MeV×cm2/mg 6T 6T_GR
22Ne 7 0.32 0.11 40Ar 18 0.45 0.35 84Kr 41 0.55 0.51
136Xe 60 0.50 0.59
One can see that the Rcoll values for different blocks are close to each other for high LET values. In this case the effective collection area is comparable with the cell area. The discrepancies at low LET are caused by too small number of MCU events and by the increased probability of 2-bit upsets due to 2-cell interleaving in “6T_GR” block.
C. Layout versus MCU Consideration
Let us consider the simplified layout of SRAM cell used in “6T” block (see Fig. 9). Gray stripes represent polysilicon gates, hatched rectangles are NWELLs. Light grey and black rectangles are sources and drains of “on”-state and “off”-state transistors correspondingly. Dashed rectangles show the cells’ margins. Dotted circles represent heavy ion tracks.
Fig. 9. Simplified layout of SRAM cell used in “6T” block.
Generated electron-hole pairs can recombine or be separated by electric field. The effectiveness of the separation increases in higher electric fields. The generated near the source charges can partially recombine and partially flow to the ground and supply bus. But due to the small critical charge (see Table I) the rest amount of charge could be enough to cause upset in one or two cells, depending on the LET, track radius and the location of strike (see circles number “1” and “4” in Fig. 9 and the first 2 upper-left fragments in Fig. 6). In fact, due to the layout features of “6T” block, the occurrences of single and double upsets have practically equal probability. The sum of single and double upsets is approximately equal (see Fig. 7).
If an ion strikes the region in N-well (see circle number “2” in Fig. 9), it inevitably affects one or two drains of “off”-state transistors. It leads to charge spreading in vertical directions
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within N-well and to upsets in several (from 2 to 5) vertically adjacent cells (see upper fragments in Fig. 6). If an ion strikes the central region in Fig. 9 (see circle number 3), it affects 2-4 drains of “off”-state transistors. The amount of charge is relatively high and the diffusion process spreads it to 4-10 adjacent cells (see lower fragments in Fig. 6). Therefore, the number of affected bits depends not only on LET value, but also on the location of a strike.
Note that in the case of physical checkerboard pattern there is no any region with more than 2 drains of “off”-state transistors located near each other (see Fig. 9). Thus, this type of pattern is not the worst case.
It is interesting to compare obtained results with those obtained by Uznanski, Gasiot, Roche, et al. for ST Microelectronics technology [10], [11]. For high density SRAM (~0.5 μm2 per cell) the maximum upset cross-section is ~10-8 cm2/bit which is comparable with the results presented in current work. Unlike presented results with dominant 3-8 bit MCU at 40 MeV×cm2/mg , 3- and 4-bit upsets are the major part of MCUs in STM results at 34 MeV×cm2/mg. Therefore, the SEE sensitivity results are not fully portable from one technology to another not only due to the different layout, but also due to different doping profiles, parameters of parasitic bipolar structures and devices geometry. The SEE elimination strategy must be chosen based on the results for the used technology.
D. Irradiation at Tilted Angles
The obtained results clearly show that the bit separation technique is capable to avoid the MBUs at normal ion’s incidence, while even 10-bit MCUs are observable. At the same time, the tilted ion strikes can further increase the multiplicity of the upsets.
The worst cases for the designed blocks in sense of azimuth incidence are obvious from simple layout considerations. The “vertical” ion passage (in the Y-direction) is the worst case for “6T” block (see Fig. 9). The “horizontal” (in the X-direction) passage can play a significant role only at high polar angles (60° and more) when an ion passes through several sensitive volumes. As the nodal separation is horizontal (see Fig. 1), the MBU events can be observed in this case.
The “horizontal” passage is the worst case for “6T_GR”, “DICE” and “DICE_GR” blocks, because the sensitive volumes are separated in horizontal direction. An increase of the MCU multiplicity and a number of MBUs can be observed in this case.
Generally, since the area of “6T_GR” cell is 8 times larger than the “6T” cell area, the “angle-induced” increase of the error cross-section for the former block would be as large as that for the higher technology node circuits. The error cross section for DICE would significantly increase by 1-2 orders of magnitude (as shown in [5]), because an ion would strike two sensitive volumes simultaneously.
VI. CONCLUSION
The design of different SRAM blocks based on a
commercial 65 nm CMOS technology is presented. The experimental results for X-ray, proton and heavy ion irradiation campaigns are discussed. DICE cells demonstrate about 2-3 orders of magnitude lower than cross-sections for 6T-cells due to the 2-μm nodal spacing of sensitive pairs. Solid and intermittent guard rings has high effectiveness in SEL elimination. High TID tolerance (more than 1.2 Mrad (Si)) is demonstrated.
The main conclusions are the following. The comparison of different RHBD techniques is provided for SRAM blocks manufactured at the same chip. The cross-section value for high LET is compared to the cell’s layout. The sensitive area is estimated as the whole SRAM cell area after deduction of the region between N+ and P+ guard rings. The number of affected bits depends not only on LET value, but also on the location of a strike. MCU patterns are discussed. The results for normally incident particles clearly showed the advantages and trade-offs of different circuit and layout techniques.
ACKNOWLEDGMENT
The authors wish to thank the colleagues at Scientific Research Institute of System Analysis Alexander Zadorozhniy, Anastasia Vetoshkina, Pavel Monahov, Artemiy Zuikov, Boris Vasilegin, Andrey Ivlev, Valeriy Shunkov, Pavel Osipenko and Alexander Asonov for discussions and design of the test system. We also wish to thank Alexander Chumakov and Andrey Yanenko (Specialized Electronic Systems) for discussions about strategy of the experiment and about the results.
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