Gujarat Technological University

Ahmedabad

&

C-DAC, Pune

M.E (Electronics & Communication Engineering)

In

VLSI & Embedded System Design (sem-1)

En No-160930359011

Inter-Process Communication using

Pipes in FPGA-based Adaptive

Computing

Presented by

Mayur Shah

What is Inter Process Communication ?[1]

Exchange of data between two or more separate, independent processes/threads.

Operating systems provide facilities/resources for inter-process communications (IPC), such as message queues, semaphores, and shared memory.

Distributed computing systems make use of these facilities/resources to provide application programming interface (API) which allows IPC to be programmed at a higher level of abstraction. (e.g., send and receive)

Distributed computing requires information to be exchanged among independent processes.

Figure Of Inter Process Communication

Process 1 Process 2

data

sender receiver

IPC Mechanisms

Signals

Pipes

FIFOs

Message Queue

Shared memory

Purposes for IPC

Data Transfer

Sharing Data

Event notification

Resource Sharing and Synchronization

Process Control

What is pipe?

Pipe which allow transfer data between processes in First in-

First-out manner.

A pipe is usually realized in memory.

Pipe operations are memory operations.

Create a Pipeline

Sometimes useful to connect a set of processes in a pipeline.

Process

cProcess

DPipePipe

Process A writes to pipe AB, Process B reads from AB and

writes to BC

Process C reads from BC and writes to CD …..

Field Programmable Gate Array

It is primarily a semiconductor device that can be configured by the user (customer or designer) after the manufacturing process has been completed

The term "field-programmable" means the device is programmed by the customer, not the manufacturer.

Can be programmed using a logic circuit diagram or source code in VHDL or Verilog.

It offers partial re-configuration of a portion of design.

General Figure of FPGA

Logic blocks

to implement combinational

and sequential logic

Interconnect

wires to connect inputs and

outputs to logic blocks

I/O blocks

special logic blocks at periphery

of device for external connections

Adaptive Computing

Adaptive computing refers to the capability of a computing system

to adapt one or more of its properties (e.g. performance) during

runtime.

There are diverse reasons of why it is advantageous for a computing

system to adapt during runtime and there are various enabling

techniques and paradigms that allow a computing system to perform

such an adaptation.

Now We starting our main topic ………….

Inter-Process Communication using Pipes in FPGA-based

Adaptive Computing

Abstract:-

In FPGA-based adaptive computing, Inter-Process Communications

(IPC) are required to exchange information among hardware processes

which time multiplex the resources in a same reconfigurable region.

Adaptive computing based on FPGA Partial Reconfiguration (PR)

technologie tailors various computation algorithmes to ambient

conditions during system run-time. It intelligently manages on-chip

computing resources and improves their utilization efficiency .

In contrast to conventional static configuration of FPGAs, PR

provides the technical support for changing only a particular section

of an FPGA design, while the remaining system is still in operation.

Analogous to software multiprogramming on CPUs, the PR

technology enables multitasking on limited FPGA resources by

dynamically configuring or unloading processing modules according

to computation requirements. In this context, each processing module

is treated as a hardware process for one specific algorithm.

Now Introduction

IPC QUEING MODEL

Static Process Model

Pipes and FIFOs (Also called named pipes. We use pipe as the general name.)

are a basic IPC mechanism provided in all flavors of Unix OSes. They are best

suited to implement producer-consumer interactions among processes.

A pipe is a unidirectional channel: All data written by a process to the pipe is

routed by the OS kernel to another process which can thus read it .In FPGA-based

designs, hardware pipes behave in an analogous manner as the software ones in

Oses.

(Figure 1) shows consecutive pipe communications between algorithm

modules. Conventionally all algorithm processors or algorithm steps are

statically placed on the FPGA fabric. They work in parallel to process

their respective input data streams, possibly generate output results, and

pass IPC information to the next computation stage. In this model,

intermediate pipes with buffering capability decouple and coordinate

producers and consumers, if they do not generate and consume data at the

same pace.

Re-configurable Process Model

In adaptive computing scenarios in which multiple algorithm processors or

algorithm steps timeshare the same resources in one PR Region (PRR), pipes can

be used to bridge the communication of two modules activated at different time.

In Figure 2, a reconfigurable design is demonstrated with the same dataflow as

the static algorithm placement shown in Figure 1: Algorithm modules are

sequentially loaded into the PR region for a period of time. They read and

consume data from the previous-stage pipe, and store the generated inter-module

information in the current-stage pipe for next-stage computation. For example

after activated, algorithm A1 reads IPC packets of A0 from pipe0, and

passinformation to A2 via pipe1.

• Pipes can be implemented with

• BRAM on Xilinx Virtex-4 FPGA

• External DDR memory

M. Liu, Z. Lu, W. Kuehn, S. Yang, and A. Jantsch,"A Reconfigurable Design Framework for FPGA Adaptive Computing“, ReConFig’09.

HARDWARE IMPLEMENTATION

DDR_pipe:

The complete system architectureFPGA adaptive computing [1]

• Embedded microprocessor

(scheduler)

• Memory (partial bitstream storage)

• HWICAP for PR

Conclusion

The latency of IPC packets is expected to be reduced with

more intelligent mechanisms, and to be properly coordinated

with throughput requirements in realtime applications.

Reference

.1. ipc using pipe in fpga adtive computinghttps://www.google.com.sg/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&cad=rja&uact=8&ved=0ahUKEwivuNm46tXPAhVMNY8KHU3cBt8QFggiMAE&url=http%3A%2F%2Fpeople.kth.se%2F~mingliu%2Fpublications%2Fisvlsi.pdf&usg=AFQjCNHrXxzujLetB6rt_lVIcY5Be53bVw&sig2=QknRCLRS3W8mus0v3vJLig&bvm=bv.135475266,d.c2I2. ipchttps://www.google.com.sg/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&sqi=2&ved=0ahUKEwi6wp-d69XPAhVELI8KHWhgDaoQFggaMAA&url=http%3A%2F%2Fcs.gmu.edu%2F~yhwang1%2FSWE622%2FSlides%2FIPC.ppt&usg=AFQjCNEmVM6Hulc8KHty_Ws4_d25fp5Hig&sig2=hGeYLuamFJGVZD4D0C0yMA&bvm=bv.135475266,d.c2I3. ipc using pipehttps://www.google.com.sg/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&cad=rja&uact=8&ved=0ahUKEwiu79bH69XPAhXDtI8KHQbMB8sQFgggMAE&url=http%3A%2F%2Fwww.cs.fsu.edu%2F~xyuan%2Fcop4610%2Flecture_6_osinterface4.ppt&usg=AFQjCNH9xpXqX1FLfvCPiDcHFz3KnGhEZQ&sig2=PRFlyBr8RnehonF4TCelVA&bvm=bv.135475266,d.c2I

3.2https://www.google.com.sg/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&cad=rja&uact=8&ved=0ahUKEwiu79bH69XPAhXDtI8KHQbMB8sQFgggMAE&url=http%3A%2F%2Fwww.cs.fsu.edu%2F~xyuan%2Fcop4610%2Flecture_6_osinterface4.ppt&usg=AFQjCNH9xpXqX1FLfvCPiDcHFz3KnGhEZQ&sig2=PRFlyBr8RnehonF4TCelVA&bvm=bv.135475266,d.c2I4. adptive computinghttps://www.google.com.sg/url?sa=t&rct=j&q=&esrc=s&source=web&cd=4&cad=rja&uact=8&ved=0ahUKEwiH8_L959XPAhUBsY8KHeeSAAYQFgg5MAM&url=http%3A%2F%2Fwww.diva-portal.org%2Fsmash%2Fget%2Fdiva2%3A418205%2FFULLTEXT01.pdfAdaptive&usg=AFQjCNFvnAiqgy6XEdUTifSQmdGJdIijtQ&sig2=uriWwwdTeAfmcub9ISpXtg