Design of CMOS Inverter for Low Power and High Speed using Mentor Graphics

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

71 NITTTR, Chandigarh EDIT-2015

Design of CMOS Inverter for Low Power andHigh Speed using Mentor Graphics

1Rachna Manchanda, 2Chanpreet Kaur1,2Assistant Professor

1,2Department of Electronics and Communication, CEC landran1Cecm.ece.rm@gmail.com, 2cecm.ece.ctoor@gmail.com

ABSTRACT:- In parallel with enhancements in thetechnology low power consumption have emerged as aprimary design constraint in digital VLSI. This is due tothe increasing demand of portable battery operateddevices in the VLSI circuit design. This really implies aneed to balance ultra low power with area efficient design.So the only way to minimize energy per operation is todecrease VDD. The inverter is designed using 25nmtechnology in mentor graphics is presented. Further thedesigning is followed by the layout of the inverter is donein this paper.

KEYWORDS: Mentor Graphics, Pyxis Schematic, ELDO,Pyxis layout, Delay, temperature, Rise time, fall time.

INTRODUCTIONThe level of integration keeps on growing more andmore refined as signal processing systems getimplemented on a Very Large Scale Integration (VLSI)chip. The CMOS technology has emerged as apredominant technology in the field of nano electronics.As the technology become compact there is rapidincrease in demand of high performance and also lowpower digital systems [1]. These signal processingapplications demands great computation capacity andconsume considerable amounts of energy. While theperformance and the area remain to be two majordesign issues, power consumption has become a criticalconcern in today’s VLSI system designing. The powerconsumption of a design determines how much energyis consumed per operation and much heat the circuitdissipates [1].These above given factors influence a great number ofdemanding design decisions, such as the power-supplycapacity, supply-line sizing, packaging, the batterylifetime and cooling requirements. Digital circuits inVLSI design have become more advent in recent yearsbecause of its large amount of applications. So there isneed to develop low power design methodologies todesign these circuits.Propagation delay and power dissipation are two majorissues for the design & synthesis of any VLSI circuitsin this range [2]. Power dissipation limitations come intwo ways. The first is related to cooling applicationswhen the implementation of high performance systemsis to be done. The high speed circuits dissipate verylarge amount of energy in a very short amount of timeand generating a great amount of heat. This heat needsto be removed by the package on which integratedcircuits are mounted. The second failure of high-powercircuits relates to the increasing popularity of portableelectronic devices. Laptop computers, compact video

players and cellular phones all use batteries as a powersource [3].To extend the battery life, low power operation is needed inintegrated circuits. This paper briefly presents the concept ofeffect of temperature and delay at different voltages at 25nm technology in mentor graphics.

CHARACTERISTICS OF CMOS

CMOS circuits are made in such a way that all thePMOS transistors known as pull up networks are alwaysconnected to the voltage source or from another PMOStransistor. On the same hands all NMOS transistors knownas pull downs are having either an input from ground orfrom another NMOS transistor [4]. The PMOS transistor isdesigned in such a way that it createslow resistance between its source and drain contacts, when alow gate or negative voltage at the gate of the PMOStransistor and high resistance when a high gate voltage orpositive voltage is applied.On the other hand, the NMOS transistor creates highresistance between its source and drain contacts, when a lowgate or negative voltage is applied and low resistance whena high gate or positive voltage is applied.CMOS accomplishes the current reduction bycomplementing every nMOSFET with a pMOSFET andconnecting both gates and both drains together. A highvoltage on the gates of transistor will cause the nMOSFETto be in conducting state and the pMOSFET to be in nonconducting state, while a low voltage on the gates causes thereverse operation. This will reduces the power consumptionand heat generation. Therefore, during the switching timeboth MOSFETs will conducts as the gate voltage changesfrom one state to another [5]. This induces a spike in powerconsumption and becomes a serious issue at highfrequencies.

INTRODUCTION DESIGN STEPS TO MENTORGRAPHICS TOOL

The Mentor Graphics HEP2 tools for the flow of the FullCustom IC design cycle is used. It will run the DRC, LVSand Parasitic Extraction on all the designs. Initial step is tocreate a schematic and attach the technology library called“TSMC025”.Other options for choosing the library are also included.Adding a technology library will ensure that the design canbe done on front to back design. A new cell called“Inverter” with schematic view is designed a01nd hencebuild the inverter schematic by initializing variouscomponents. Once the inverter schematic is done, symbol

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

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for “Inverter” is generated. Now it will create a newcell view called “Inverter1”, here it will instantiate“Inverter” symbol. This circuit is verified by doingvarious simulations using ELDO.In the process EZviewer will show the waveformwindow options, waveform calculator, etc... The PyxisLayout Editor is based on concentrating the design an“Inverter” through automatic layout generation, withcompleting the other layouts, generating steps, GDSIIfile. After that, by taking GDSII file as reference it willrun DRC, LVS checksum the layout, Extract parasiticand back-annotate them to the simulation environment.

SCHEMATIC OF INVERTER

In this paper, Schematics of inverter are drawn and thesimulations are performed by ELdo simulator in pyxisSchematic. Eldo provides the most advanced simulationtechnology and provides extensive simulationcapabilities.

Fig 2- Schematic view of inverterIts advanced various analysis can be performed like DCanalysis, transient analysis, DC mismatch, sensitivity,aging analysis, optimization of parameters, distributedcomputing, multi-threading, RC reduction, pole-zero,Monte-Carlo analysis, distributed computing, S-parameters, S-domain and Z-domain transfer functionscan be obtained.Here a 4 pin P-MOS and N- MOS Transistor are usedin pyxis schematic as shown in fig 2. Here VDD isattached to the P-MOS inverter and ground is attachedto N-MOS inverter.

Fig 3- schematic view of inverter symbol with a pulse input and a DCsource

In fig 3 a symbol is generated of CMOS inverter and apulse is applied to the input port of inverter. Pulse is of3 V and period of pulse is 50ns is set. Similarly a DCvoltage of 1.1 to 3 V is applied to the VDD of inverter.

SIMULATION RESULT

Here are the simulation results of the inverter. Fig 4 isthe DC simulation result of inverter. V(a) shows thegraph of the input to the inverter is starting from zero tothe final value of 3V, and V(y) Shows in below figurethat output is inverted from 3 V to 0V.

Fig 4- DC Simulation result of inverter

Another simulation result is for the transient response of theinverter both for the input and the output of the inverter asshown in fig 5. Here it is observed that output of the inverteris inverted. Here V(y) is the output of the inverter and V (a)is the input to the inverter.

Fig 5- Simulated output of the inverter

PRACTICAL OBSERVATIONS

Calculation of power dissipation, delay, fall time, rise timeis observed for the Simulation results under 27 degreestemperature as mentioned in table 1 given below.

Table 1- Various parameters using different VDD

VDD POWERDISSIPATION

DELAY FALLTIME

RISETIME

3V 13.9997PATTS

21.165ns 133.36ps

239.54ps

1.5V 2.1273PWATTS

21.310ns

87.683ps

181.57ps

1.3 V 2.8832PWATTS

21.381ns

81.790ps

127.82ps

1.1 V 2.1273PWATTS

21.447ns

63.853ps

97.420ps

From the table 1 it is observed that power dissipation ofinverter is reduced as VDD is reduced from 3V to 1.1 V.Delay is also calculated for various applied voltages. Thefall time and Rise time of output waveform is also reducedfor the when VDD is decreased.

PYXIS LAYOUT FOR INVERTER

The same design of inverter is being implemented on pyxislayout in mentor graphics as shown if figure 5. Layout is thefabrication mask of the design for IC manufacturing.For the low power and high speed inverter design, Layout isdrawn using these following layers - Nwell layer, P

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

73 NITTTR, Chandigarh EDIT-2015

diffusion, N diffusion, poly silicon, vias, and metal 1contact.

Fig 5 - Inverter layout on pyxis layout tool

CONCLUSION

The proposed design shows low power, high speedinverter by using TSMC025 is done. Here the power isdissipation is less for low voltages as well as fall time,rise time is also reduced. Further the inverter layout isalso designed using DRC and LVS tools.

REFERENCES[1] Adil Zaidi, Kapil Garg, Ankit Verma, Ashish Raheja“Design & Simulation of CMOS Inverter at Nanoscalebeyond 22nm “ in International Journal of Emerging Scienceand Engineering (IJESE) ISSN: 2319–6378, Volume-1, Issue-5, March 2013 ,Pages: 83-87.[2] Srinivasa Rao.Ijjada, S.V.Sunil Kumar, M. Dinesh Reddy,Sk.Abdul Rahaman, Dr.V. Malleswara Rao, “DESIGN OFLOW POWER AND HIGH SPEED INVERTER,” (IJDPS)Vol.2, No.5, September 2011, pages: 127-134.[3] Jagannath Samanta, Bishnu Prasad De, Banibrata Bag, RajKumar Maity “Comparative study for delay & powerdissipation of CMOS Inverter in UDSM range “ inInternational Journal of Soft Computing and Engineering(IJSCE) ISSN: 2231-2307, Volume-1, Issue-6, January 2012 ,pages: 162-167.[4] K. Roy, S. Mukhopadhyay, H. Mahmoodi-Meimand,“Leakage Current Mechanisms and Leakage ReductionTechniques in Deep-Submicrometer CMOS Circuits,”Proceedings of the IEEE, vol. 91, no. 2, Feb. 2003, pages:305-327.[5] CMOS VLSI Design, NEIL H.E. WESTE, IEEE 2006.