MPMC Unit-1

The 8085 Bus Structure

The 8-bit 8085 CPU (or MPU – Micro Processing Unit) communicates with the other units using a 16-bit address bus, an 8-bit data bus and a control bus.

The 8085 Bus Structure

Address Bus

Consists of 16 address lines: A0 – A15

Operates in unidirectional mode: The address bits are always sent from the MPU to peripheral devices, not reverse.

16 address lines are capable of addressing a total of 216 = 65,536 (64k) memory locations.

Address locations: 0000 (hex) – FFFF (hex)

The 8085 Bus Structure Data Bus

Consists of 8 data lines: D0 – D7

Operates in bidirectional mode: The data bits are sent from the MPU to peripheral devices, as well as from the peripheral devices to the MPU.

Data range: 00 (hex) – FF (hex)

Control Bus

Consists of various lines carrying the control signals such as read / write enable, flag bits.

The 8085: CPU Internal Structure

The internal architecture of the 8085 CPU is capable of performing the following operations:

Store 8-bit data (Registers, Accumulator)

Perform arithmetic and logic operations (ALU)

Test for conditions (IF / THEN)

Sequence the execution of instructions

Store temporary data in RAM during execution

Simplified block diagram

The 8085: Registers

Registers

Six general purpose 8-bit registers: B, C, D, E, H, L

They can also be combined as register pairs to perform 16-bit operations: BC, DE, HL

Registers are programmable (data load, move, etc.)

Accumulator

Single 8-bit register that is part of the ALU !

Used for arithmetic / logic operations – the result is always stored in the accumulator.

Flag Bits

Indicate the result of condition tests.

Carry, Zero, Sign, Parity, etc.

Conditional operations (IF / THEN) are executed based on the condition of these flag bits.

Program Counter (PC)

Contains the memory address (16 bits) of the instruction that will be executed in the next step.

Stack Pointer (SP)

Features of 8086Features of 8086

- 8086 is a 16 bit microprocessor, It can - 8086 is a 16 bit microprocessor, It can perform read & write operation on both 8 or perform read & write operation on both 8 or 16 bit data..16 bit data..- 8086 has 16 bit data bus & 20 bit address - 8086 has 16 bit data bus & 20 bit address bus. bus.

Features of 8086 ( continued)Features of 8086 ( continued)

- 20 bit address lines capable of addressing - 20 bit address lines capable of addressing 1MB memory location1MB memory location- 16 bit data are stored in 2 consecutive - 16 bit data are stored in 2 consecutive memory locationsmemory locations- 8086 can generate 16 bit I/O address , 256 - 8086 can generate 16 bit I/O address , 256 = 65536 I/O ports= 65536 I/O ports

Features of 8086 ( continued)Features of 8086 ( continued)

- 8086 has fourteen 16 bit registers- 8086 has fourteen 16 bit registers - 8086 has multiplexed address & data bus- 8086 has multiplexed address & data bus- 8086 operates in 2 modes , minimum( single - 8086 operates in 2 modes , minimum( single processor )processor ) & maximum( multi processor) modes & maximum( multi processor) modes

- 8086 has 6 byte prefetch instruction Queue- 8086 has 6 byte prefetch instruction Queue

Registers OrganisationRegisters Organisation• 16-Bit General Purpose Registers

– can access all 16-bits at once– can access just high (H) byte, or low (L) byte

only the GeneralPurpose registersallow access as8-bit High/Lowsub-registers

Registers Organisation (continued)Registers Organisation (continued)

• Register Set16-Bit Segment Addressing Registers

CS Code SegmentDS Data SegmentSS Stack SegmentES Extra Segment

16-Bit Offset Addressing RegistersSP Stack PointerBP Base PointerSI Source IndexDI Destination Index

16-Bit Control/Status Registers- IP Instruction Pointer (Program Counter

for execution control)- FLAGS 16-bit register• It is not a 16-bit value but it is a

collection of 9 bit-flags (six are unused)• Flag is set when it is equal to 1• Flag is clear when it is equal to 0

ArchitectureArchitecture

Architecture (continued)Architecture (continued)

• The 8086 has two parts, the Bus Interface Unit (BIU) and the Execution Unit (EU).

• The BIU fetches instructions, reads and writes data, and computes the 20-bit address

• The EU decodes and executes the instructions using the 16-bit ALU.

• The BIU contains the following registers- IP - the Instruction Pointer

- CS - the Code Segment Register- DS - the Data Segment Register- SS - the Stack Segment Register- ES - the Extra Segment Register

• The BIU fetches instructions using the CS and IP, written CS:IP, to construct the 20-bit address. Data is fetched using a segment register (usually the DS) and an effective address (EA) computed by the EU depending on the addressing mode

• The EU contains the following 16-bit general purpose registers:

» AX - the Accumulator» BX - the Base Register» CX - the Count Register» DX - the Data Register» SP - the Stack Pointer \ defaults to» BP - the Base Pointer / Stack segment» SI - the Source Index Register» DI - the Destination Register

HIGH BYTE GP REGISTERS LOW BYTE

AHBHCHDH

AXBXCXDX

ALBLCLDL

8 BIT 16 BIT 8 BIT

Architecture (continued)Architecture (continued)ESCSSSDSIP

AHBHCHDH

ALBLCLDL

SPBPSIDI

AXBXCXDX

Extra SegmentCode SegmentStack SegmentData SegmentInstruction Pointer

AccumulatorBase RegisterCount RegisterData RegisterStack PointerBase PointerSource Index RegisterDestination Index Register

BIU registers

(20 bit adder)

EU registers

16 bit arithmetic

General purpose RegistersGeneral purpose Registers

• AX – Accumulator Register – Preferred register to use in arithmetic, logic and

data transfer instructions because it generates the shortest Machine Language Code

– Must be used in multiplication and division operations

– Must also be used in I/O operations

General purpose Registers (conti..)General purpose Registers (conti..)

• BX– Base Register– Also serves as an address register– Used in array operations– Used in Table Lookup operations (XLAT )

General purpose Registers (conti..)General purpose Registers (conti..)

• CX– Count register– Used as a loop counter– Used in shift and rotate operations

• DX– Data register– Used in multiplication and division– Also used in I/O operations

Pointer & Index RegistersPointer & Index Registers

• Contain the offset addresses of memory locations

• Can also be used in arithmetic and other operations

• SP: Stack pointer – Used with SS to access the stack segment

Pointer & Index Registers (continued)Pointer & Index Registers (continued)

• BP: Base Pointer– Primarily used to access data on the stack– Can be used to access data in other segments

• SI: Source Index register– is required for some string operations– When string operations are performed, the SI

register points to memory locations in the data segment which is addressed by the DS register. Thus, SI is associated with the DS in string operations.

Pointer & Index Registers (continued)Pointer & Index Registers (continued)

• DI: Destination Index register – is also required for some string operations.– When string operations are performed, the DI

register points to memory locations in the data segment which is addressed by the ES register. Thus, DI is associated with the ES in string operations.

• The SI and the DI registers may also be used to access data stored in arrays

Segment RegistersSegment Registers

• Are Address registers• Store the memory addresses of instructions

and data• Memory Organization

– Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1 meg of addressable memory

Segment Registers (continued)Segment Registers (continued)

– Addresses are expressed as 5 hex digits from 00000 - FFFFF

– Problem: But 20 bit addresses are TOO BIG to fit in 16 bit registers!

– Solution: Memory Segment• Block of 64K (65,536) consecutive memory bytes• A segment number is a 16 bit number

• Segment numbers range from 0000 to FFFF• Within a segment, a particular memory

location is specified with an offset• An offset also ranges from 0000 to FFFF

Memory Model for 20-bit Address Space

• to calculate physical memory address

Memory Address Generation

Physical Address (20 Bits)

Segment Register (16 bits) 0 0 0 0

Offset Value (16 bits)

Flag RegisterFlag Register

Carry flag

Parity flag

Auxiliary flag

Overflow

Direction

Interrupt enable

Sign6 are status flags3 are control flag

8086 Addressing Modes

What is the Addressing Mode ?add dest, source ; dest +source→destadd ax,bx ; ax +bx→ax

The addressing mode means where and how the CPU gets the operands when the instruction is executed.

• Addressing modes for Sequential Control Addressing modes for Sequential Control Transfer InstructionsTransfer Instructions

--------These Instructions transfer control to the These Instructions transfer control to the next sequential instruction in the programnext sequential instruction in the program

• Addressing modes for Control TransferAddressing modes for Control Transfer InstructionsInstructions

-----These Instructions transfer control to -----These Instructions transfer control to some predefined address Ex:INT CALLsome predefined address Ex:INT CALL

Addressing modes for Sequential Control Addressing modes for Sequential Control

Transfer InstructionsTransfer Instructions Three types of 8086 addressing modes

• Immediate Addressing Mode ---CPU gets the operand from the instruction • Register Addressing Mode ---CPU gets the operand from one of the internal

registers

• Memory Addressing Mode ---CPU gets the operand from the memory location(s)

ExpMOV AL, 80HMachine code:B080H

Instruction Queue

MACHINECODE

Instruction Queue

MACHINECODE

1. Immediate Addressing Mode

MOV AX, 1234HMachine Code:B83412H

Exp ： MOV AX, CX

Memory AX

CX Machine code

2. Register Addressing Mode

• Specify an offset address (effective address) using expressions of the form (different parts of expression are optional):

– [ Base Register + Index Register+ Displacement]• 1) Base Register---BX, BP• 2) Index Register---SI, DI• 3) Displacement ---constant value• Example: 1) add ax,[20h] 2) add ax,[bx] 3) add ax,[bx+20h] 4) add ax, [bx+si] 5) add ax, [bx+si+20h]

3. Memory Addressing Mode

⑴ Direct Addressing ModeExp: MOV AL, [1064H]

Machine code:A06410H

• The offset address of the operand is provided in the instruction directly;

• The physical address can be calculated using the content of DS and the offset :

PA = (DS)*10H+Offset

⑴ Direct Addressing ModeExample: MOV AL, [1064h] ;Assume (DS)=2000HMachine code: A06410H

21064H

（ DS)*10H=20000H

20000H

21064H

CodeSegment

DataSegment

+ 1064H

⑵ Register Indirect Addressing Mode

• The address of memory location is in a register (SI,DI,or BX only)

• The physical address is calculated using the content of DS and the register(SI,DI,BX) PA = (DS)*10H+(SI)/(DI)/(BX)

……

⑵ Register Indirect Addressing Mode ASSUME: (DS)=3000H, (SI)=2000H, (BX)=1000H

30000H

(DS)*10H=30000H(SI)= 2000H+

32000H

……

AL 30000H

(DS)*10h= 30000H (BX)= 1000H+

31000H

31000H64H

MOV [BX], ALMOV AX, [SI]

⑶ Register Relative Addressing

(BX)(BP)(DI)(SI)

+ Displacement

For physical address calculation: DS is used for BX,DI,SI; SS is used for BP

PA=(DS)*10H+(BX)/(DI)/(SI)+DispOR

PA=(SS)*10H+(BP)+Disp

⑶ Register Relative AddressingMOV CL, [BX+1064H] ;assume: (DS)=2000h, (bx)=1000h ;Machine Code: 8A8F6410

22064H

CodeSegment

DataSegment

45 21000H

(BX)= 1000H

(DS)*10h= 20000H

20000H

+ 1064H

PA=(ds)*10h+(bx)+1064hPA=(ds)*10h+(bx)+1064h

⑷ Based Indexed Addressing

EA=(BX)(BP) +

(DI)(SI)

• Base register(bx or bp) determines which segment(data or stack) the operand is stored;• if using BX, the operand is defaultly located in Data segment,then: PA=(DS)*10H+(BX)+(DI)/(SI)

• if using BP, the operand is defaultly located in stack segment,then: PA=(SS)*10H+(BP)+(DI)/(SI)

⑷ Based Indexed Addressing

Example: MOV AH, [BP][SI];Assume(ss)=4000h,(bp)=2000h,(si)=1200h

……

AH 40000H

(SS)*10H= 40000H(BP)= 2000H

43200H

(SI)= 1200H

PA=(ss)*10h+(bp)+(si)PA=(ss)*10h+(bp)+(si)

⑸ Based Indexed Relative Addressing

EA=(BX)(BP) +

(DI)(SI) + Displacement

if using BX, the operand is defaultly located in Data segment,then: PA=(DS)*10H+(BX)+(DI)/(SI)+disp

if using BP, the operand is defaultly located in stack segment,then: PA=(SS)*10H+(BP)+(DI)/(SI)+disp

⑸ Based Indexed Relative Addressing MOV [BX+DI+1234H], AH

;assume (ds)=4000h,(bx)=0200h,(di)=0010h;machine code:88A13412h

Codesegment

Datasegment

40000H

(DS)*10H=40000H(BX)= 0200H

(DI)= 0010H 1234H

41444H

Summary on the 8086 memory addressing modes

operand offset address Default Overridden （ effective address ） Segment Register Segment Register

3. Register [SI/DI/BX/BP+disp] (SI)/(DI)/(BX)/(BP)+disp DS CS ES SS Relative Addressing

2. Register [BX]/[SI] /[DI] Content of the R DS CS ES SS Indirect Addressing

1. Direct Addressing [disp] disp DS CS ES SS

4. Based Indexed [BX+SI/DI] (BX)+disp DS CS ES SS Addressing [BP+SI/DI] (BP)+disp SS CS ES DS

5. Based Indexed [BX+SI/DI+disp] (BX)+(SI)/(DI)+disp DS CS ES SS Relative Addressing [BP+SI/DI+disp] (BP)+(SI)/(DI)+disp SS CS ES DS

Examples:Assume: (BX)=6000H, (BP)=4000H, (SI)=2000H, (DS)=3000H, (ES)=3500H, (SS)=5000H

3000:0520 30520HDirect Addressing

2. MOV AX, [BX]

1. MOV AX, [0520H]

5. MOV AX, ES: [BX+SI+0050H]

4. MOV AX, [BP+6060H]

Register Indirect Addressing 3000:6000 36000H

Register Relative Addressing

3. MOV AX, [SI+1000H] 3000:3000 33000H

5000:A060 5A060H

3500:8050 3D050HBased Indexed Relative Addressing

Instruction Instruction addressingaddressing logical logical physical physical modemode address address address address

•Addressing modes for Control Transfer Addressing modes for Control Transfer InstructionsInstructions

Modes for Control Modes for Control Transfer InstructionsTransfer Instructions

Inter-segmentInter-segment

Intra-segmentIntra-segment

Inter-segment-In DirectInter-segment-In Direct

Inter-segment-DirectInter-segment-Direct

Intra-segment DirectIntra-segment Direct

Intra-segment IndirectIntra-segment Indirect

Inter-segment-Direct Addressing ModeInter-segment-Direct Addressing ModeThe address to which control is to be transferred lies in the different The address to which control is to be transferred lies in the different segment and appears directly In the instruction as an immediate segment and appears directly In the instruction as an immediate displacement value w.r.t IP If the displacement is displacement value w.r.t IP If the displacement is 8-bits(-128<d<+127)(short) If the displacement is 8-bits(-128<d<+127)(short) If the displacement is 16-bits(-32768<d<+32767)(Long)16-bits(-32768<d<+32767)(Long)

Ex: CALL 0020:0010HEx: CALL 0020:0010H

segment1

Assume CS=2000h,IP=0000hAssume CS=2000h,IP=0000h

After JMP,CS= 0020h,IP=0010hAfter JMP,CS= 0020h,IP=0010h

segment2

Sub-routine

Op-code for CALL

2000hCS

Inter-segment-IN-Direct Addressing ModeInter-segment-IN-Direct Addressing ModeThe address to which control is to be transferredThe address to which control is to be transferred lies in the different \segment and it is passed to lies in the different \segment and it is passed to thethe instruction indirectly i.e contents of a memory instruction indirectly i.e contents of a memory blockblock containing four bytes containing four bytes IP(LSB),IP(MSB),CS(LSB),CS(MSB)IP(LSB),IP(MSB),CS(LSB),CS(MSB)

Ex: CALL [BX]Ex: CALL [BX]

IP(LSB)10

IP(MSB)00

CS(LSB)20

Sub-routine

segment1

0020CS

Before JMP,Assume BX=100h, CS=3000h,IP=200hBefore JMP,Assume BX=100h, CS=3000h,IP=200h

Op-code for CALL

After JMP,CS= 0020h,IP=0010hAfter JMP,CS= 0020h,IP=0010h

segment2

0010IP

3000hCS

CS(MSB)00

0010IP

Intra-segment-Direct Addressing ModeIntra-segment-Direct Addressing ModeThe address to which control is to be transferred lies in the sameThe address to which control is to be transferred lies in the samesegment and appears directly In the instruction as an immediate segment and appears directly In the instruction as an immediate displacement value w.r.t IP If the displacement is displacement value w.r.t IP If the displacement is 8-bits(-128<d<+127)(short) If the displacement is 8-bits(-128<d<+127)(short) If the displacement is 16-bits(-32768<d<+32767)(Long)16-bits(-32768<d<+32767)(Long)

Ex: CALL 500hEx: CALL 500h

CodeSegment

Assume CS=2000h,IP=0000hAssume CS=2000h,IP=0000h

After CALL,CS= 2000h,IP=IP+500hAfter CALL,CS= 2000h,IP=IP+500h

Op-code for CALL2000hCS

0500Sub-routine

0000IP

Intra-segment-In-Direct Addressing ModeIntra-segment-In-Direct Addressing ModeIn this mode the displacement to which control is to be transferred,In this mode the displacement to which control is to be transferred,Is in the same segment in which the control transfer instruction liesIs in the same segment in which the control transfer instruction liesBut it is passed to the instruction indirectlyBut it is passed to the instruction indirectly

Ex: CALL [BX]Ex: CALL [BX]

CodeSegment

Assume CS=2000h,IP=0000h , BX=800hAssume CS=2000h,IP=0000h , BX=800h

After CALL,CS= 2000h,IP=IP+800hAfter CALL,CS= 2000h,IP=IP+800h

Op-code for CALL2000hCS

0800Sub-routine

0000IP

Example:Example:

The Contents of different registers are given below. Form effective addresses for The Contents of different registers are given below. Form effective addresses for different addressing modesdifferent addressing modesOffset(displacement)= 5000HOffset(displacement)= 5000HAX=1000H,BX=2000H,SI=3000H,DI=4000H,BP=5000H,SP=6000H,CS=0000H,DS=1000HAX=1000H,BX=2000H,SI=3000H,DI=4000H,BP=5000H,SP=6000H,CS=0000H,DS=1000HSS=2000H,IP=7000HSS=2000H,IP=7000HShifting a number four times is equivalent to multiplying it by 16Shifting a number four times is equivalent to multiplying it by 16D D or 10 or 10HH

Instruction Set &

Assembler Directives

Programming in 8088/8086

Three levels of languages available to program a microprocessor:

Machine Languages, Assembly Languages, and High-level Languages.

Machine Language

A sequence of binary codes for the instruction to be executed by

microcomputers.

Long binary bits can be simplified by using Hexadecimal format

It is difficult to program and error prone.

Different uP (micro-processor) uses different machine codes.

Programming in 8088/8086 (cont.)

Assembly Language

To simplify the programming, assembly language (instead of machine language) is used.

Assembly language uses 2- to 4-letter mnemonics to represent each instruction type. E.g. “Subtraction” is represented by SUB

Four fields in assembly language statement:

Label, OP Code, Operand and Comment fields.

Programs will be ‘translated’ into machine language, by Assembler, so it can be loaded into memory for execution.

High-Level Language

High level languages, like C, Basic or Pascal, can also be used to program

microcomputers.

An interpreter or a compiler is used to ‘translate’ high level language statement to machine code. High level language is easier to read by human and is more suitable when the programs involves complex data structures.

Assemblers

Programming the instructions directly in machine code is possible but every machine codes depending on how the data is stored.

The process of converting the microprocessor instructions to the binary machine code can be performed automatically by a computer program, called an ASSEMBLER. Popular assemblers include IBM macro Assembler, Microsoft Macro Assembler (MASM) and Borland Turbo Assembler(installed on IE NT Network).

Most assemblers accept an input text file containing lines with a rigorously defined syntax split into four fields.

Not all fields need to be present in a line. Eg. A line can be just a comment line if it starts with semicolon;

Source Codes, Object Codes and Linking

Source code is the text written by the programmer in assembly language

(or any other programming language)

Object code is the binary code obtained after running the assembler (

Or compiler if the source is in a high level language).

Modules of a program may be written separately and linked together to

form a executable program using a linker.

The linker joins the object code of the different modules into one large

object file which is executable. Most assemblers on IBM PCs produce

object files which must be linked ( even if there are no separate modules).

Source Codes, Object Codes and Linking(Contd.,)

Fields in Assembler

Comment field contains internal program documentation to improve

human readability -use meaningful comments

Operand field contains data or address used by the instruction.

The following conventions typically apply:

Fields in Assembler (Contd.,)

Mnemonic/directive field contains the abbreviation for the processor instruction (eg. MOV) or an assembler DIRECTIVE. Adirective produces no object code but is used to control how the assembler operates.

Examples of directives include:

END -indicate the end of a program listing,

FRED LABEL NEAR - define “FRED” as a near label

TOM EQU 1000H -define “TOM” as the number 1000H

Label field contains a label which is assigned a value equal to the address where the label appears.

Why Program in Assembler?

Assembler language instruction has a one-to-one correspondence with the binary machine code: the programmer controls precisely all the operations performed by the processor (a high level language relies on a compiler or interpreter to generate the instructions).

Assembler can generate faster and more compact programs

Assembler language allows direct access and full control of input/output operations

However, high-level language programs are easier to write and develop than assembler language programs

Advantages of High-level languages

Block structure code: programs are most readable when they are

broken into “logical blocks” that perform specific function.

Productivity: easier to program

Level of complexity: no need to know the hardware details

Simple mathematics formula statement

Portability: only need to change the compiler when it is ported to other machine

Abstract data types: different data types like floating-point value,

record and array, and high precision value.

Readability

Intel 8086 Instruction Set Overview

Intel 8088 has ninety basic ( ie not counting addressing mode

variants) instructions

Instructions belong to one of the following groups: data

transfer, arithmetic, logic, string manipulation, control

transfer and processor control.

Converting Assembly Language Instructions to Machine Code

• An instruction can be coded with 1 to 6 bytes

• Byte 1 contains three kinds of information– Opcode field (6 bits) specifies the operation (add, subtract, move)

– Register Direction Bit (D bit) Tells the register operand in REG field in byte 2 is source or destination operand

1: destination 0: source

-Data Size Bit (W bit) Specifies whether the operation will be performed on 8-bit or 16-bit data

0: 8 bits 1: 16 bits

• Byte 2 has three fields– Mode field (MOD)

– Register field (REG) used to identify the register for the first operand

– Register/memory field (R/M field)

2-bit MOD field and 3-bit R/M field together specify the second operand

Mode Field encoding

Register/memory (R/M) Field Encoding

Examples

MOV BL,AL (88C316)Opcode for MOV = 100010D = 0 (AL source operand)W bit = 0 (8-bits)

Therefore byte 1 is 100010002=8816

• MOD = 11 (register mode)• REG = 000 (code for AL)• R/M = 011 (destination is BL)

Therefore Byte 2 is 110000112=C316

Examples:MOV BL, AL = 10001000 11000011 = 88 C3h

ADD AX, [SI] = 00000011 00000100 = 03 04 h

ADD [BX] [DI] + 1234h, AX = 00000001 10000001 __ __ h = 01 81 34 12 h

Intel 8086 Instruction Set Overview

(abbreviations below: d=destination, s=source)

General Data Movement Instructions

MOV d,s - moves byte or word; most commonly used instruction

PUSH s - stores a word (register or memory) onto the stack

POP d - removes a word from the stack

XCHG d,s - exchanges data, reg.-reg. Or memory to register

XLAT - translates a byte using a lookup table (has no operands)

IN d,s - moves data (byte or word) from I/O port to AX or AL

OUT d,s - moves data (byte or word) from AX or AL to I/O port

LEA d,s - loads effective address (not data at address) into register

LDS d,s - loads 4 bytes (starting at s) to pointer (d) and DS

LES d,s - loads 4 bytes (starting at s) to pointer (d) and ES

LAHF - loads the low-order bytes of the FLAGS register to AH

SAHF - stores AH into the low-order byte of FLAGS

PUSHF - copies the FLAGS register to the stack

POPF - copies a word from the stack to the FLAGS register

I. Data Movement Instructions (14)

Instructions for moving strings

String instructions are repeated when prefixed by the REP mnemonic (CX contains the repetition count)

MOVS d,s - (MOVSB, MOVSW) memory to memory data transfer

LODS s - (LODSB and LODSW) copies data into AX or AH

STOS d - (STOSB, STOSW) stores data from AH or AX

Data movement using MOV

MOV d, s

d=destination (register or effective memory address),

s=source (immediate data, register or memory address)

MOV can transfer data from:

any register to any register (except CS register)

memory to any register (except CS)

immediate operand to any register (except CS)

any register to a memory location

immediate operand to memory

MOV cannot perform memory to memory transfers (must use a register as an intermediate storage).

MOV moves a word or byte depending on the operand bit-lengths; the source

and destination operands must have the same bit length.

MOV cannot be used to transfer data directly into the CS register.

The stackThe stack

The stack is a block of memory reserved for temporary storage of data and registers. Access is LAST-IN, FIRST OUT (LIFO)

The last memory location used in the stack is given by the effective

address calculated from the SP register and the SS register:

Example:

The stack

Data may be stored onto the stack using the PUSH instruction –this automatically decrements SP by 2 (all stack operations involve words).

The POP instruction removes data from the stack (and increments SP by 2).

The stack may be up to 64K-bytes in length.

PUSH and POP instructions

Examples:

PUSH AX ;stores AX onto the stack

POP AX ;removes a word from the stack and loads it into AX

PUSHF ;stores the FLAGS register onto the stack

POPF ; removes a word from the stack and loads it into FLAGS

PUSH may be used with any register to save a word (the register contents) onto the stack. The usual order (e.g. as with MOV) of storing the lower order byte in the lower memory location is used.

PUSH may also be used with immediate data, or data in memory.

POP is the inverse of the PUSH instruction; it removes a word from the top of the stack. Any memory location or 16-bit register (except CS) may be used as the destination of a POP instruction.

PUSHF and POPF saves and loads the FLAGS register to/from the stack,respectively.

Exchange Instruction (XCHG)

XCHG exchanges the contents of two registers or a register and memory. Both byte and word sized exchanges are possible.

Examples:

XCHG AX,BX; exchange the contents of AX and BX

XCHG CL,BL; exchange CL and BL contents

XCHG DX,FRED; exchanges content of DX and memory

DS:FRED

Memory to Memory exchanges using XCHG are NOT allowed.

Translate Instruction (XLAT)

Many applications need to quickly convert byte sized codes to other values mapping one byte value to another (e.g. mapping keyboard binary codes to ASCII code)

XLAT can perform a byte translation using a look-up table containing up to 256 elements

XLAT assumes that the 256-byte table starts at the address given by DS:BX (i.e. effective address formed by the DS and BX registers). AL is used as an index to point to the required element in the table prior to the execution of XLAT. The result of XLAT instruction is returned in the same register (AL). Address Data TableAddress Data Table

LEA &LDS

LEA loads the offset of a memory address into a 16-bit register. The offset address may be specified by any of the addressing modes.

Examples (with BP=1000H):

LEA AX,[BP+40H];=>SS:[1000H+40H] =SS:[1040H];load 1040H into AX

LEA BX,FRED; load the offset of FRED (in data segment) to BX

LEA CX,ES:FRED; loads the offset of FRED (in extra segment) to CX

LDS -Load data and DS

LDS reads two words from the consecutive memory locations and loads them into the specified register and the DS segment registers.

Examples (DS=1000H initially)

LDS BX,[2222H]; copies content of 12222H to BL, 12223H to BH, and 12224 and 12225 to DS register

LDS is useful for initializing the SI and DS registers before a string operation. E.g. LDS SI, sting_pointer

The source for LDS can be displacement, index or pointer register (except SP).

LES -Load data and ES

LES reads two words from memory and is very similar to LDS except that the second word is stored in ES instead of DS.

LES is useful for initializing that DI and ES registers for strings operation.

Example (with DS=1000H):

LES DI, [2222H]; loads DI with contents stored at 12222H and 12223H and loads ES with contents at 12224 and 12225H

LAHF, SAHF

LAHF (load AH with the low-order byte of the FLAGS register) and SAHF (Store AH into the low-order byte of the FLAG register)

very rarely used instructions -originally present to allow translation of 8085 programs to 8086.

IN, OUT

Examples:

IN AX, 0C8h ;reads port address at C8h (8 bit address) and loads into AX

IN AL, DX ;reads the port address given by DX and loads into AL

OUT p8 ,AX ;sends the data in AX to port p8

OUT DL, AX ; sends the data in AX to port given by DL

IN reads data from the specified IO port (8-bit or 16-bit wide) to the accumulator (

AL or AX).

The IO port can be an immediate address (8-bit only) or specified by a variable

or register (8 or 16-bit address). (Seems only DX can be used.)

OUT sends data from the accumulator register to the specified I/O port. Both byte and word sized data may be sent using IN and OUT.

II. Arithmetic Instructions(20)II. Arithmetic Instructions(20)

Intel 8088 has 20 instructions for performing integer addition,Intel 8088 has 20 instructions for performing integer addition,Subtraction , multiplication, division, and conversions from binary coded decimal to binary.Subtraction , multiplication, division, and conversions from binary coded decimal to binary.

Arithmetic Instructions (cont.)Arithmetic Instructions (cont.)

AdditionAddition

Binary addition of two bytes or two words are performed using:Binary addition of two bytes or two words are performed using:ADD d,sADD d,s

ADD adds bytes or words in d and s and stores ADD adds bytes or words in d and s and stores result in d.result in d.The operands d and s can use the same addressing modes as in MOV.The operands d and s can use the same addressing modes as in MOV. Addition of double-word is achieved by using the carry bit in the FLAGS register. The Addition of double-word is achieved by using the carry bit in the FLAGS register. The instructioninstruction

ADC d,sADC d,sautomatically includes the carry flag, and is used to add the more significant word in a automatically includes the carry flag, and is used to add the more significant word in a

double-word addition.double-word addition.

AdditionExample: addition of two double words stored at [x] and [y]MOV AX, [x] ; Loads AX with the word stored at location [x]MOV DX, [x+2] ; Loads the high order wordADD AX, [y] ; Adds the low order word at [y]ADC DX, [y+2] ; Add including the carry from the low order words

Addition (cont.)Addition (cont.)

Example: addition of two double words stored at [x] and [y]Example: addition of two double words stored at [x] and [y]

Addition of binary coded decimal numbers (BCD) can be performed by using ADD Addition of binary coded decimal numbers (BCD) can be performed by using ADD or ADC followed by the DAA instruction to convert theor ADC followed by the DAA instruction to convert thenumber in register AL to a BCD representation. (see example)number in register AL to a BCD representation. (see example)

Addition of numbers in their ASCII form is achieved by using AAA (ascii adjust Addition of numbers in their ASCII form is achieved by using AAA (ascii adjust after addition).after addition).

ASCII adjust for Addition (AAA)

ASCII codes for the numbers 0 to 9 are 30H to 39H respectively. The ascii adjust instructions convert the sum stored in AL to two-byte unpack BCD number which are placed in AX. When 30H is added to each byte, the result is the ASCII codes of the digits representing the decimal for the original number in AL.Example: Register AL contains 31H (the ASCII code for 1), BL contains 39H (the ASCII code for 9).ADD AL, BL ; produces the result 6AH which is kept in AL.AAA ; converts 6AH in AL to 0100H in AXAddition of 30H to each byte of AX produces the result 3130H (the ASCII codefor 10 which is the result of 1+9)

Subtraction

Multiplication

Division

SIGN EXTENDED INSTRUCTIONS

Other Arithmetic Instructions

III. Logic and bit MANIPULATION Instructions (12)

III. Logic and bit MANIPULATION Instructions (12) (Contd)

Shift and Rotate

Shift and Rotate(Contd)

List file of 8086 assembly language program to produce packed BCD from two ASCII characters

IV. Strings Instruction (6)

IV. Instruction for moving strings(Contd)

REP prefix

LODS and STOS string instructions

LODS and STOS string instructions(Contd)

CMPS and SCAS string instructions

V. Program Flow Instruction

Program Flow Instruction

Unconditional JUMP

Unconditional JUMP (cont.)

List file of program Demonstrating “backward” JMP

List file of program demonstrating “forward” JMP

Conditional Jumps

8086 Conditional Jump Instructions

Ex.: Reading ASCII code when a strobe is present

Assembly language for Reading ASCII code when a strobe is present

Procedures and modular Programming

Procedures and modular Programming (Contd)

Procedures

Stack Diagram

Using PUSH and POP instructions

Interrupt Instructions

• Assembler directives for data storage– DB - byte(s)– DW - word(s)– DD - doubleword(s)– DQ - quadword(s)– DT - tenbyte(s)

Program Data and Storage

Arrays• Any consecutive storage locations of the

same size can be called an arrayX DW 40CH,10B,-13,0

Y DB 'This is an array'

Z DD -109236, FFFFFFFFH, -1, 100B• Components of X are at X, X+2, X+4, X+8• Components of Y are at Y, Y+1, …, Y+15• Components of Z are at Z, Z+4, Z+8, Z+12

DUP• Allows a sequence of storage locations to

be defined or reserved• Only used as an operand of a define

directiveDB 40 DUP (?)

DW 10h DUP (0)

DB 3 dup ("ABC")

db 4 dup(3 dup (0,1), 2 dup('$'))

Word Storage• Word, doubleword, and quadword data are

stored in reverse byte order (in memory)Directive Bytes in Storage

DW 256 00 01

DD 1234567H 67 45 23 01

DQ 10 0A 00 00 00 00 00 00 00

X DW 35DAh DA 35Low byte of X is at X, high byte of X is at X+1

EQU Directive• name EQU expression

– expression can be string or numeric– Use < and > to specify a string EQU– these symbols cannot be redefined later in the

programsample EQU 7Fh

aString EQU <1.234>

message EQU <This is a message>

Macro definition: name MACRO [parameters,...] <instructions> ENDM

MyMacro MACRO p1, p2, p3 MOV AX, p1 MOV BX, p2 MOV CX, p3 ENDM ORG 100h MyMacro 1, 2, 3 MyMacro 4, 5, DX RET

The syntax for procedure declaration: name PROC

; here goes the code ; of the procedure ...

RETname ENDP

ORG 100h CALL m1 MOV AX, 2 RET ; return to Main Program. m1 PROCMOV BX, 5RET ; return to caller.m1 ENDP END

ORG 100h MOV AL, 1MOV BL, 2 CALL m2CALL m2CALL m2CALL m2 RET ; return to operating system. m2 PROCMUL BL ; AX = AL * BL.RET ; return to caller.m2 ENDP END

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