Hierachical structural modeling

HanbatHanbat

NationalNational

UniversityUniversityHanbatHanbat

NationalNational

UniversityUniversity

Hierarchical Structural Hierarchical Structural ModelingModeling

Hierarchical Structural Hierarchical Structural ModelingModeling

Gookyi Dennis A. N.Gookyi Dennis A. N.

SoC Design Lab.SoC Design Lab.

June.20.2014

ContentsContents Module Generate Statements

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Module Module The basic units of Verilog HDL are modules A module has two major parts:

The interfaceThe body

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Module Module A module is defined by using the keyword module

and has various forms as below:

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Parameters Parameters Parameters are constants which can be used

throughout the module defining them They are used to specify delays and width of

variables There are two types of parameters:

Module parameter Specify parameter

The module parameters can be defined by using the following keywords within the module:

Parameter localparam

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Parameter DeclarationParameter Declaration The parameter is used to define module parameters

that can be overridden by defparam or module instance parameter value assignment

It has the forms as below:parameter [signed] [range] param_assignmentparameter var_types param_assignment

Some examples of the usage of parameter is as below:parameter SIZE =7;parameter WIDTH_BUSA = 24, WIDTH_BUSB = 8;parameter signed [3:0] mux_selector = 4’b0;

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Localparam DeclarationLocalparam Declaration It is used to define parameters local to a module It cannot be overridden by the defparam statement

or by module instance parameter value assignment The following are some examples of the usage of

localparam:localparam SIZE =7;localparam WIDTH_BUSA = 24, WIDTH_BUSB = 8;localparam signed [3:0] mux_selector = 4’b0;

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Parameter PortsParameter Ports A parameter can be placed between module name

and port list or port list declarations A parameter can have both the type and range

specifications as shown below:module module_name#(parameter SIZE =7,parameter WIDTH_BUSA = 24, WIDTH_BUSB = 8,parameter signed [3:0] mux_selector = 4’b0)(port list or port list declaration) …endmodule

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Module InstantiationModule Instantiation Modules cannot be nested, however, a module can

incorporate a copy (called an instance) of another module into itself through instantiations

The syntax is as below:module_name[#(parameters)]instance_name[range]([ports]);

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Port Connection RulesPort Connection Rules Connecting ports to external signals can be done by:

Named association: ports are connected by listing their names. The form is as follows:.port_id1(port_expr1),…, .port_idn(port_exprn)

Positional association: ports are connected by ordered list of ports, each corresponding to a port. It has the following form:port_expr1, …, port_exprn

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Module Parameter ValueModule Parameter Value When a module instantiates other modules, the

higher-level module can change the values of parameters defined by the keyword parameter in the lower-level modules

An example is shown below:

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Module Parameter ValueModule Parameter Value Waveform and RTL schematic:

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Module Parameter ValueModule Parameter Value There are two ways to override parameter values:

Defparam statementModule instance parameter value assignment

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Using The Using The defparamdefparam StatementStatement It is used to redefine the parameter values defined by

the keyword parameter Its syntax is as below:

defparam hierarchical_path_name1 = value1, hierarchical_path_name2 = value2, … hierarchical_path_namen = valuen;

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Using The defparam Using The defparam StatementStatement An example is a parameter adder. Here there is the

instantiation of two adder modules using the defparam statement

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Using The defparam Using The defparam StatementStatement Waveform

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Using The defparam Using The defparam StatementStatement RTL schematic

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Module Instance ParameterModule Instance Parameter The parameters defined by using the keyword

parameter within a module are overridden by parameters passed through parameters ports whenever the module is instantiated

There are two approaches:Positional associationNamed association

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Module Instance Parameter: Module Instance Parameter: Positional AssociationPositional Association In this form the order of the assignment must follow

the order of declaration of the parameters within the module

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Module Instance Parameter: Module Instance Parameter: Positional AssociationPositional Association Waveform

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Module Instance Parameter: Module Instance Parameter: Positional AssociationPositional Association RTL schematic

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Module Instance Parameter: Module Instance Parameter: Named AssociationNamed Association It explicitly links the names specified in the

instantiated module and the associated value

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Module Instance Parameter: Module Instance Parameter: Named AssociationNamed Association Waveform

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Module Instance Parameter: Module Instance Parameter: Named AssociationNamed Association RTL schematic

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Generate StatementGenerate Statement Generate statement allows selection and replication

of some statements during elaboration time Elaboration time is the time after a design has been

parsed but before simulation begins The generate statement has the syntax as below:

generateGenerate-declarationGenerate-loop statementsGenerate-conditional statementsGenerate-case statement …

endgenerate

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Generate StatementGenerate Statement The power of generate statements is that they can

conditionally generate declarations and instantiations into a design

There are three kinds of statements that can be used within a generate statement:

Generate-loopGenerate-conditionalGenerate-case

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Generate-loop StatementGenerate-loop Statement It is formed by using a for statement within a

generate statement The generate loop is of the form:

for (init_expr; condition_expr; update_expr) Begin: block_name Generate_statements

end An index variable is always declared when using the

for statement within a generate statement The index variable is declared as follows

genvar genvar_id1, … genvar_idn;

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Generate-loop StatementGenerate-loop Statement An example is the use of continuous assignment

within a generate-loop for converting gray code into binary code

To convert gray code into binary code, we may count the number of 1’s from MSB to the current position

If it is odd, the binary bit is 1 Otherwise, the binary bit is 0

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Generate-loop StatementGenerate-loop Statement Code for converting gray code to binary code

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Generate-loop StatementGenerate-loop Statement During elaboration time, the generate-loop is

expanded The body of the for statement is replicated once for

each value of the iteration as follows:assign bin[0] = ^gray[SIZE-1:0];assign bin[1] = ^gray[SIZE-1:1];assign bin[2] = ^gray[SIZE-1:2];assign bin[3] = ^gray[SIZE-1:3];assign bin[4] = ^gray[SIZE-1:4];assign bin[5] = ^gray[SIZE-1:5];assign bin[6] = ^gray[SIZE-1:6];assign bin[7] = ^gray[SIZE-1:7];

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Generate-loop StatementGenerate-loop Statement Waveform

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Generate-loop StatementGenerate-loop Statement RTL schematic

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Generate-conditional Generate-conditional StatementStatement Allows modules, gate primitives, continuous

assignments etc. to be instantiated into another module based on an if-else conditional expression

It has the form as below:if (condition) generate_statements [else generate_statements]

if (condition) generate_statements [else if (condition2) generate_statements] [else generate_statements]

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Generate-conditional Generate-conditional StatementStatement An example of generate-conditional statement is

given Here, if-else is employed to set up the boundary cells,

the LSB and the MSB of an n-bit adder

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Generate-conditional Generate-conditional StatementStatement Code

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Generate-conditional Generate-conditional StatementStatement Testbench

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Generate-conditional Generate-conditional StatementStatement Technology schematic

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Generate-Case StatementGenerate-Case Statement Allows modules, gate primitives, continuous

assignments etc. to be instantiated into another module based on the case conditional expression

Its general form is as follows:Case (case_expr)

Case_item1: generate_statements …Case_itemn: generate_statements

[default: generate_statement]

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Generate-Case StatementGenerate-Case Statement An example of is used to model an n-bit adder:

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Generate-Case StatementGenerate-Case Statement Waveform

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Generate-Case StatementGenerate-Case Statement Technology schematic

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