Aicd cmos layouts

Analog IC Design BITS PilaniPilani Campus ANU GUPTAp

BITS PilaniBITS PilaniPilani Campus

Analog Layout Techniques

Organisation

• Design rules, Schematic to layout, vice versa,

• cross-sectional diagram, big layouts

• Matched componentsp

Over-etching errors

unit components designunit components design

design using non unit component

Boundary condition matching Boundary condition matching

Common centroid layout, parasitic cap estimation

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Scalable design rules-----same set can be used for next tech generation by changing λ. Worst case values of spacings, widths etc. are used , so can’t be an optimized set. e. g. MOSIS design rulesg g

Absolute design rules----optimized set but same set can’t be used for next tech gen. Entire new set is to be created.

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Tanner

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4 NAND GATES4 NAND GATES

CADENCE

MOS LAYOUT

λλ 2λ

2λ

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λ

5λ

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Junction cap-single transistorsingle transistor

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Other layouts of MOS

Annular transistor

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Elongated annular transistor

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Dense MOS layouts

metal1metal1

metal2

B t t i t

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Waffle transistor Bent transistor

Compute w/L?

Circuit And Layout

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Try more examples

How to reduce parasitic capacitances?

Careful layout by junction sharing

CAPACITOR LAYOUTS

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RESISTOR LAYOUT

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Matching Issues

Large device => many small unit devicesg y

Same boundary conditions for devices

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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Overetching –MOS dimensions

(W/L)u = 8um/2um= 4 desired

MOS dimensions

After over etching ---(W/L)u = 7um/1um= 7; 0.5um= ∆e

LL

∆e

Poly layer

w Over etched Poly layer

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Absolute dimension of MOSRemedy---use Unit components w=L

(W/L)u = 10um/10um, RATIO=1

Remedy---use Unit components w=L

After fab. (W/L)u 8um/8um, RATIO=1

Conclusion—Abs. dimensions change, ratio does not changechange

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Ratio of matched devices

• (W/L)1 = 2, (W/L)2 = 8, ratio= 4

Ratio of matched devices

( )1 , ( )2 ,• We take unit device (W/L)u = 10um/10um• After fab. (W/L)u 8um/8um( )u

(W/L)2 8(W/L)u 4( )2 ( )u(W/L)1 2(W/L)u

= =4

Thus, ratio remains same, if same unit device is used

Application of technique

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS PilaniBITS PilaniPilani Campus

Layout of CAPACITORSLayout of CAPACITORS

CAPACITOR LAYOUTS

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Over-Etching

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

LetC1/ C2 = 3.4 = 2+1.4= [6/3] + [1.4/1] [6/3] [1.4/1]

[6/3]---can be implemented by using unit[6/3]---can be implemented by using unit capacitors

[1 4/1]---we require non unit capacitor[1.4/1]---we require non unit capacitorMismatch can occur due to second term

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No mismatch conditionNo mismatch condition

• We should design non unit cap Such thatWe should design non unit cap. Such that ratio (1.4) remains constant even after overetchingoveretching

H t d i ?• How to design?• What is the condition?

Condition

= c1c2c

εr1= εr2

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Non unit sized cap dim. estimation

= 1 4

estimation

= 1.4

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Boundary condition matchingBoundary condition matchingCommon centroid layout

What if unit devices change randomly?g y

Since one device is facing larger change in dimension, g g gmaintaining constant ratio would be difficult.

So We should have same change in all unit devices how?So, We should have same change in all unit devices. how?Inter-digitization

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Reduce mismatches

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

D DD

S

SSS S

Bulk (backgate contact)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

RESISTOR LAYOUT

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Big Resistor

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BIG RESISTOR (unit components)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Multi fingered Common Centroid layoutCommon Centroid layout

Parasitic cap. calculation of MOS device

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20λ 6λ 6λ 6λ

5λ 5λ

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Fingered layout

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View of fingered layout

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